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26 /** @file intel_mipmap_tree.h
28 * This file defines the structure that wraps a BO and describes how the
29 * mipmap levels and slices of a texture are laid out.
31 * The hardware has a fixed layout of a texture depending on parameters such
32 * as the target/type (2D, 3D, CUBE), width, height, pitch, and number of
33 * mipmap levels. The individual level/layer slices are each 2D rectangles of
34 * pixels at some x/y offset from the start of the brw_bo.
36 * Original OpenGL allowed texture miplevels to be specified in arbitrary
37 * order, and a texture may change size over time. Thus, each
38 * intel_texture_image has a reference to a miptree that contains the pixel
39 * data sized appropriately for it, which will later be referenced by/copied
40 * to the intel_texture_object at draw time (intel_finalize_mipmap_tree()) so
41 * that there's a single miptree for the complete texture.
44 #ifndef INTEL_MIPMAP_TREE_H
45 #define INTEL_MIPMAP_TREE_H
49 #include "main/mtypes.h"
51 #include "blorp/blorp.h"
52 #include "brw_bufmgr.h"
53 #include <GL/internal/dri_interface.h>
60 struct intel_renderbuffer
;
62 struct intel_texture_image
;
65 * This bit extends the set of GL_MAP_*_BIT enums.
67 * When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
68 * depthstencil-split-to-separate-stencil miptree, we'll normally make a
69 * temporary and recreate the kind of data requested by Mesa core, since we're
70 * satisfying some glGetTexImage() request or something.
72 * However, occasionally you want to actually map the miptree's current data
73 * without transcoding back. This flag to intel_miptree_map() gets you that.
75 #define BRW_MAP_DIRECT_BIT 0x80000000
77 struct intel_miptree_map
{
78 /** Bitfield of GL_MAP_*_BIT and BRW_MAP_*_BIT. */
80 /** Region of interest for the map. */
82 /** Possibly malloced temporary buffer for the mapping. */
84 /** Possible pointer to a temporary linear miptree for the mapping. */
85 struct intel_mipmap_tree
*linear_mt
;
86 /** Pointer to the start of (map_x, map_y) returned by the mapping. */
88 /** Stride of the mapping. */
93 * Describes the location of each texture image within a miptree.
95 struct intel_mipmap_level
97 /** Offset to this miptree level, used in computing x_offset. */
99 /** Offset to this miptree level, used in computing y_offset. */
103 * \brief Is HiZ enabled for this level?
105 * If \c mt->level[l].has_hiz is set, then (1) \c mt->hiz_mt has been
106 * allocated and (2) the HiZ memory for the slices in this level reside at
107 * \c mt->hiz_mt->level[l].
112 * \brief List of 2D images in this mipmap level.
114 * This may be a list of cube faces, array slices in 2D array texture, or
115 * layers in a 3D texture. The list's length is \c depth.
117 struct intel_mipmap_slice
{
119 * Mapping information. Persistent for the duration of
120 * intel_miptree_map/unmap on this slice.
122 struct intel_miptree_map
*map
;
127 * Miptree aux buffer. These buffers are associated with a miptree, but the
128 * format is managed by the hardware.
130 * For Gen7+, we always give the hardware the start of the buffer, and let it
131 * handle all accesses to the buffer. Therefore we don't need the full miptree
132 * layout structure for this buffer.
134 struct intel_miptree_aux_buffer
136 struct isl_surf surf
;
139 * Buffer object containing the pixel data.
141 * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
142 * @see 3DSTATE_HIER_DEPTH_BUFFER.AuxiliarySurfaceBaseAddress
147 * Offset into bo where the surface starts.
149 * @see intel_mipmap_aux_buffer::bo
151 * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
152 * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
153 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
154 * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
159 * Size of the MCS surface.
161 * This is needed when doing any gtt mapped operations on the buffer (which
162 * will be Y-tiled). It is possible that it will not be the same as bo->size
163 * when the drm allocator rounds up the requested size.
170 * @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch
171 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch
176 * The distance in rows between array slices.
178 * @see RENDER_SURFACE_STATE.AuxiliarySurfaceQPitch
179 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch
184 struct intel_mipmap_tree
186 struct isl_surf surf
;
189 * Buffer object containing the surface.
191 * @see intel_mipmap_tree::offset
192 * @see RENDER_SURFACE_STATE.SurfaceBaseAddress
193 * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
194 * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
195 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
196 * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
201 * @brief One of GL_TEXTURE_2D, GL_TEXTURE_2D_ARRAY, etc.
203 * @see RENDER_SURFACE_STATE.SurfaceType
204 * @see RENDER_SURFACE_STATE.SurfaceArray
205 * @see 3DSTATE_DEPTH_BUFFER.SurfaceType
210 * Generally, this is just the same as the gl_texture_image->TexFormat or
211 * gl_renderbuffer->Format.
213 * However, for textures and renderbuffers with packed depth/stencil formats
214 * on hardware where we want or need to use separate stencil, there will be
215 * two miptrees for storing the data. If the depthstencil texture or rb is
216 * MESA_FORMAT_Z32_FLOAT_S8X24_UINT, then mt->format will be
217 * MESA_FORMAT_Z_FLOAT32, otherwise for MESA_FORMAT_Z24_UNORM_S8_UINT objects it will be
218 * MESA_FORMAT_Z24_UNORM_X8_UINT.
220 * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
221 * formats if the hardware lacks support for ETC1/ETC2. See @ref etc_format.
223 * @see RENDER_SURFACE_STATE.SurfaceFormat
224 * @see 3DSTATE_DEPTH_BUFFER.SurfaceFormat
229 * This variable stores the value of ETC compressed texture format
231 * @see RENDER_SURFACE_STATE.SurfaceFormat
233 mesa_format etc_format
;
238 /** Bytes per pixel (or bytes per block if compressed) */
243 /* Includes image offset tables: */
244 struct intel_mipmap_level level
[MAX_TEXTURE_LEVELS
];
247 * Offset into bo where the surface starts.
249 * @see intel_mipmap_tree::bo
251 * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
252 * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
253 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
254 * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
259 * \brief HiZ aux buffer
261 * To allocate the hiz buffer, use intel_miptree_alloc_hiz().
263 * To determine if hiz is enabled, do not check this pointer. Instead, use
264 * intel_miptree_level_has_hiz().
266 struct intel_miptree_aux_buffer
*hiz_buf
;
269 * \brief The type of auxiliary compression used by this miptree.
271 * This describes the type of auxiliary compression that is intended to be
272 * used by this miptree. An aux usage of ISL_AUX_USAGE_NONE means that
273 * auxiliary compression is permanently disabled. An aux usage other than
274 * ISL_AUX_USAGE_NONE does not imply that the auxiliary buffer has actually
275 * been allocated nor does it imply that auxiliary compression will always
276 * be enabled for this surface. For instance, with CCS_D, we may allocate
277 * the CCS on-the-fly and it may not be used for texturing if the miptree
280 enum isl_aux_usage aux_usage
;
283 * \brief Whether or not this miptree supports fast clears.
285 bool supports_fast_clear
;
288 * \brief Maps miptree slices to their current aux state
290 * This two-dimensional array is indexed as [level][layer] and stores an
291 * aux state for each slice.
293 enum isl_aux_state
**aux_state
;
296 * \brief Stencil miptree for depthstencil textures.
298 * This miptree is used for depthstencil textures and renderbuffers that
299 * require separate stencil. It always has the true copy of the stencil
300 * bits, regardless of mt->format.
302 * \see 3DSTATE_STENCIL_BUFFER
303 * \see intel_miptree_map_depthstencil()
304 * \see intel_miptree_unmap_depthstencil()
306 struct intel_mipmap_tree
*stencil_mt
;
309 * \brief Stencil texturing miptree for sampling from a stencil texture
311 * Some hardware doesn't support sampling from the stencil texture as
312 * required by the GL_ARB_stencil_texturing extenion. To workaround this we
313 * blit the texture into a new texture that can be sampled.
315 * \see intel_update_r8stencil()
317 struct intel_mipmap_tree
*r8stencil_mt
;
318 bool r8stencil_needs_update
;
321 * \brief MCS auxiliary buffer.
323 * This buffer contains the "multisample control surface", which stores
324 * the necessary information to implement compressed MSAA
325 * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+.
327 * NULL if no MCS buffer is in use for this surface.
329 struct intel_miptree_aux_buffer
*mcs_buf
;
332 * Planes 1 and 2 in case this is a planar surface.
334 struct intel_mipmap_tree
*plane
[2];
337 * Fast clear color for this surface. For depth surfaces, the clear value
338 * is stored as a float32 in the red component.
340 union isl_color_value fast_clear_color
;
342 /* These are also refcounted:
348 intel_miptree_alloc_ccs(struct brw_context
*brw
,
349 struct intel_mipmap_tree
*mt
);
352 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
= 1 << 0,
353 MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
= 1 << 1,
354 MIPTREE_LAYOUT_FOR_BO
= 1 << 2,
355 MIPTREE_LAYOUT_DISABLE_AUX
= 1 << 3,
356 MIPTREE_LAYOUT_FORCE_HALIGN16
= 1 << 4,
358 MIPTREE_LAYOUT_TILING_Y
= 1 << 5,
359 MIPTREE_LAYOUT_TILING_NONE
= 1 << 6,
360 MIPTREE_LAYOUT_TILING_ANY
= MIPTREE_LAYOUT_TILING_Y
|
361 MIPTREE_LAYOUT_TILING_NONE
,
363 MIPTREE_LAYOUT_FOR_SCANOUT
= 1 << 7,
366 struct intel_mipmap_tree
*intel_miptree_create(struct brw_context
*brw
,
377 struct intel_mipmap_tree
*
378 intel_miptree_create_for_bo(struct brw_context
*brw
,
386 uint32_t layout_flags
);
388 struct intel_mipmap_tree
*
389 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
392 enum isl_colorspace colorspace
,
393 bool is_winsys_image
);
396 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
397 struct intel_renderbuffer
*irb
,
398 struct intel_mipmap_tree
*singlesample_mt
,
399 uint32_t width
, uint32_t height
,
403 * Create a miptree appropriate as the storage for a non-texture renderbuffer.
404 * The miptree has the following properties:
405 * - The target is GL_TEXTURE_2D.
406 * - There are no levels other than the base level 0.
409 struct intel_mipmap_tree
*
410 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
414 uint32_t num_samples
);
417 intel_depth_format_for_depthstencil_format(mesa_format format
);
420 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
);
422 /** \brief Assert that the level and layer are valid for the miptree. */
424 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
428 void intel_miptree_reference(struct intel_mipmap_tree
**dst
,
429 struct intel_mipmap_tree
*src
);
431 void intel_miptree_release(struct intel_mipmap_tree
**mt
);
433 /* Check if an image fits an existing mipmap tree layout
435 bool intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
436 struct gl_texture_image
*image
);
439 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
440 GLuint level
, GLuint slice
,
441 GLuint
*x
, GLuint
*y
);
444 get_isl_surf_dim(GLenum target
);
447 get_isl_dim_layout(const struct gen_device_info
*devinfo
,
448 enum isl_tiling tiling
, GLenum target
);
451 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
452 const struct intel_mipmap_tree
*mt
);
455 intel_get_image_dims(struct gl_texture_image
*image
,
456 int *width
, int *height
, int *depth
);
459 intel_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
460 uint32_t *mask_x
, uint32_t *mask_y
);
463 intel_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
464 uint32_t *tile_w
, uint32_t *tile_h
);
467 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
468 GLuint level
, GLuint slice
,
472 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
473 uint32_t x
, uint32_t y
);
476 intel_miptree_copy_slice(struct brw_context
*brw
,
477 struct intel_mipmap_tree
*src_mt
,
478 unsigned src_level
, unsigned src_layer
,
479 struct intel_mipmap_tree
*dst_mt
,
480 unsigned dst_level
, unsigned dst_layer
);
483 intel_miptree_copy_teximage(struct brw_context
*brw
,
484 struct intel_texture_image
*intelImage
,
485 struct intel_mipmap_tree
*dst_mt
, bool invalidate
);
488 * \name Miptree HiZ functions
491 * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
492 * functions on a miptree without HiZ. In that case, each function is a no-op.
496 * \brief Allocate the miptree's embedded HiZ miptree.
497 * \see intel_mipmap_tree:hiz_mt
498 * \return false if allocation failed
501 intel_miptree_alloc_hiz(struct brw_context
*brw
,
502 struct intel_mipmap_tree
*mt
);
505 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
);
510 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
511 unsigned start_level
, unsigned num_levels
,
512 unsigned start_layer
, unsigned num_layers
);
515 #define INTEL_REMAINING_LAYERS UINT32_MAX
516 #define INTEL_REMAINING_LEVELS UINT32_MAX
518 /** Prepare a miptree for access
520 * This function should be called prior to any access to miptree in order to
521 * perform any needed resolves.
523 * \param[in] start_level The first mip level to be accessed
525 * \param[in] num_levels The number of miplevels to be accessed or
526 * INTEL_REMAINING_LEVELS to indicate every level
527 * above start_level will be accessed
529 * \param[in] start_layer The first array slice or 3D layer to be accessed
531 * \param[in] num_layers The number of array slices or 3D layers be
532 * accessed or INTEL_REMAINING_LAYERS to indicate
533 * every layer above start_layer will be accessed
535 * \param[in] aux_supported Whether or not the access will support the
536 * miptree's auxiliary compression format; this
537 * must be false for uncompressed miptrees
539 * \param[in] fast_clear_supported Whether or not the access will support
540 * fast clears in the miptree's auxiliary
544 intel_miptree_prepare_access(struct brw_context
*brw
,
545 struct intel_mipmap_tree
*mt
,
546 uint32_t start_level
, uint32_t num_levels
,
547 uint32_t start_layer
, uint32_t num_layers
,
548 enum isl_aux_usage aux_usage
,
549 bool fast_clear_supported
);
551 /** Complete a write operation
553 * This function should be called after any operation writes to a miptree.
554 * This will update the miptree's compression state so that future resolves
555 * happen correctly. Technically, this function can be called before the
556 * write occurs but the caller must ensure that they don't interlace
557 * intel_miptree_prepare_access and intel_miptree_finish_write calls to
558 * overlapping layer/level ranges.
560 * \param[in] level The mip level that was written
562 * \param[in] start_layer The first array slice or 3D layer written
564 * \param[in] num_layers The number of array slices or 3D layers
565 * written or INTEL_REMAINING_LAYERS to indicate
566 * every layer above start_layer was written
568 * \param[in] written_with_aux Whether or not the write was done with
569 * auxiliary compression enabled
572 intel_miptree_finish_write(struct brw_context
*brw
,
573 struct intel_mipmap_tree
*mt
, uint32_t level
,
574 uint32_t start_layer
, uint32_t num_layers
,
575 enum isl_aux_usage aux_usage
);
577 /** Get the auxiliary compression state of a miptree slice */
579 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
580 uint32_t level
, uint32_t layer
);
582 /** Set the auxiliary compression state of a miptree slice range
584 * This function directly sets the auxiliary compression state of a slice
585 * range of a miptree. It only modifies data structures and does not do any
586 * resolves. This should only be called by code which directly performs
587 * compression operations such as fast clears and resolves. Most code should
588 * use intel_miptree_prepare_access or intel_miptree_finish_write.
591 intel_miptree_set_aux_state(struct brw_context
*brw
,
592 struct intel_mipmap_tree
*mt
, uint32_t level
,
593 uint32_t start_layer
, uint32_t num_layers
,
594 enum isl_aux_state aux_state
);
597 * Prepare a miptree for raw access
599 * This helper prepares the miptree for access that knows nothing about any
600 * sort of compression whatsoever. This is useful when mapping the surface or
601 * using it with the blitter.
604 intel_miptree_access_raw(struct brw_context
*brw
,
605 struct intel_mipmap_tree
*mt
,
606 uint32_t level
, uint32_t layer
,
609 intel_miptree_prepare_access(brw
, mt
, level
, 1, layer
, 1, false, false);
611 intel_miptree_finish_write(brw
, mt
, level
, layer
, 1, false);
615 intel_miptree_texture_aux_usage(struct brw_context
*brw
,
616 struct intel_mipmap_tree
*mt
,
617 enum isl_format view_format
);
619 intel_miptree_prepare_texture(struct brw_context
*brw
,
620 struct intel_mipmap_tree
*mt
,
621 enum isl_format view_format
,
622 bool *aux_supported_out
);
624 intel_miptree_prepare_image(struct brw_context
*brw
,
625 struct intel_mipmap_tree
*mt
);
627 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
628 struct intel_mipmap_tree
*mt
, uint32_t level
,
629 uint32_t start_layer
, uint32_t num_layers
);
631 intel_miptree_render_aux_usage(struct brw_context
*brw
,
632 struct intel_mipmap_tree
*mt
,
635 intel_miptree_prepare_render(struct brw_context
*brw
,
636 struct intel_mipmap_tree
*mt
, uint32_t level
,
637 uint32_t start_layer
, uint32_t layer_count
,
640 intel_miptree_finish_render(struct brw_context
*brw
,
641 struct intel_mipmap_tree
*mt
, uint32_t level
,
642 uint32_t start_layer
, uint32_t layer_count
,
645 intel_miptree_prepare_depth(struct brw_context
*brw
,
646 struct intel_mipmap_tree
*mt
, uint32_t level
,
647 uint32_t start_layer
, uint32_t layer_count
);
649 intel_miptree_finish_depth(struct brw_context
*brw
,
650 struct intel_mipmap_tree
*mt
, uint32_t level
,
651 uint32_t start_layer
, uint32_t layer_count
,
655 intel_miptree_make_shareable(struct brw_context
*brw
,
656 struct intel_mipmap_tree
*mt
);
659 intel_miptree_updownsample(struct brw_context
*brw
,
660 struct intel_mipmap_tree
*src
,
661 struct intel_mipmap_tree
*dst
);
664 intel_update_r8stencil(struct brw_context
*brw
,
665 struct intel_mipmap_tree
*mt
);
668 brw_miptree_layout(struct brw_context
*brw
,
669 struct intel_mipmap_tree
*mt
,
670 uint32_t layout_flags
);
673 intel_miptree_map(struct brw_context
*brw
,
674 struct intel_mipmap_tree
*mt
,
683 ptrdiff_t *out_stride
);
686 intel_miptree_unmap(struct brw_context
*brw
,
687 struct intel_mipmap_tree
*mt
,
692 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
693 struct intel_mipmap_tree
*mt
);