2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "main/context.h"
30 #include "main/framebuffer.h"
31 #include "main/renderbuffer.h"
32 #include "main/texobj.h"
33 #include "main/hash.h"
34 #include "main/fbobject.h"
35 #include "main/version.h"
36 #include "swrast/s_renderbuffer.h"
37 #include "util/ralloc.h"
38 #include "brw_defines.h"
39 #include "compiler/nir/nir.h"
44 #ifndef DRM_FORMAT_MOD_INVALID
45 #define DRM_FORMAT_MOD_INVALID ((1ULL<<56) - 1)
48 static const __DRIconfigOptionsExtension brw_config_options
= {
49 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
52 DRI_CONF_SECTION_PERFORMANCE
53 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_ALWAYS_SYNC
)
54 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
55 * DRI_CONF_BO_REUSE_ALL
57 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
58 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
59 DRI_CONF_ENUM(0, "Disable buffer object reuse")
60 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
65 DRI_CONF_SECTION_QUALITY
66 DRI_CONF_FORCE_S3TC_ENABLE("false")
68 DRI_CONF_PRECISE_TRIG("false")
70 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
71 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
72 "given integer. If negative, then do not clamp.")
76 DRI_CONF_SECTION_DEBUG
77 DRI_CONF_NO_RAST("false")
78 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
79 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
80 DRI_CONF_DISABLE_THROTTLING("false")
81 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
82 DRI_CONF_FORCE_GLSL_VERSION(0)
83 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
84 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
85 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
86 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
87 DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
89 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
90 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
94 DRI_CONF_SECTION_MISCELLANEOUS
95 DRI_CONF_GLSL_ZERO_INIT("false")
100 #include "intel_batchbuffer.h"
101 #include "intel_buffers.h"
102 #include "intel_bufmgr.h"
103 #include "intel_fbo.h"
104 #include "intel_mipmap_tree.h"
105 #include "intel_screen.h"
106 #include "intel_tex.h"
107 #include "intel_image.h"
109 #include "brw_context.h"
111 #include "i915_drm.h"
114 * For debugging purposes, this returns a time in seconds.
121 clock_gettime(CLOCK_MONOTONIC
, &tp
);
123 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
126 static const __DRItexBufferExtension intelTexBufferExtension
= {
127 .base
= { __DRI_TEX_BUFFER
, 3 },
129 .setTexBuffer
= intelSetTexBuffer
,
130 .setTexBuffer2
= intelSetTexBuffer2
,
131 .releaseTexBuffer
= NULL
,
135 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
136 __DRIdrawable
*dPriv
,
138 enum __DRI2throttleReason reason
)
140 struct brw_context
*brw
= cPriv
->driverPrivate
;
145 struct gl_context
*ctx
= &brw
->ctx
;
147 FLUSH_VERTICES(ctx
, 0);
149 if (flags
& __DRI2_FLUSH_DRAWABLE
)
150 intel_resolve_for_dri2_flush(brw
, dPriv
);
152 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
)
153 brw
->need_swap_throttle
= true;
154 if (reason
== __DRI2_THROTTLE_FLUSHFRONT
)
155 brw
->need_flush_throttle
= true;
157 intel_batchbuffer_flush(brw
);
161 * Provides compatibility with loaders that only support the older (version
162 * 1-3) flush interface.
164 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
167 intel_dri2_flush(__DRIdrawable
*drawable
)
169 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
170 __DRI2_FLUSH_DRAWABLE
,
171 __DRI2_THROTTLE_SWAPBUFFER
);
174 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
175 .base
= { __DRI2_FLUSH
, 4 },
177 .flush
= intel_dri2_flush
,
178 .invalidate
= dri2InvalidateDrawable
,
179 .flush_with_flags
= intel_dri2_flush_with_flags
,
182 static struct intel_image_format intel_image_formats
[] = {
183 { __DRI_IMAGE_FOURCC_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
184 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
186 { __DRI_IMAGE_FOURCC_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
187 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
189 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
190 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
192 { __DRI_IMAGE_FOURCC_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
193 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
195 { __DRI_IMAGE_FOURCC_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
196 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
198 { __DRI_IMAGE_FOURCC_ARGB1555
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
199 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555
, 2 } } },
201 { __DRI_IMAGE_FOURCC_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
202 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
204 { __DRI_IMAGE_FOURCC_R8
, __DRI_IMAGE_COMPONENTS_R
, 1,
205 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 }, } },
207 { __DRI_IMAGE_FOURCC_R16
, __DRI_IMAGE_COMPONENTS_R
, 1,
208 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 1 }, } },
210 { __DRI_IMAGE_FOURCC_GR88
, __DRI_IMAGE_COMPONENTS_RG
, 1,
211 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 }, } },
213 { __DRI_IMAGE_FOURCC_GR1616
, __DRI_IMAGE_COMPONENTS_RG
, 1,
214 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616
, 2 }, } },
216 { __DRI_IMAGE_FOURCC_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
217 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
218 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
219 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
221 { __DRI_IMAGE_FOURCC_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
222 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
223 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
224 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
226 { __DRI_IMAGE_FOURCC_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
227 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
228 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
229 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
231 { __DRI_IMAGE_FOURCC_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
232 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
233 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
234 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
236 { __DRI_IMAGE_FOURCC_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
237 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
238 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
239 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
241 { __DRI_IMAGE_FOURCC_YVU410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
242 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
243 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
244 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
246 { __DRI_IMAGE_FOURCC_YVU411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
247 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
248 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
249 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
251 { __DRI_IMAGE_FOURCC_YVU420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
252 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
253 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
254 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
256 { __DRI_IMAGE_FOURCC_YVU422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
257 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
258 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
259 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
261 { __DRI_IMAGE_FOURCC_YVU444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
262 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
263 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
264 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
266 { __DRI_IMAGE_FOURCC_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
267 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
268 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
270 { __DRI_IMAGE_FOURCC_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
271 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
272 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
274 /* For YUYV buffers, we set up two overlapping DRI images and treat
275 * them as planar buffers in the compositors. Plane 0 is GR88 and
276 * samples YU or YV pairs and places Y into the R component, while
277 * plane 1 is ARGB and samples YUYV clusters and places pairs and
278 * places U into the G component and V into A. This lets the
279 * texture sampler interpolate the Y components correctly when
280 * sampling from plane 0, and interpolate U and V correctly when
281 * sampling from plane 1. */
282 { __DRI_IMAGE_FOURCC_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
283 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
284 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } }
288 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
290 uint32_t tiling
, swizzle
;
291 drm_intel_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
293 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
294 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
295 func
, image
->offset
);
299 static struct intel_image_format
*
300 intel_image_format_lookup(int fourcc
)
302 struct intel_image_format
*f
= NULL
;
304 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
305 if (intel_image_formats
[i
].fourcc
== fourcc
) {
306 f
= &intel_image_formats
[i
];
314 static boolean
intel_lookup_fourcc(int dri_format
, int *fourcc
)
316 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
317 if (intel_image_formats
[i
].planes
[0].dri_format
== dri_format
) {
318 *fourcc
= intel_image_formats
[i
].fourcc
;
326 intel_allocate_image(struct intel_screen
*screen
, int dri_format
,
331 image
= calloc(1, sizeof *image
);
335 image
->screen
= screen
;
336 image
->dri_format
= dri_format
;
339 image
->format
= driImageFormatToGLFormat(dri_format
);
340 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
341 image
->format
== MESA_FORMAT_NONE
) {
346 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
347 image
->data
= loaderPrivate
;
353 * Sets up a DRIImage structure to point to a slice out of a miptree.
356 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
357 struct intel_mipmap_tree
*mt
, GLuint level
,
360 intel_miptree_make_shareable(brw
, mt
);
362 intel_miptree_check_level_layer(mt
, level
, zoffset
);
364 image
->width
= minify(mt
->physical_width0
, level
- mt
->first_level
);
365 image
->height
= minify(mt
->physical_height0
, level
- mt
->first_level
);
366 image
->pitch
= mt
->pitch
;
368 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
372 drm_intel_bo_unreference(image
->bo
);
374 drm_intel_bo_reference(mt
->bo
);
378 intel_create_image_from_name(__DRIscreen
*dri_screen
,
379 int width
, int height
, int format
,
380 int name
, int pitch
, void *loaderPrivate
)
382 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
386 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
390 if (image
->format
== MESA_FORMAT_NONE
)
393 cpp
= _mesa_get_format_bytes(image
->format
);
395 image
->width
= width
;
396 image
->height
= height
;
397 image
->pitch
= pitch
* cpp
;
398 image
->bo
= drm_intel_bo_gem_create_from_name(screen
->bufmgr
, "image",
409 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
410 int renderbuffer
, void *loaderPrivate
)
413 struct brw_context
*brw
= context
->driverPrivate
;
414 struct gl_context
*ctx
= &brw
->ctx
;
415 struct gl_renderbuffer
*rb
;
416 struct intel_renderbuffer
*irb
;
418 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
420 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
424 irb
= intel_renderbuffer(rb
);
425 intel_miptree_make_shareable(brw
, irb
->mt
);
426 image
= calloc(1, sizeof *image
);
430 image
->internal_format
= rb
->InternalFormat
;
431 image
->format
= rb
->Format
;
433 image
->data
= loaderPrivate
;
434 drm_intel_bo_unreference(image
->bo
);
435 image
->bo
= irb
->mt
->bo
;
436 drm_intel_bo_reference(irb
->mt
->bo
);
437 image
->width
= rb
->Width
;
438 image
->height
= rb
->Height
;
439 image
->pitch
= irb
->mt
->pitch
;
440 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
441 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
443 rb
->NeedsFinishRenderTexture
= true;
448 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
449 unsigned texture
, int zoffset
,
455 struct brw_context
*brw
= context
->driverPrivate
;
456 struct gl_texture_object
*obj
;
457 struct intel_texture_object
*iobj
;
460 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
461 if (!obj
|| obj
->Target
!= target
) {
462 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
466 if (target
== GL_TEXTURE_CUBE_MAP
)
469 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
470 iobj
= intel_texture_object(obj
);
471 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
472 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
476 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
477 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
481 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
482 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
485 image
= calloc(1, sizeof *image
);
487 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
491 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
492 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
493 image
->data
= loaderPrivate
;
494 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
495 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
496 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
497 if (image
->dri_format
== MESA_FORMAT_NONE
) {
498 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
503 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
508 intel_destroy_image(__DRIimage
*image
)
510 drm_intel_bo_unreference(image
->bo
);
515 select_best_modifier(struct gen_device_info
*devinfo
,
516 const uint64_t *modifiers
,
517 const unsigned count
)
519 /* Modifiers are not supported by this DRI driver */
520 return DRM_FORMAT_MOD_INVALID
;
524 intel_create_image_common(__DRIscreen
*dri_screen
,
525 int width
, int height
, int format
,
527 const uint64_t *modifiers
,
532 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
537 /* Callers of this may specify a modifier, or a dri usage, but not both. The
538 * newer modifier interface deprecates the older usage flags newer modifier
539 * interface deprecates the older usage flags.
541 assert(!(use
&& count
));
543 uint64_t modifier
= select_best_modifier(&screen
->devinfo
, modifiers
, count
);
544 assert(modifier
== DRM_FORMAT_MOD_INVALID
);
546 if (modifier
== DRM_FORMAT_MOD_INVALID
&& modifiers
)
549 /* Historically, X-tiled was the default, and so lack of modifier means
552 tiling
= I915_TILING_X
;
553 if (use
& __DRI_IMAGE_USE_CURSOR
) {
554 if (width
!= 64 || height
!= 64)
556 tiling
= I915_TILING_NONE
;
559 if (use
& __DRI_IMAGE_USE_LINEAR
)
560 tiling
= I915_TILING_NONE
;
562 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
566 cpp
= _mesa_get_format_bytes(image
->format
);
567 image
->bo
= drm_intel_bo_alloc_tiled(screen
->bufmgr
, "image",
568 width
, height
, cpp
, &tiling
,
570 if (image
->bo
== NULL
) {
574 image
->width
= width
;
575 image
->height
= height
;
576 image
->pitch
= pitch
;
582 intel_create_image(__DRIscreen
*dri_screen
,
583 int width
, int height
, int format
,
587 return intel_create_image_common(dri_screen
, width
, height
, format
, use
, NULL
, 0,
592 intel_create_image_with_modifiers(__DRIscreen
*dri_screen
,
593 int width
, int height
, int format
,
594 const uint64_t *modifiers
,
595 const unsigned count
,
598 return intel_create_image_common(dri_screen
, width
, height
, format
, 0, NULL
,
603 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
606 case __DRI_IMAGE_ATTRIB_STRIDE
:
607 *value
= image
->pitch
;
609 case __DRI_IMAGE_ATTRIB_HANDLE
:
610 *value
= image
->bo
->handle
;
612 case __DRI_IMAGE_ATTRIB_NAME
:
613 return !drm_intel_bo_flink(image
->bo
, (uint32_t *) value
);
614 case __DRI_IMAGE_ATTRIB_FORMAT
:
615 *value
= image
->dri_format
;
617 case __DRI_IMAGE_ATTRIB_WIDTH
:
618 *value
= image
->width
;
620 case __DRI_IMAGE_ATTRIB_HEIGHT
:
621 *value
= image
->height
;
623 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
624 if (image
->planar_format
== NULL
)
626 *value
= image
->planar_format
->components
;
628 case __DRI_IMAGE_ATTRIB_FD
:
629 return !drm_intel_bo_gem_export_to_prime(image
->bo
, value
);
630 case __DRI_IMAGE_ATTRIB_FOURCC
:
631 return intel_lookup_fourcc(image
->dri_format
, value
);
632 case __DRI_IMAGE_ATTRIB_NUM_PLANES
:
635 case __DRI_IMAGE_ATTRIB_OFFSET
:
636 *value
= image
->offset
;
645 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
649 image
= calloc(1, sizeof *image
);
653 drm_intel_bo_reference(orig_image
->bo
);
654 image
->bo
= orig_image
->bo
;
655 image
->internal_format
= orig_image
->internal_format
;
656 image
->planar_format
= orig_image
->planar_format
;
657 image
->dri_format
= orig_image
->dri_format
;
658 image
->format
= orig_image
->format
;
659 image
->offset
= orig_image
->offset
;
660 image
->width
= orig_image
->width
;
661 image
->height
= orig_image
->height
;
662 image
->pitch
= orig_image
->pitch
;
663 image
->tile_x
= orig_image
->tile_x
;
664 image
->tile_y
= orig_image
->tile_y
;
665 image
->has_depthstencil
= orig_image
->has_depthstencil
;
666 image
->data
= loaderPrivate
;
668 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
669 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
675 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
677 if (use
& __DRI_IMAGE_USE_CURSOR
) {
678 if (image
->width
!= 64 || image
->height
!= 64)
686 intel_create_image_from_names(__DRIscreen
*dri_screen
,
687 int width
, int height
, int fourcc
,
688 int *names
, int num_names
,
689 int *strides
, int *offsets
,
692 struct intel_image_format
*f
= NULL
;
696 if (dri_screen
== NULL
|| names
== NULL
|| num_names
!= 1)
699 f
= intel_image_format_lookup(fourcc
);
703 image
= intel_create_image_from_name(dri_screen
, width
, height
,
704 __DRI_IMAGE_FORMAT_NONE
,
705 names
[0], strides
[0],
711 image
->planar_format
= f
;
712 for (i
= 0; i
< f
->nplanes
; i
++) {
713 index
= f
->planes
[i
].buffer_index
;
714 image
->offsets
[index
] = offsets
[index
];
715 image
->strides
[index
] = strides
[index
];
722 intel_create_image_from_fds(__DRIscreen
*dri_screen
,
723 int width
, int height
, int fourcc
,
724 int *fds
, int num_fds
, int *strides
, int *offsets
,
727 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
728 struct intel_image_format
*f
;
732 if (fds
== NULL
|| num_fds
< 1)
735 /* We only support all planes from the same bo */
736 for (i
= 0; i
< num_fds
; i
++)
737 if (fds
[0] != fds
[i
])
740 f
= intel_image_format_lookup(fourcc
);
745 image
= intel_allocate_image(screen
, f
->planes
[0].dri_format
,
748 image
= intel_allocate_image(screen
, __DRI_IMAGE_FORMAT_NONE
,
754 image
->width
= width
;
755 image
->height
= height
;
756 image
->pitch
= strides
[0];
758 image
->planar_format
= f
;
760 for (i
= 0; i
< f
->nplanes
; i
++) {
761 index
= f
->planes
[i
].buffer_index
;
762 image
->offsets
[index
] = offsets
[index
];
763 image
->strides
[index
] = strides
[index
];
765 const int plane_height
= height
>> f
->planes
[i
].height_shift
;
766 const int end
= offsets
[index
] + plane_height
* strides
[index
];
771 image
->bo
= drm_intel_bo_gem_create_from_prime(screen
->bufmgr
,
773 if (image
->bo
== NULL
) {
778 if (f
->nplanes
== 1) {
779 image
->offset
= image
->offsets
[0];
780 intel_image_warn_if_unaligned(image
, __func__
);
787 intel_create_image_from_dma_bufs(__DRIscreen
*dri_screen
,
788 int width
, int height
, int fourcc
,
789 int *fds
, int num_fds
,
790 int *strides
, int *offsets
,
791 enum __DRIYUVColorSpace yuv_color_space
,
792 enum __DRISampleRange sample_range
,
793 enum __DRIChromaSiting horizontal_siting
,
794 enum __DRIChromaSiting vertical_siting
,
799 struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
802 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
806 image
= intel_create_image_from_fds(dri_screen
, width
, height
, fourcc
, fds
,
807 num_fds
, strides
, offsets
,
811 * Invalid parameters and any inconsistencies between are assumed to be
812 * checked by the caller. Therefore besides unsupported formats one can fail
813 * only in allocation.
816 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
820 image
->dma_buf_imported
= true;
821 image
->yuv_color_space
= yuv_color_space
;
822 image
->sample_range
= sample_range
;
823 image
->horizontal_siting
= horizontal_siting
;
824 image
->vertical_siting
= vertical_siting
;
826 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
831 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
833 int width
, height
, offset
, stride
, dri_format
, index
;
834 struct intel_image_format
*f
;
837 if (parent
== NULL
|| parent
->planar_format
== NULL
)
840 f
= parent
->planar_format
;
842 if (plane
>= f
->nplanes
)
845 width
= parent
->width
>> f
->planes
[plane
].width_shift
;
846 height
= parent
->height
>> f
->planes
[plane
].height_shift
;
847 dri_format
= f
->planes
[plane
].dri_format
;
848 index
= f
->planes
[plane
].buffer_index
;
849 offset
= parent
->offsets
[index
];
850 stride
= parent
->strides
[index
];
852 image
= intel_allocate_image(parent
->screen
, dri_format
, loaderPrivate
);
856 if (offset
+ height
* stride
> parent
->bo
->size
) {
857 _mesa_warning(NULL
, "intel_create_sub_image: subimage out of bounds");
862 image
->bo
= parent
->bo
;
863 drm_intel_bo_reference(parent
->bo
);
865 image
->width
= width
;
866 image
->height
= height
;
867 image
->pitch
= stride
;
868 image
->offset
= offset
;
870 intel_image_warn_if_unaligned(image
, __func__
);
875 static const __DRIimageExtension intelImageExtension
= {
876 .base
= { __DRI_IMAGE
, 13 },
878 .createImageFromName
= intel_create_image_from_name
,
879 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
880 .destroyImage
= intel_destroy_image
,
881 .createImage
= intel_create_image
,
882 .queryImage
= intel_query_image
,
883 .dupImage
= intel_dup_image
,
884 .validateUsage
= intel_validate_usage
,
885 .createImageFromNames
= intel_create_image_from_names
,
886 .fromPlanar
= intel_from_planar
,
887 .createImageFromTexture
= intel_create_image_from_texture
,
888 .createImageFromFds
= intel_create_image_from_fds
,
889 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
,
891 .getCapabilities
= NULL
,
894 .createImageWithModifiers
= intel_create_image_with_modifiers
,
898 brw_query_renderer_integer(__DRIscreen
*dri_screen
,
899 int param
, unsigned int *value
)
901 const struct intel_screen
*const screen
=
902 (struct intel_screen
*) dri_screen
->driverPrivate
;
905 case __DRI2_RENDERER_VENDOR_ID
:
908 case __DRI2_RENDERER_DEVICE_ID
:
909 value
[0] = screen
->deviceID
;
911 case __DRI2_RENDERER_ACCELERATED
:
914 case __DRI2_RENDERER_VIDEO_MEMORY
: {
915 /* Once a batch uses more than 75% of the maximum mappable size, we
916 * assume that there's some fragmentation, and we start doing extra
917 * flushing, etc. That's the big cliff apps will care about.
920 size_t mappable_size
;
922 drm_intel_get_aperture_sizes(dri_screen
->fd
, &mappable_size
, &aper_size
);
924 const unsigned gpu_mappable_megabytes
=
925 (aper_size
/ (1024 * 1024)) * 3 / 4;
927 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
928 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
930 if (system_memory_pages
<= 0 || system_page_size
<= 0)
933 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
934 * (uint64_t) system_page_size
;
936 const unsigned system_memory_megabytes
=
937 (unsigned) (system_memory_bytes
/ (1024 * 1024));
939 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
942 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
945 case __DRI2_RENDERER_HAS_TEXTURE_3D
:
949 return driQueryRendererIntegerCommon(dri_screen
, param
, value
);
956 brw_query_renderer_string(__DRIscreen
*dri_screen
,
957 int param
, const char **value
)
959 const struct intel_screen
*screen
=
960 (struct intel_screen
*) dri_screen
->driverPrivate
;
963 case __DRI2_RENDERER_VENDOR_ID
:
964 value
[0] = brw_vendor_string
;
966 case __DRI2_RENDERER_DEVICE_ID
:
967 value
[0] = brw_get_renderer_string(screen
);
976 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
977 .base
= { __DRI2_RENDERER_QUERY
, 1 },
979 .queryInteger
= brw_query_renderer_integer
,
980 .queryString
= brw_query_renderer_string
983 static const __DRIrobustnessExtension dri2Robustness
= {
984 .base
= { __DRI2_ROBUSTNESS
, 1 }
987 static const __DRIextension
*screenExtensions
[] = {
988 &intelTexBufferExtension
.base
,
989 &intelFenceExtension
.base
,
990 &intelFlushExtension
.base
,
991 &intelImageExtension
.base
,
992 &intelRendererQueryExtension
.base
,
993 &dri2ConfigQueryExtension
.base
,
997 static const __DRIextension
*intelRobustScreenExtensions
[] = {
998 &intelTexBufferExtension
.base
,
999 &intelFenceExtension
.base
,
1000 &intelFlushExtension
.base
,
1001 &intelImageExtension
.base
,
1002 &intelRendererQueryExtension
.base
,
1003 &dri2ConfigQueryExtension
.base
,
1004 &dri2Robustness
.base
,
1009 intel_get_param(struct intel_screen
*screen
, int param
, int *value
)
1012 struct drm_i915_getparam gp
;
1014 memset(&gp
, 0, sizeof(gp
));
1018 if (drmIoctl(screen
->driScrnPriv
->fd
, DRM_IOCTL_I915_GETPARAM
, &gp
) == -1) {
1021 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
1028 intel_get_boolean(struct intel_screen
*screen
, int param
)
1031 return (intel_get_param(screen
, param
, &value
) == 0) && value
;
1035 intel_get_integer(struct intel_screen
*screen
, int param
)
1039 if (intel_get_param(screen
, param
, &value
) == 0)
1046 intelDestroyScreen(__DRIscreen
* sPriv
)
1048 struct intel_screen
*screen
= sPriv
->driverPrivate
;
1050 dri_bufmgr_destroy(screen
->bufmgr
);
1051 driDestroyOptionInfo(&screen
->optionCache
);
1053 ralloc_free(screen
);
1054 sPriv
->driverPrivate
= NULL
;
1059 * This is called when we need to set up GL rendering to a new X window.
1062 intelCreateBuffer(__DRIscreen
*dri_screen
,
1063 __DRIdrawable
* driDrawPriv
,
1064 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
1066 struct intel_renderbuffer
*rb
;
1067 struct intel_screen
*screen
= (struct intel_screen
*)
1068 dri_screen
->driverPrivate
;
1069 mesa_format rgbFormat
;
1070 unsigned num_samples
=
1071 intel_quantize_num_samples(screen
, mesaVis
->samples
);
1072 struct gl_framebuffer
*fb
;
1077 fb
= CALLOC_STRUCT(gl_framebuffer
);
1081 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
1083 if (screen
->winsys_msaa_samples_override
!= -1) {
1084 num_samples
= screen
->winsys_msaa_samples_override
;
1085 fb
->Visual
.samples
= num_samples
;
1088 if (mesaVis
->redBits
== 5) {
1089 rgbFormat
= mesaVis
->redMask
== 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1090 : MESA_FORMAT_B5G6R5_UNORM
;
1091 } else if (mesaVis
->sRGBCapable
) {
1092 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1093 : MESA_FORMAT_B8G8R8A8_SRGB
;
1094 } else if (mesaVis
->alphaBits
== 0) {
1095 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8X8_UNORM
1096 : MESA_FORMAT_B8G8R8X8_UNORM
;
1098 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1099 : MESA_FORMAT_B8G8R8A8_SRGB
;
1100 fb
->Visual
.sRGBCapable
= true;
1103 /* setup the hardware-based renderbuffers */
1104 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
1105 _mesa_add_renderbuffer(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
1107 if (mesaVis
->doubleBufferMode
) {
1108 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
1109 _mesa_add_renderbuffer(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1113 * Assert here that the gl_config has an expected depth/stencil bit
1114 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1115 * which constructs the advertised configs.)
1117 if (mesaVis
->depthBits
== 24) {
1118 assert(mesaVis
->stencilBits
== 8);
1120 if (screen
->devinfo
.has_hiz_and_separate_stencil
) {
1121 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_X8_UINT
,
1123 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1124 rb
= intel_create_private_renderbuffer(MESA_FORMAT_S_UINT8
,
1126 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1129 * Use combined depth/stencil. Note that the renderbuffer is
1130 * attached to two attachment points.
1132 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_S8_UINT
,
1134 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1135 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1138 else if (mesaVis
->depthBits
== 16) {
1139 assert(mesaVis
->stencilBits
== 0);
1140 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z_UNORM16
,
1142 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1145 assert(mesaVis
->depthBits
== 0);
1146 assert(mesaVis
->stencilBits
== 0);
1149 /* now add any/all software-based renderbuffers we may need */
1150 _swrast_add_soft_renderbuffers(fb
,
1151 false, /* never sw color */
1152 false, /* never sw depth */
1153 false, /* never sw stencil */
1154 mesaVis
->accumRedBits
> 0,
1155 false, /* never sw alpha */
1156 false /* never sw aux */ );
1157 driDrawPriv
->driverPrivate
= fb
;
1163 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1165 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1167 _mesa_reference_framebuffer(&fb
, NULL
);
1171 intel_detect_sseu(struct intel_screen
*screen
)
1173 assert(screen
->devinfo
.gen
>= 8);
1176 screen
->subslice_total
= -1;
1177 screen
->eu_total
= -1;
1179 ret
= intel_get_param(screen
, I915_PARAM_SUBSLICE_TOTAL
,
1180 &screen
->subslice_total
);
1181 if (ret
< 0 && ret
!= -EINVAL
)
1184 ret
= intel_get_param(screen
,
1185 I915_PARAM_EU_TOTAL
, &screen
->eu_total
);
1186 if (ret
< 0 && ret
!= -EINVAL
)
1189 /* Without this information, we cannot get the right Braswell brandstrings,
1190 * and we have to use conservative numbers for GPGPU on many platforms, but
1191 * otherwise, things will just work.
1193 if (screen
->subslice_total
< 1 || screen
->eu_total
< 1)
1195 "Kernel 4.1 required to properly query GPU properties.\n");
1200 screen
->subslice_total
= -1;
1201 screen
->eu_total
= -1;
1202 _mesa_warning(NULL
, "Failed to query GPU properties (%s).\n", strerror(-ret
));
1206 intel_init_bufmgr(struct intel_screen
*screen
)
1208 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1210 screen
->no_hw
= getenv("INTEL_NO_HW") != NULL
;
1212 screen
->bufmgr
= intel_bufmgr_gem_init(dri_screen
->fd
, BATCH_SZ
);
1213 if (screen
->bufmgr
== NULL
) {
1214 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1215 __func__
, __LINE__
);
1219 drm_intel_bufmgr_gem_enable_fenced_relocs(screen
->bufmgr
);
1221 if (!intel_get_boolean(screen
, I915_PARAM_HAS_RELAXED_DELTA
)) {
1222 fprintf(stderr
, "[%s: %u] Kernel 2.6.39 required.\n", __func__
, __LINE__
);
1230 intel_detect_swizzling(struct intel_screen
*screen
)
1232 drm_intel_bo
*buffer
;
1233 unsigned long flags
= 0;
1234 unsigned long aligned_pitch
;
1235 uint32_t tiling
= I915_TILING_X
;
1236 uint32_t swizzle_mode
= 0;
1238 buffer
= drm_intel_bo_alloc_tiled(screen
->bufmgr
, "swizzle test",
1240 &tiling
, &aligned_pitch
, flags
);
1244 drm_intel_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1245 drm_intel_bo_unreference(buffer
);
1247 if (swizzle_mode
== I915_BIT_6_SWIZZLE_NONE
)
1254 intel_detect_timestamp(struct intel_screen
*screen
)
1256 uint64_t dummy
= 0, last
= 0;
1257 int upper
, lower
, loops
;
1259 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1260 * TIMESTAMP register being shifted and the low 32bits always zero.
1262 * More recent kernels offer an interface to read the full 36bits
1265 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &dummy
) == 0)
1268 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1269 * upper 32bits for a rapidly changing timestamp.
1271 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
, &last
))
1275 for (loops
= 0; loops
< 10; loops
++) {
1276 /* The TIMESTAMP should change every 80ns, so several round trips
1277 * through the kernel should be enough to advance it.
1279 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
, &dummy
))
1282 upper
+= (dummy
>> 32) != (last
>> 32);
1283 if (upper
> 1) /* beware 32bit counter overflow */
1284 return 2; /* upper dword holds the low 32bits of the timestamp */
1286 lower
+= (dummy
& 0xffffffff) != (last
& 0xffffffff);
1288 return 1; /* timestamp is unshifted */
1293 /* No advancement? No timestamp! */
1298 * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
1300 * Some combinations of hardware and kernel versions allow this feature,
1301 * while others don't. Instead of trying to enumerate every case, just
1302 * try and write a register and see if works.
1305 intel_detect_pipelined_register(struct intel_screen
*screen
,
1306 int reg
, uint32_t expected_value
, bool reset
)
1308 drm_intel_bo
*results
, *bo
;
1310 uint32_t offset
= 0;
1311 bool success
= false;
1313 /* Create a zero'ed temporary buffer for reading our results */
1314 results
= drm_intel_bo_alloc(screen
->bufmgr
, "registers", 4096, 0);
1315 if (results
== NULL
)
1318 bo
= drm_intel_bo_alloc(screen
->bufmgr
, "batchbuffer", 4096, 0);
1322 if (drm_intel_bo_map(bo
, 1))
1325 batch
= bo
->virtual;
1327 /* Write the register. */
1328 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1330 *batch
++ = expected_value
;
1332 /* Save the register's value back to the buffer. */
1333 *batch
++ = MI_STORE_REGISTER_MEM
| (3 - 2);
1335 drm_intel_bo_emit_reloc(bo
, (char *)batch
-(char *)bo
->virtual,
1336 results
, offset
*sizeof(uint32_t),
1337 I915_GEM_DOMAIN_INSTRUCTION
,
1338 I915_GEM_DOMAIN_INSTRUCTION
);
1339 *batch
++ = results
->offset
+ offset
*sizeof(uint32_t);
1341 /* And afterwards clear the register */
1343 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1348 *batch
++ = MI_BATCH_BUFFER_END
;
1350 drm_intel_bo_mrb_exec(bo
, ALIGN((char *)batch
- (char *)bo
->virtual, 8),
1354 /* Check whether the value got written. */
1355 if (drm_intel_bo_map(results
, false) == 0) {
1356 success
= *((uint32_t *)results
->virtual + offset
) == expected_value
;
1357 drm_intel_bo_unmap(results
);
1361 drm_intel_bo_unreference(bo
);
1363 drm_intel_bo_unreference(results
);
1369 intel_detect_pipelined_so(struct intel_screen
*screen
)
1371 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1373 /* Supposedly, Broadwell just works. */
1374 if (devinfo
->gen
>= 8)
1377 if (devinfo
->gen
<= 6)
1380 /* See the big explanation about command parser versions below */
1381 if (screen
->cmd_parser_version
>= (devinfo
->is_haswell
? 7 : 2))
1384 /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
1385 * statistics registers), and we already reset it to zero before using it.
1387 return intel_detect_pipelined_register(screen
,
1388 GEN7_SO_WRITE_OFFSET(0),
1394 * Return array of MSAA modes supported by the hardware. The array is
1395 * zero-terminated and sorted in decreasing order.
1398 intel_supported_msaa_modes(const struct intel_screen
*screen
)
1400 static const int gen9_modes
[] = {16, 8, 4, 2, 0, -1};
1401 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
1402 static const int gen7_modes
[] = {8, 4, 0, -1};
1403 static const int gen6_modes
[] = {4, 0, -1};
1404 static const int gen4_modes
[] = {0, -1};
1406 if (screen
->devinfo
.gen
>= 9) {
1408 } else if (screen
->devinfo
.gen
>= 8) {
1410 } else if (screen
->devinfo
.gen
>= 7) {
1412 } else if (screen
->devinfo
.gen
== 6) {
1419 static __DRIconfig
**
1420 intel_screen_make_configs(__DRIscreen
*dri_screen
)
1422 static const mesa_format formats
[] = {
1423 MESA_FORMAT_B5G6R5_UNORM
,
1424 MESA_FORMAT_B8G8R8A8_UNORM
,
1425 MESA_FORMAT_B8G8R8X8_UNORM
1428 /* GLX_SWAP_COPY_OML is not supported due to page flipping. */
1429 static const GLenum back_buffer_modes
[] = {
1430 GLX_SWAP_UNDEFINED_OML
, GLX_NONE
,
1433 static const uint8_t singlesample_samples
[1] = {0};
1434 static const uint8_t multisample_samples
[2] = {4, 8};
1436 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1437 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1438 uint8_t depth_bits
[4], stencil_bits
[4];
1439 __DRIconfig
**configs
= NULL
;
1441 /* Generate singlesample configs without accumulation buffer. */
1442 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1443 __DRIconfig
**new_configs
;
1444 int num_depth_stencil_bits
= 2;
1446 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
1447 * buffer that has a different number of bits per pixel than the color
1448 * buffer, gen >= 6 supports this.
1451 stencil_bits
[0] = 0;
1453 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1455 stencil_bits
[1] = 0;
1456 if (devinfo
->gen
>= 6) {
1458 stencil_bits
[2] = 8;
1459 num_depth_stencil_bits
= 3;
1463 stencil_bits
[1] = 8;
1466 new_configs
= driCreateConfigs(formats
[i
],
1469 num_depth_stencil_bits
,
1470 back_buffer_modes
, 2,
1471 singlesample_samples
, 1,
1473 configs
= driConcatConfigs(configs
, new_configs
);
1476 /* Generate the minimum possible set of configs that include an
1477 * accumulation buffer.
1479 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1480 __DRIconfig
**new_configs
;
1482 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1484 stencil_bits
[0] = 0;
1487 stencil_bits
[0] = 8;
1490 new_configs
= driCreateConfigs(formats
[i
],
1491 depth_bits
, stencil_bits
, 1,
1492 back_buffer_modes
, 1,
1493 singlesample_samples
, 1,
1495 configs
= driConcatConfigs(configs
, new_configs
);
1498 /* Generate multisample configs.
1500 * This loop breaks early, and hence is a no-op, on gen < 6.
1502 * Multisample configs must follow the singlesample configs in order to
1503 * work around an X server bug present in 1.12. The X server chooses to
1504 * associate the first listed RGBA888-Z24S8 config, regardless of its
1505 * sample count, with the 32-bit depth visual used for compositing.
1507 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
1508 * supported. Singlebuffer configs are not supported because no one wants
1511 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1512 if (devinfo
->gen
< 6)
1515 __DRIconfig
**new_configs
;
1516 const int num_depth_stencil_bits
= 2;
1517 int num_msaa_modes
= 0;
1520 stencil_bits
[0] = 0;
1522 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1524 stencil_bits
[1] = 0;
1527 stencil_bits
[1] = 8;
1530 if (devinfo
->gen
>= 7)
1532 else if (devinfo
->gen
== 6)
1535 new_configs
= driCreateConfigs(formats
[i
],
1538 num_depth_stencil_bits
,
1539 back_buffer_modes
, 1,
1540 multisample_samples
,
1543 configs
= driConcatConfigs(configs
, new_configs
);
1546 if (configs
== NULL
) {
1547 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
1556 set_max_gl_versions(struct intel_screen
*screen
)
1558 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1559 const bool has_astc
= screen
->devinfo
.gen
>= 9;
1561 switch (screen
->devinfo
.gen
) {
1564 dri_screen
->max_gl_core_version
= 45;
1565 dri_screen
->max_gl_compat_version
= 30;
1566 dri_screen
->max_gl_es1_version
= 11;
1567 dri_screen
->max_gl_es2_version
= has_astc
? 32 : 31;
1570 dri_screen
->max_gl_core_version
= 33;
1571 if (screen
->devinfo
.is_haswell
&&
1572 can_do_pipelined_register_writes(screen
)) {
1573 dri_screen
->max_gl_core_version
= 42;
1574 if (can_do_compute_dispatch(screen
))
1575 dri_screen
->max_gl_core_version
= 43;
1576 if (can_do_mi_math_and_lrr(screen
))
1577 dri_screen
->max_gl_core_version
= 45;
1579 dri_screen
->max_gl_compat_version
= 30;
1580 dri_screen
->max_gl_es1_version
= 11;
1581 dri_screen
->max_gl_es2_version
= screen
->devinfo
.is_haswell
? 31 : 30;
1584 dri_screen
->max_gl_core_version
= 33;
1585 dri_screen
->max_gl_compat_version
= 30;
1586 dri_screen
->max_gl_es1_version
= 11;
1587 dri_screen
->max_gl_es2_version
= 30;
1591 dri_screen
->max_gl_core_version
= 0;
1592 dri_screen
->max_gl_compat_version
= 21;
1593 dri_screen
->max_gl_es1_version
= 11;
1594 dri_screen
->max_gl_es2_version
= 20;
1597 unreachable("unrecognized intel_screen::gen");
1602 * Return the revision (generally the revid field of the PCI header) of the
1605 * XXX: This function is useful to keep around even if it is not currently in
1606 * use. It is necessary for new platforms and revision specific workarounds or
1607 * features. Please don't remove it so that we know it at least continues to
1610 static __attribute__((__unused__
)) int
1611 brw_get_revision(int fd
)
1613 struct drm_i915_getparam gp
;
1617 memset(&gp
, 0, sizeof(gp
));
1618 gp
.param
= I915_PARAM_REVISION
;
1619 gp
.value
= &revision
;
1621 ret
= drmCommandWriteRead(fd
, DRM_I915_GETPARAM
, &gp
, sizeof(gp
));
1629 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
1631 struct brw_context
*brw
= (struct brw_context
*)data
;
1634 va_start(args
, fmt
);
1636 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
1637 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
1638 MESA_DEBUG_TYPE_OTHER
,
1639 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
1644 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
1646 struct brw_context
*brw
= (struct brw_context
*)data
;
1649 va_start(args
, fmt
);
1651 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
1653 va_copy(args_copy
, args
);
1654 vfprintf(stderr
, fmt
, args_copy
);
1658 if (brw
->perf_debug
) {
1660 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
1661 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
1662 MESA_DEBUG_TYPE_PERFORMANCE
,
1663 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
1669 * This is the driver specific part of the createNewScreen entry point.
1670 * Called when using DRI2.
1672 * \return the struct gl_config supported by this driver
1675 __DRIconfig
**intelInitScreen2(__DRIscreen
*dri_screen
)
1677 struct intel_screen
*screen
;
1679 if (dri_screen
->image
.loader
) {
1680 } else if (dri_screen
->dri2
.loader
->base
.version
<= 2 ||
1681 dri_screen
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
1683 "\nERROR! DRI2 loader with getBuffersWithFormat() "
1684 "support required\n");
1688 /* Allocate the private area */
1689 screen
= rzalloc(NULL
, struct intel_screen
);
1691 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
1694 /* parse information in __driConfigOptions */
1695 driParseOptionInfo(&screen
->optionCache
, brw_config_options
.xml
);
1697 screen
->driScrnPriv
= dri_screen
;
1698 dri_screen
->driverPrivate
= (void *) screen
;
1700 if (!intel_init_bufmgr(screen
))
1703 screen
->deviceID
= drm_intel_bufmgr_gem_get_devid(screen
->bufmgr
);
1704 if (!gen_get_device_info(screen
->deviceID
, &screen
->devinfo
))
1707 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1709 brw_process_intel_debug_variable();
1711 if (INTEL_DEBUG
& DEBUG_BUFMGR
)
1712 dri_bufmgr_set_debug(screen
->bufmgr
, true);
1714 if ((INTEL_DEBUG
& DEBUG_SHADER_TIME
) && devinfo
->gen
< 7) {
1716 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
1717 INTEL_DEBUG
&= ~DEBUG_SHADER_TIME
;
1720 if (intel_get_integer(screen
, I915_PARAM_MMAP_GTT_VERSION
) >= 1) {
1721 /* Theorectically unlimited! At least for individual objects...
1723 * Currently the entire (global) address space for all GTT maps is
1724 * limited to 64bits. That is all objects on the system that are
1725 * setup for GTT mmapping must fit within 64bits. An attempt to use
1726 * one that exceeds the limit with fail in drm_intel_bo_map_gtt().
1728 * Long before we hit that limit, we will be practically limited by
1729 * that any single object must fit in physical memory (RAM). The upper
1730 * limit on the CPU's address space is currently 48bits (Skylake), of
1731 * which only 39bits can be physical memory. (The GPU itself also has
1732 * a 48bit addressable virtual space.) We can fit over 32 million
1733 * objects of the current maximum allocable size before running out
1736 screen
->max_gtt_map_object_size
= UINT64_MAX
;
1738 /* Estimate the size of the mappable aperture into the GTT. There's an
1739 * ioctl to get the whole GTT size, but not one to get the mappable subset.
1740 * It turns out it's basically always 256MB, though some ancient hardware
1743 uint32_t gtt_size
= 256 * 1024 * 1024;
1745 /* We don't want to map two objects such that a memcpy between them would
1746 * just fault one mapping in and then the other over and over forever. So
1747 * we would need to divide the GTT size by 2. Additionally, some GTT is
1748 * taken up by things like the framebuffer and the ringbuffer and such, so
1749 * be more conservative.
1751 screen
->max_gtt_map_object_size
= gtt_size
/ 4;
1754 screen
->hw_has_swizzling
= intel_detect_swizzling(screen
);
1755 screen
->hw_has_timestamp
= intel_detect_timestamp(screen
);
1757 /* GENs prior to 8 do not support EU/Subslice info */
1758 if (devinfo
->gen
>= 8) {
1759 intel_detect_sseu(screen
);
1760 } else if (devinfo
->gen
== 7) {
1761 screen
->subslice_total
= 1 << (devinfo
->gt
- 1);
1764 /* Gen7-7.5 kernel requirements / command parser saga:
1767 * Haswell and Baytrail cannot use any privileged batchbuffer features.
1769 * Ivybridge has aliasing PPGTT on by default, which accidentally marks
1770 * all batches secure, allowing them to use any feature with no checking.
1771 * This is effectively equivalent to a command parser version of
1772 * \infinity - everything is possible.
1774 * The command parser does not exist, and querying the version will
1778 * The kernel enables the command parser by default, for systems with
1779 * aliasing PPGTT enabled (Ivybridge and Haswell). However, the
1780 * hardware checker is still enabled, so Haswell and Baytrail cannot
1783 * Ivybridge goes from "everything is possible" to "only what the
1784 * command parser allows" (if the user boots with i915.cmd_parser=0,
1785 * then everything is possible again). We can only safely use features
1786 * allowed by the supported command parser version.
1788 * Annoyingly, I915_PARAM_CMD_PARSER_VERSION reports the static version
1789 * implemented by the kernel, even if it's turned off. So, checking
1790 * for version > 0 does not mean that you can write registers. We have
1791 * to try it and see. The version does, however, indicate the age of
1794 * Instead of matching the hardware checker's behavior of converting
1795 * privileged commands to MI_NOOP, it makes execbuf2 start returning
1796 * -EINVAL, making it dangerous to try and use privileged features.
1798 * Effective command parser versions:
1799 * - Haswell: 0 (reporting 1, writes don't work)
1800 * - Baytrail: 0 (reporting 1, writes don't work)
1801 * - Ivybridge: 1 (enabled) or infinite (disabled)
1804 * Baytrail aliasing PPGTT is enabled, making it like Ivybridge:
1805 * effectively version 1 (enabled) or infinite (disabled).
1807 * - v3.19: f1f55cc0556031c8ee3fe99dae7251e78b9b653b
1808 * Command parser v2 supports predicate writes.
1810 * - Haswell: 0 (reporting 1, writes don't work)
1811 * - Baytrail: 2 (enabled) or infinite (disabled)
1812 * - Ivybridge: 2 (enabled) or infinite (disabled)
1814 * So version >= 2 is enough to know that Ivybridge and Baytrail
1815 * will work. Haswell still can't do anything.
1817 * - v4.0: Version 3 happened. Largely not relevant.
1819 * - v4.1: 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b
1820 * L3 config registers are properly saved and restored as part
1821 * of the hardware context. We can approximately detect this point
1822 * in time by checking if I915_PARAM_REVISION is recognized - it
1823 * landed in a later commit, but in the same release cycle.
1825 * - v4.2: 245054a1fe33c06ad233e0d58a27ec7b64db9284
1826 * Command parser finally gains secure batch promotion. On Haswell,
1827 * the hardware checker gets disabled, which finally allows it to do
1828 * privileged commands.
1830 * I915_PARAM_CMD_PARSER_VERSION reports 3. Effective versions:
1831 * - Haswell: 3 (enabled) or 0 (disabled)
1832 * - Baytrail: 3 (enabled) or infinite (disabled)
1833 * - Ivybridge: 3 (enabled) or infinite (disabled)
1835 * Unfortunately, detecting this point in time is tricky, because
1836 * no version bump happened when this important change occurred.
1837 * On Haswell, if we can write any register, then the kernel is at
1838 * least this new, and we can start trusting the version number.
1840 * - v4.4: 2bbe6bbb0dc94fd4ce287bdac9e1bd184e23057b and
1841 * Command parser reaches version 4, allowing access to Haswell
1842 * atomic scratch and chicken3 registers. If version >= 4, we know
1843 * the kernel is new enough to support privileged features on all
1844 * hardware. However, the user might have disabled it...and the
1845 * kernel will still report version 4. So we still have to guess
1848 * - v4.4: 7b9748cb513a6bef4af87b79f0da3ff7e8b56cd8
1849 * Command parser v5 whitelists indirect compute shader dispatch
1850 * registers, needed for OpenGL 4.3 and later.
1853 * Command parser v7 lets us use MI_MATH on Haswell.
1855 * Additionally, the kernel begins reporting version 0 when
1856 * the command parser is disabled, allowing us to skip the
1857 * guess-and-check step on Haswell. Unfortunately, this also
1858 * means that we can no longer use it as an indicator of the
1859 * age of the kernel.
1861 if (intel_get_param(screen
, I915_PARAM_CMD_PARSER_VERSION
,
1862 &screen
->cmd_parser_version
) < 0) {
1863 /* Command parser does not exist - getparam is unrecognized */
1864 screen
->cmd_parser_version
= 0;
1867 if (!intel_detect_pipelined_so(screen
)) {
1868 /* We can't do anything, so the effective version is 0. */
1869 screen
->cmd_parser_version
= 0;
1871 screen
->kernel_features
|= KERNEL_ALLOWS_SOL_OFFSET_WRITES
;
1874 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
1876 screen
->winsys_msaa_samples_override
=
1877 intel_quantize_num_samples(screen
, atoi(force_msaa
));
1878 printf("Forcing winsys sample count to %d\n",
1879 screen
->winsys_msaa_samples_override
);
1881 screen
->winsys_msaa_samples_override
= -1;
1884 set_max_gl_versions(screen
);
1886 /* Notification of GPU resets requires hardware contexts and a kernel new
1887 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
1888 * supported, calling it with a context of 0 will either generate EPERM or
1889 * no error. If the ioctl is not supported, it always generate EINVAL.
1890 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
1891 * extension to the loader.
1893 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
1895 if (devinfo
->gen
>= 6) {
1896 struct drm_i915_reset_stats stats
;
1897 memset(&stats
, 0, sizeof(stats
));
1899 const int ret
= drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
1901 screen
->has_context_reset_notification
=
1902 (ret
!= -1 || errno
!= EINVAL
);
1905 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 2)
1906 screen
->kernel_features
|= KERNEL_ALLOWS_PREDICATE_WRITES
;
1908 /* Haswell requires command parser version 4 in order to have L3
1909 * atomic scratch1 and chicken3 bits
1911 if (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 4) {
1912 screen
->kernel_features
|=
1913 KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3
;
1916 /* Haswell requires command parser version 6 in order to write to the
1917 * MI_MATH GPR registers, and version 7 in order to use
1918 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
1920 if (devinfo
->gen
>= 8 ||
1921 (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 7)) {
1922 screen
->kernel_features
|= KERNEL_ALLOWS_MI_MATH_AND_LRR
;
1925 /* Gen7 needs at least command parser version 5 to support compute */
1926 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 5)
1927 screen
->kernel_features
|= KERNEL_ALLOWS_COMPUTE_DISPATCH
;
1929 dri_screen
->extensions
= !screen
->has_context_reset_notification
1930 ? screenExtensions
: intelRobustScreenExtensions
;
1932 screen
->compiler
= brw_compiler_create(screen
, devinfo
);
1933 screen
->compiler
->shader_debug_log
= shader_debug_log_mesa
;
1934 screen
->compiler
->shader_perf_log
= shader_perf_log_mesa
;
1935 screen
->program_id
= 1;
1937 screen
->has_exec_fence
=
1938 intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_FENCE
);
1940 return (const __DRIconfig
**) intel_screen_make_configs(dri_screen
);
1943 struct intel_buffer
{
1948 static __DRIbuffer
*
1949 intelAllocateBuffer(__DRIscreen
*dri_screen
,
1950 unsigned attachment
, unsigned format
,
1951 int width
, int height
)
1953 struct intel_buffer
*intelBuffer
;
1954 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1956 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
1957 attachment
== __DRI_BUFFER_BACK_LEFT
);
1959 intelBuffer
= calloc(1, sizeof *intelBuffer
);
1960 if (intelBuffer
== NULL
)
1963 /* The front and back buffers are color buffers, which are X tiled. */
1964 uint32_t tiling
= I915_TILING_X
;
1965 unsigned long pitch
;
1966 int cpp
= format
/ 8;
1967 intelBuffer
->bo
= drm_intel_bo_alloc_tiled(screen
->bufmgr
,
1968 "intelAllocateBuffer",
1973 BO_ALLOC_FOR_RENDER
);
1975 if (intelBuffer
->bo
== NULL
) {
1980 drm_intel_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
1982 intelBuffer
->base
.attachment
= attachment
;
1983 intelBuffer
->base
.cpp
= cpp
;
1984 intelBuffer
->base
.pitch
= pitch
;
1986 return &intelBuffer
->base
;
1990 intelReleaseBuffer(__DRIscreen
*dri_screen
, __DRIbuffer
*buffer
)
1992 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
1994 drm_intel_bo_unreference(intelBuffer
->bo
);
1998 static const struct __DriverAPIRec brw_driver_api
= {
1999 .InitScreen
= intelInitScreen2
,
2000 .DestroyScreen
= intelDestroyScreen
,
2001 .CreateContext
= brwCreateContext
,
2002 .DestroyContext
= intelDestroyContext
,
2003 .CreateBuffer
= intelCreateBuffer
,
2004 .DestroyBuffer
= intelDestroyBuffer
,
2005 .MakeCurrent
= intelMakeCurrent
,
2006 .UnbindContext
= intelUnbindContext
,
2007 .AllocateBuffer
= intelAllocateBuffer
,
2008 .ReleaseBuffer
= intelReleaseBuffer
2011 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
2012 .base
= { __DRI_DRIVER_VTABLE
, 1 },
2013 .vtable
= &brw_driver_api
,
2016 static const __DRIextension
*brw_driver_extensions
[] = {
2017 &driCoreExtension
.base
,
2018 &driImageDriverExtension
.base
,
2019 &driDRI2Extension
.base
,
2021 &brw_config_options
.base
,
2025 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
2027 globalDriverAPI
= &brw_driver_api
;
2029 return brw_driver_extensions
;