2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include <drm_fourcc.h>
30 #include "main/context.h"
31 #include "main/framebuffer.h"
32 #include "main/renderbuffer.h"
33 #include "main/texobj.h"
34 #include "main/hash.h"
35 #include "main/fbobject.h"
36 #include "main/version.h"
37 #include "swrast/s_renderbuffer.h"
38 #include "util/ralloc.h"
39 #include "brw_defines.h"
40 #include "brw_state.h"
41 #include "compiler/nir/nir.h"
46 #ifndef DRM_FORMAT_MOD_INVALID
47 #define DRM_FORMAT_MOD_INVALID ((1ULL<<56) - 1)
50 #ifndef DRM_FORMAT_MOD_LINEAR
51 #define DRM_FORMAT_MOD_LINEAR 0
54 static const __DRIconfigOptionsExtension brw_config_options
= {
55 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
58 DRI_CONF_SECTION_PERFORMANCE
59 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
60 * DRI_CONF_BO_REUSE_ALL
62 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
63 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
64 DRI_CONF_ENUM(0, "Disable buffer object reuse")
65 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
70 DRI_CONF_SECTION_QUALITY
71 DRI_CONF_FORCE_S3TC_ENABLE("false")
73 DRI_CONF_PRECISE_TRIG("false")
75 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
76 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
77 "given integer. If negative, then do not clamp.")
81 DRI_CONF_SECTION_DEBUG
82 DRI_CONF_NO_RAST("false")
83 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
84 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
85 DRI_CONF_DISABLE_THROTTLING("false")
86 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
87 DRI_CONF_FORCE_GLSL_VERSION(0)
88 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
89 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
90 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
91 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
92 DRI_CONF_ALLOW_GLSL_BUILTIN_VARIABLE_REDECLARATION("false")
93 DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
94 DRI_CONF_FORCE_GLSL_ABS_SQRT("false")
96 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
97 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
101 DRI_CONF_SECTION_MISCELLANEOUS
102 DRI_CONF_GLSL_ZERO_INIT("false")
107 #include "intel_batchbuffer.h"
108 #include "intel_buffers.h"
109 #include "brw_bufmgr.h"
110 #include "intel_fbo.h"
111 #include "intel_mipmap_tree.h"
112 #include "intel_screen.h"
113 #include "intel_tex.h"
114 #include "intel_image.h"
116 #include "brw_context.h"
118 #include "i915_drm.h"
121 * For debugging purposes, this returns a time in seconds.
128 clock_gettime(CLOCK_MONOTONIC
, &tp
);
130 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
133 static const __DRItexBufferExtension intelTexBufferExtension
= {
134 .base
= { __DRI_TEX_BUFFER
, 3 },
136 .setTexBuffer
= intelSetTexBuffer
,
137 .setTexBuffer2
= intelSetTexBuffer2
,
138 .releaseTexBuffer
= NULL
,
142 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
143 __DRIdrawable
*dPriv
,
145 enum __DRI2throttleReason reason
)
147 struct brw_context
*brw
= cPriv
->driverPrivate
;
152 struct gl_context
*ctx
= &brw
->ctx
;
154 FLUSH_VERTICES(ctx
, 0);
156 if (flags
& __DRI2_FLUSH_DRAWABLE
)
157 intel_resolve_for_dri2_flush(brw
, dPriv
);
159 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
)
160 brw
->need_swap_throttle
= true;
161 if (reason
== __DRI2_THROTTLE_FLUSHFRONT
)
162 brw
->need_flush_throttle
= true;
164 intel_batchbuffer_flush(brw
);
168 * Provides compatibility with loaders that only support the older (version
169 * 1-3) flush interface.
171 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
174 intel_dri2_flush(__DRIdrawable
*drawable
)
176 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
177 __DRI2_FLUSH_DRAWABLE
,
178 __DRI2_THROTTLE_SWAPBUFFER
);
181 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
182 .base
= { __DRI2_FLUSH
, 4 },
184 .flush
= intel_dri2_flush
,
185 .invalidate
= dri2InvalidateDrawable
,
186 .flush_with_flags
= intel_dri2_flush_with_flags
,
189 static struct intel_image_format intel_image_formats
[] = {
190 { __DRI_IMAGE_FOURCC_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
191 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
193 { __DRI_IMAGE_FOURCC_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
194 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
196 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
197 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
199 { __DRI_IMAGE_FOURCC_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
200 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
202 { __DRI_IMAGE_FOURCC_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
203 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
205 { __DRI_IMAGE_FOURCC_ARGB1555
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
206 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555
, 2 } } },
208 { __DRI_IMAGE_FOURCC_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
209 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
211 { __DRI_IMAGE_FOURCC_R8
, __DRI_IMAGE_COMPONENTS_R
, 1,
212 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 }, } },
214 { __DRI_IMAGE_FOURCC_R16
, __DRI_IMAGE_COMPONENTS_R
, 1,
215 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 1 }, } },
217 { __DRI_IMAGE_FOURCC_GR88
, __DRI_IMAGE_COMPONENTS_RG
, 1,
218 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 }, } },
220 { __DRI_IMAGE_FOURCC_GR1616
, __DRI_IMAGE_COMPONENTS_RG
, 1,
221 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616
, 2 }, } },
223 { __DRI_IMAGE_FOURCC_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
224 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
225 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
226 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
228 { __DRI_IMAGE_FOURCC_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
229 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
230 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
231 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
233 { __DRI_IMAGE_FOURCC_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
234 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
235 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
236 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
238 { __DRI_IMAGE_FOURCC_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
239 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
240 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
241 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
243 { __DRI_IMAGE_FOURCC_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
244 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
245 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
246 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
248 { __DRI_IMAGE_FOURCC_YVU410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
249 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
250 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
251 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
253 { __DRI_IMAGE_FOURCC_YVU411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
254 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
255 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
256 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
258 { __DRI_IMAGE_FOURCC_YVU420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
259 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
260 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
261 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
263 { __DRI_IMAGE_FOURCC_YVU422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
264 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
265 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
266 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
268 { __DRI_IMAGE_FOURCC_YVU444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
269 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
270 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
271 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
273 { __DRI_IMAGE_FOURCC_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
274 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
275 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
277 { __DRI_IMAGE_FOURCC_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
278 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
279 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
281 /* For YUYV and UYVY buffers, we set up two overlapping DRI images
282 * and treat them as planar buffers in the compositors.
283 * Plane 0 is GR88 and samples YU or YV pairs and places Y into
284 * the R component, while plane 1 is ARGB/ABGR and samples YUYV/UYVY
285 * clusters and places pairs and places U into the G component and
286 * V into A. This lets the texture sampler interpolate the Y
287 * components correctly when sampling from plane 0, and interpolate
288 * U and V correctly when sampling from plane 1. */
289 { __DRI_IMAGE_FOURCC_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
290 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
291 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
292 { __DRI_IMAGE_FOURCC_UYVY
, __DRI_IMAGE_COMPONENTS_Y_UXVX
, 2,
293 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
294 { 0, 1, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } }
297 static const struct {
300 } supported_modifiers
[] = {
301 { .modifier
= DRM_FORMAT_MOD_LINEAR
, .since_gen
= 1 },
302 { .modifier
= I915_FORMAT_MOD_X_TILED
, .since_gen
= 1 },
303 { .modifier
= I915_FORMAT_MOD_Y_TILED
, .since_gen
= 6 },
307 modifier_is_supported(const struct gen_device_info
*devinfo
,
312 for (i
= 0; i
< ARRAY_SIZE(supported_modifiers
); i
++) {
313 if (supported_modifiers
[i
].modifier
!= modifier
)
316 return supported_modifiers
[i
].since_gen
<= devinfo
->gen
;
323 tiling_to_modifier(uint32_t tiling
)
325 static const uint64_t map
[] = {
326 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
327 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
328 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
331 assert(tiling
< ARRAY_SIZE(map
));
337 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
339 uint32_t tiling
, swizzle
;
340 brw_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
342 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
343 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
344 func
, image
->offset
);
348 static struct intel_image_format
*
349 intel_image_format_lookup(int fourcc
)
351 struct intel_image_format
*f
= NULL
;
353 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
354 if (intel_image_formats
[i
].fourcc
== fourcc
) {
355 f
= &intel_image_formats
[i
];
363 static boolean
intel_lookup_fourcc(int dri_format
, int *fourcc
)
365 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
366 if (intel_image_formats
[i
].planes
[0].dri_format
== dri_format
) {
367 *fourcc
= intel_image_formats
[i
].fourcc
;
375 intel_allocate_image(struct intel_screen
*screen
, int dri_format
,
380 image
= calloc(1, sizeof *image
);
384 image
->screen
= screen
;
385 image
->dri_format
= dri_format
;
388 image
->format
= driImageFormatToGLFormat(dri_format
);
389 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
390 image
->format
== MESA_FORMAT_NONE
) {
395 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
396 image
->data
= loaderPrivate
;
402 * Sets up a DRIImage structure to point to a slice out of a miptree.
405 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
406 struct intel_mipmap_tree
*mt
, GLuint level
,
409 intel_miptree_make_shareable(brw
, mt
);
411 intel_miptree_check_level_layer(mt
, level
, zoffset
);
413 image
->width
= minify(mt
->physical_width0
, level
- mt
->first_level
);
414 image
->height
= minify(mt
->physical_height0
, level
- mt
->first_level
);
415 image
->pitch
= mt
->pitch
;
417 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
421 brw_bo_unreference(image
->bo
);
423 brw_bo_reference(mt
->bo
);
427 intel_create_image_from_name(__DRIscreen
*dri_screen
,
428 int width
, int height
, int format
,
429 int name
, int pitch
, void *loaderPrivate
)
431 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
435 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
439 if (image
->format
== MESA_FORMAT_NONE
)
442 cpp
= _mesa_get_format_bytes(image
->format
);
444 image
->width
= width
;
445 image
->height
= height
;
446 image
->pitch
= pitch
* cpp
;
447 image
->bo
= brw_bo_gem_create_from_name(screen
->bufmgr
, "image",
453 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
459 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
460 int renderbuffer
, void *loaderPrivate
)
463 struct brw_context
*brw
= context
->driverPrivate
;
464 struct gl_context
*ctx
= &brw
->ctx
;
465 struct gl_renderbuffer
*rb
;
466 struct intel_renderbuffer
*irb
;
468 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
470 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
474 irb
= intel_renderbuffer(rb
);
475 intel_miptree_make_shareable(brw
, irb
->mt
);
476 image
= calloc(1, sizeof *image
);
480 image
->internal_format
= rb
->InternalFormat
;
481 image
->format
= rb
->Format
;
482 image
->modifier
= tiling_to_modifier(
483 isl_tiling_to_i915_tiling(irb
->mt
->surf
.tiling
));
485 image
->data
= loaderPrivate
;
486 brw_bo_unreference(image
->bo
);
487 image
->bo
= irb
->mt
->bo
;
488 brw_bo_reference(irb
->mt
->bo
);
489 image
->width
= rb
->Width
;
490 image
->height
= rb
->Height
;
491 image
->pitch
= irb
->mt
->pitch
;
492 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
493 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
495 rb
->NeedsFinishRenderTexture
= true;
500 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
501 unsigned texture
, int zoffset
,
507 struct brw_context
*brw
= context
->driverPrivate
;
508 struct gl_texture_object
*obj
;
509 struct intel_texture_object
*iobj
;
512 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
513 if (!obj
|| obj
->Target
!= target
) {
514 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
518 if (target
== GL_TEXTURE_CUBE_MAP
)
521 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
522 iobj
= intel_texture_object(obj
);
523 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
524 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
528 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
529 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
533 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
534 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
537 image
= calloc(1, sizeof *image
);
539 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
543 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
544 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
545 image
->modifier
= tiling_to_modifier(
546 isl_tiling_to_i915_tiling(iobj
->mt
->surf
.tiling
));
547 image
->data
= loaderPrivate
;
548 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
549 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
550 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
551 if (image
->dri_format
== MESA_FORMAT_NONE
) {
552 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
557 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
562 intel_destroy_image(__DRIimage
*image
)
564 brw_bo_unreference(image
->bo
);
568 enum modifier_priority
{
569 MODIFIER_PRIORITY_INVALID
= 0,
570 MODIFIER_PRIORITY_LINEAR
,
575 const uint64_t priority_to_modifier
[] = {
576 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
577 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
578 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
579 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
583 select_best_modifier(struct gen_device_info
*devinfo
,
584 const uint64_t *modifiers
,
585 const unsigned count
)
587 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
589 for (int i
= 0; i
< count
; i
++) {
590 if (!modifier_is_supported(devinfo
, modifiers
[i
]))
593 switch (modifiers
[i
]) {
594 case I915_FORMAT_MOD_Y_TILED
:
595 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
597 case I915_FORMAT_MOD_X_TILED
:
598 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
600 case DRM_FORMAT_MOD_LINEAR
:
601 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
603 case DRM_FORMAT_MOD_INVALID
:
609 return priority_to_modifier
[prio
];
613 intel_create_image_common(__DRIscreen
*dri_screen
,
614 int width
, int height
, int format
,
616 const uint64_t *modifiers
,
621 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
622 uint64_t modifier
= DRM_FORMAT_MOD_INVALID
;
625 /* Callers of this may specify a modifier, or a dri usage, but not both. The
626 * newer modifier interface deprecates the older usage flags newer modifier
627 * interface deprecates the older usage flags.
629 assert(!(use
&& count
));
631 if (use
& __DRI_IMAGE_USE_CURSOR
) {
632 if (width
!= 64 || height
!= 64)
634 modifier
= DRM_FORMAT_MOD_LINEAR
;
637 if (use
& __DRI_IMAGE_USE_LINEAR
)
638 modifier
= DRM_FORMAT_MOD_LINEAR
;
640 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
642 /* User requested specific modifiers */
643 modifier
= select_best_modifier(&screen
->devinfo
, modifiers
, count
);
644 if (modifier
== DRM_FORMAT_MOD_INVALID
)
647 /* Historically, X-tiled was the default, and so lack of modifier means
650 modifier
= I915_FORMAT_MOD_X_TILED
;
654 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
658 const struct isl_drm_modifier_info
*mod_info
=
659 isl_drm_modifier_get_info(modifier
);
661 struct isl_surf surf
;
662 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
663 .dim
= ISL_SURF_DIM_2D
,
664 .format
= brw_isl_format_for_mesa_format(image
->format
),
671 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
672 ISL_SURF_USAGE_TEXTURE_BIT
|
673 ISL_SURF_USAGE_STORAGE_BIT
,
674 .tiling_flags
= (1 << mod_info
->tiling
));
681 /* We request that the bufmgr zero because, if a buffer gets re-used from
682 * the pool, we don't want to leak random garbage from our process to some
685 image
->bo
= brw_bo_alloc_tiled(screen
->bufmgr
, "image", surf
.size
,
686 isl_tiling_to_i915_tiling(mod_info
->tiling
),
687 surf
.row_pitch
, BO_ALLOC_ZEROED
);
688 if (image
->bo
== NULL
) {
692 image
->width
= width
;
693 image
->height
= height
;
694 image
->pitch
= surf
.row_pitch
;
695 image
->modifier
= modifier
;
701 intel_create_image(__DRIscreen
*dri_screen
,
702 int width
, int height
, int format
,
706 return intel_create_image_common(dri_screen
, width
, height
, format
, use
, NULL
, 0,
711 intel_create_image_with_modifiers(__DRIscreen
*dri_screen
,
712 int width
, int height
, int format
,
713 const uint64_t *modifiers
,
714 const unsigned count
,
717 return intel_create_image_common(dri_screen
, width
, height
, format
, 0,
718 modifiers
, count
, loaderPrivate
);
722 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
725 case __DRI_IMAGE_ATTRIB_STRIDE
:
726 *value
= image
->pitch
;
728 case __DRI_IMAGE_ATTRIB_HANDLE
:
729 *value
= image
->bo
->gem_handle
;
731 case __DRI_IMAGE_ATTRIB_NAME
:
732 return !brw_bo_flink(image
->bo
, (uint32_t *) value
);
733 case __DRI_IMAGE_ATTRIB_FORMAT
:
734 *value
= image
->dri_format
;
736 case __DRI_IMAGE_ATTRIB_WIDTH
:
737 *value
= image
->width
;
739 case __DRI_IMAGE_ATTRIB_HEIGHT
:
740 *value
= image
->height
;
742 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
743 if (image
->planar_format
== NULL
)
745 *value
= image
->planar_format
->components
;
747 case __DRI_IMAGE_ATTRIB_FD
:
748 return !brw_bo_gem_export_to_prime(image
->bo
, value
);
749 case __DRI_IMAGE_ATTRIB_FOURCC
:
750 return intel_lookup_fourcc(image
->dri_format
, value
);
751 case __DRI_IMAGE_ATTRIB_NUM_PLANES
:
754 case __DRI_IMAGE_ATTRIB_OFFSET
:
755 *value
= image
->offset
;
757 case __DRI_IMAGE_ATTRIB_MODIFIER_LOWER
:
758 *value
= (image
->modifier
& 0xffffffff);
760 case __DRI_IMAGE_ATTRIB_MODIFIER_UPPER
:
761 *value
= ((image
->modifier
>> 32) & 0xffffffff);
770 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
774 image
= calloc(1, sizeof *image
);
778 brw_bo_reference(orig_image
->bo
);
779 image
->bo
= orig_image
->bo
;
780 image
->internal_format
= orig_image
->internal_format
;
781 image
->planar_format
= orig_image
->planar_format
;
782 image
->dri_format
= orig_image
->dri_format
;
783 image
->format
= orig_image
->format
;
784 image
->modifier
= orig_image
->modifier
;
785 image
->offset
= orig_image
->offset
;
786 image
->width
= orig_image
->width
;
787 image
->height
= orig_image
->height
;
788 image
->pitch
= orig_image
->pitch
;
789 image
->tile_x
= orig_image
->tile_x
;
790 image
->tile_y
= orig_image
->tile_y
;
791 image
->has_depthstencil
= orig_image
->has_depthstencil
;
792 image
->data
= loaderPrivate
;
794 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
795 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
801 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
803 if (use
& __DRI_IMAGE_USE_CURSOR
) {
804 if (image
->width
!= 64 || image
->height
!= 64)
812 intel_create_image_from_names(__DRIscreen
*dri_screen
,
813 int width
, int height
, int fourcc
,
814 int *names
, int num_names
,
815 int *strides
, int *offsets
,
818 struct intel_image_format
*f
= NULL
;
822 if (dri_screen
== NULL
|| names
== NULL
|| num_names
!= 1)
825 f
= intel_image_format_lookup(fourcc
);
829 image
= intel_create_image_from_name(dri_screen
, width
, height
,
830 __DRI_IMAGE_FORMAT_NONE
,
831 names
[0], strides
[0],
837 image
->planar_format
= f
;
838 for (i
= 0; i
< f
->nplanes
; i
++) {
839 index
= f
->planes
[i
].buffer_index
;
840 image
->offsets
[index
] = offsets
[index
];
841 image
->strides
[index
] = strides
[index
];
848 intel_create_image_from_fds_common(__DRIscreen
*dri_screen
,
849 int width
, int height
, int fourcc
,
850 uint64_t modifier
, int *fds
, int num_fds
,
851 int *strides
, int *offsets
,
854 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
855 struct intel_image_format
*f
;
860 if (fds
== NULL
|| num_fds
< 1)
863 f
= intel_image_format_lookup(fourcc
);
867 if (modifier
!= DRM_FORMAT_MOD_INVALID
&&
868 !modifier_is_supported(&screen
->devinfo
, modifier
))
872 image
= intel_allocate_image(screen
, f
->planes
[0].dri_format
,
875 image
= intel_allocate_image(screen
, __DRI_IMAGE_FORMAT_NONE
,
881 image
->width
= width
;
882 image
->height
= height
;
883 image
->pitch
= strides
[0];
885 image
->planar_format
= f
;
887 image
->bo
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[0]);
888 if (image
->bo
== NULL
) {
893 /* We only support all planes from the same bo.
894 * brw_bo_gem_create_from_prime() should return the same pointer for all
895 * fds received here */
896 for (i
= 1; i
< num_fds
; i
++) {
897 struct brw_bo
*aux
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[i
]);
898 brw_bo_unreference(aux
);
899 if (aux
!= image
->bo
) {
900 brw_bo_unreference(image
->bo
);
906 if (modifier
!= DRM_FORMAT_MOD_INVALID
)
907 image
->modifier
= modifier
;
909 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
912 for (i
= 0; i
< f
->nplanes
; i
++) {
913 index
= f
->planes
[i
].buffer_index
;
914 image
->offsets
[index
] = offsets
[index
];
915 image
->strides
[index
] = strides
[index
];
917 const struct isl_drm_modifier_info
*mod_info
=
918 isl_drm_modifier_get_info(image
->modifier
);
920 mesa_format format
= driImageFormatToGLFormat(f
->planes
[i
].dri_format
);
922 struct isl_surf surf
;
923 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
924 .dim
= ISL_SURF_DIM_2D
,
925 .format
= brw_isl_format_for_mesa_format(format
),
926 .width
= image
->width
>> f
->planes
[i
].width_shift
,
927 .height
= image
->height
>> f
->planes
[i
].height_shift
,
932 .row_pitch
= strides
[index
],
933 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
934 ISL_SURF_USAGE_TEXTURE_BIT
|
935 ISL_SURF_USAGE_STORAGE_BIT
,
936 .tiling_flags
= (1 << mod_info
->tiling
));
938 brw_bo_unreference(image
->bo
);
943 const int end
= offsets
[index
] + surf
.size
;
948 /* Check that the requested image actually fits within the BO. 'size'
949 * is already relative to the offsets, so we don't need to add that. */
950 if (image
->bo
->size
== 0) {
951 image
->bo
->size
= size
;
952 } else if (size
> image
->bo
->size
) {
953 brw_bo_unreference(image
->bo
);
958 if (f
->nplanes
== 1) {
959 image
->offset
= image
->offsets
[0];
960 intel_image_warn_if_unaligned(image
, __func__
);
967 intel_create_image_from_fds(__DRIscreen
*dri_screen
,
968 int width
, int height
, int fourcc
,
969 int *fds
, int num_fds
, int *strides
, int *offsets
,
972 return intel_create_image_from_fds_common(dri_screen
, width
, height
, fourcc
,
973 DRM_FORMAT_MOD_INVALID
,
974 fds
, num_fds
, strides
, offsets
,
979 intel_create_image_from_dma_bufs2(__DRIscreen
*dri_screen
,
980 int width
, int height
,
981 int fourcc
, uint64_t modifier
,
982 int *fds
, int num_fds
,
983 int *strides
, int *offsets
,
984 enum __DRIYUVColorSpace yuv_color_space
,
985 enum __DRISampleRange sample_range
,
986 enum __DRIChromaSiting horizontal_siting
,
987 enum __DRIChromaSiting vertical_siting
,
992 struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
995 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
999 image
= intel_create_image_from_fds_common(dri_screen
, width
, height
,
1001 fds
, num_fds
, strides
, offsets
,
1005 * Invalid parameters and any inconsistencies between are assumed to be
1006 * checked by the caller. Therefore besides unsupported formats one can fail
1007 * only in allocation.
1010 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
1014 image
->dma_buf_imported
= true;
1015 image
->yuv_color_space
= yuv_color_space
;
1016 image
->sample_range
= sample_range
;
1017 image
->horizontal_siting
= horizontal_siting
;
1018 image
->vertical_siting
= vertical_siting
;
1020 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
1025 intel_create_image_from_dma_bufs(__DRIscreen
*dri_screen
,
1026 int width
, int height
, int fourcc
,
1027 int *fds
, int num_fds
,
1028 int *strides
, int *offsets
,
1029 enum __DRIYUVColorSpace yuv_color_space
,
1030 enum __DRISampleRange sample_range
,
1031 enum __DRIChromaSiting horizontal_siting
,
1032 enum __DRIChromaSiting vertical_siting
,
1034 void *loaderPrivate
)
1036 return intel_create_image_from_dma_bufs2(dri_screen
, width
, height
,
1037 fourcc
, DRM_FORMAT_MOD_INVALID
,
1038 fds
, num_fds
, strides
, offsets
,
1048 intel_query_dma_buf_formats(__DRIscreen
*screen
, int max
,
1049 int *formats
, int *count
)
1054 *count
= ARRAY_SIZE(intel_image_formats
) - 1; /* not SARGB */
1058 for (i
= 0; i
< (ARRAY_SIZE(intel_image_formats
)) && j
< max
; i
++) {
1059 if (intel_image_formats
[i
].fourcc
== __DRI_IMAGE_FOURCC_SARGB8888
)
1061 formats
[j
++] = intel_image_formats
[i
].fourcc
;
1069 intel_query_dma_buf_modifiers(__DRIscreen
*_screen
, int fourcc
, int max
,
1070 uint64_t *modifiers
,
1071 unsigned int *external_only
,
1074 struct intel_screen
*screen
= _screen
->driverPrivate
;
1075 struct intel_image_format
*f
;
1076 int num_mods
= 0, i
;
1078 f
= intel_image_format_lookup(fourcc
);
1082 for (i
= 0; i
< ARRAY_SIZE(supported_modifiers
); i
++) {
1083 uint64_t modifier
= supported_modifiers
[i
].modifier
;
1084 if (!modifier_is_supported(&screen
->devinfo
, modifier
))
1091 modifiers
[num_mods
- 1] = modifier
;
1092 if (num_mods
>= max
)
1096 if (external_only
!= NULL
) {
1097 for (i
= 0; i
< num_mods
&& i
< max
; i
++) {
1098 if (f
->components
== __DRI_IMAGE_COMPONENTS_Y_U_V
||
1099 f
->components
== __DRI_IMAGE_COMPONENTS_Y_UV
||
1100 f
->components
== __DRI_IMAGE_COMPONENTS_Y_XUXV
) {
1101 external_only
[i
] = GL_TRUE
;
1104 external_only
[i
] = GL_FALSE
;
1114 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
1116 int width
, height
, offset
, stride
, dri_format
, index
;
1117 struct intel_image_format
*f
;
1120 if (parent
== NULL
|| parent
->planar_format
== NULL
)
1123 f
= parent
->planar_format
;
1125 if (plane
>= f
->nplanes
)
1128 width
= parent
->width
>> f
->planes
[plane
].width_shift
;
1129 height
= parent
->height
>> f
->planes
[plane
].height_shift
;
1130 dri_format
= f
->planes
[plane
].dri_format
;
1131 index
= f
->planes
[plane
].buffer_index
;
1132 offset
= parent
->offsets
[index
];
1133 stride
= parent
->strides
[index
];
1135 image
= intel_allocate_image(parent
->screen
, dri_format
, loaderPrivate
);
1139 if (offset
+ height
* stride
> parent
->bo
->size
) {
1140 _mesa_warning(NULL
, "intel_create_sub_image: subimage out of bounds");
1145 image
->bo
= parent
->bo
;
1146 brw_bo_reference(parent
->bo
);
1147 image
->modifier
= parent
->modifier
;
1149 image
->width
= width
;
1150 image
->height
= height
;
1151 image
->pitch
= stride
;
1152 image
->offset
= offset
;
1154 intel_image_warn_if_unaligned(image
, __func__
);
1159 static const __DRIimageExtension intelImageExtension
= {
1160 .base
= { __DRI_IMAGE
, 15 },
1162 .createImageFromName
= intel_create_image_from_name
,
1163 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
1164 .destroyImage
= intel_destroy_image
,
1165 .createImage
= intel_create_image
,
1166 .queryImage
= intel_query_image
,
1167 .dupImage
= intel_dup_image
,
1168 .validateUsage
= intel_validate_usage
,
1169 .createImageFromNames
= intel_create_image_from_names
,
1170 .fromPlanar
= intel_from_planar
,
1171 .createImageFromTexture
= intel_create_image_from_texture
,
1172 .createImageFromFds
= intel_create_image_from_fds
,
1173 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
,
1175 .getCapabilities
= NULL
,
1178 .createImageWithModifiers
= intel_create_image_with_modifiers
,
1179 .createImageFromDmaBufs2
= intel_create_image_from_dma_bufs2
,
1180 .queryDmaBufFormats
= intel_query_dma_buf_formats
,
1181 .queryDmaBufModifiers
= intel_query_dma_buf_modifiers
,
1185 get_aperture_size(int fd
)
1187 struct drm_i915_gem_get_aperture aperture
;
1189 if (drmIoctl(fd
, DRM_IOCTL_I915_GEM_GET_APERTURE
, &aperture
) != 0)
1192 return aperture
.aper_size
;
1196 brw_query_renderer_integer(__DRIscreen
*dri_screen
,
1197 int param
, unsigned int *value
)
1199 const struct intel_screen
*const screen
=
1200 (struct intel_screen
*) dri_screen
->driverPrivate
;
1203 case __DRI2_RENDERER_VENDOR_ID
:
1206 case __DRI2_RENDERER_DEVICE_ID
:
1207 value
[0] = screen
->deviceID
;
1209 case __DRI2_RENDERER_ACCELERATED
:
1212 case __DRI2_RENDERER_VIDEO_MEMORY
: {
1213 /* Once a batch uses more than 75% of the maximum mappable size, we
1214 * assume that there's some fragmentation, and we start doing extra
1215 * flushing, etc. That's the big cliff apps will care about.
1217 const unsigned gpu_mappable_megabytes
=
1218 screen
->aperture_threshold
/ (1024 * 1024);
1220 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
1221 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
1223 if (system_memory_pages
<= 0 || system_page_size
<= 0)
1226 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
1227 * (uint64_t) system_page_size
;
1229 const unsigned system_memory_megabytes
=
1230 (unsigned) (system_memory_bytes
/ (1024 * 1024));
1232 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
1235 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
1238 case __DRI2_RENDERER_HAS_TEXTURE_3D
:
1242 return driQueryRendererIntegerCommon(dri_screen
, param
, value
);
1249 brw_query_renderer_string(__DRIscreen
*dri_screen
,
1250 int param
, const char **value
)
1252 const struct intel_screen
*screen
=
1253 (struct intel_screen
*) dri_screen
->driverPrivate
;
1256 case __DRI2_RENDERER_VENDOR_ID
:
1257 value
[0] = brw_vendor_string
;
1259 case __DRI2_RENDERER_DEVICE_ID
:
1260 value
[0] = brw_get_renderer_string(screen
);
1269 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
1270 .base
= { __DRI2_RENDERER_QUERY
, 1 },
1272 .queryInteger
= brw_query_renderer_integer
,
1273 .queryString
= brw_query_renderer_string
1276 static const __DRIrobustnessExtension dri2Robustness
= {
1277 .base
= { __DRI2_ROBUSTNESS
, 1 }
1280 static const __DRIextension
*screenExtensions
[] = {
1281 &intelTexBufferExtension
.base
,
1282 &intelFenceExtension
.base
,
1283 &intelFlushExtension
.base
,
1284 &intelImageExtension
.base
,
1285 &intelRendererQueryExtension
.base
,
1286 &dri2ConfigQueryExtension
.base
,
1287 &dri2NoErrorExtension
.base
,
1291 static const __DRIextension
*intelRobustScreenExtensions
[] = {
1292 &intelTexBufferExtension
.base
,
1293 &intelFenceExtension
.base
,
1294 &intelFlushExtension
.base
,
1295 &intelImageExtension
.base
,
1296 &intelRendererQueryExtension
.base
,
1297 &dri2ConfigQueryExtension
.base
,
1298 &dri2Robustness
.base
,
1299 &dri2NoErrorExtension
.base
,
1304 intel_get_param(struct intel_screen
*screen
, int param
, int *value
)
1307 struct drm_i915_getparam gp
;
1309 memset(&gp
, 0, sizeof(gp
));
1313 if (drmIoctl(screen
->driScrnPriv
->fd
, DRM_IOCTL_I915_GETPARAM
, &gp
) == -1) {
1316 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
1323 intel_get_boolean(struct intel_screen
*screen
, int param
)
1326 return (intel_get_param(screen
, param
, &value
) == 0) && value
;
1330 intel_get_integer(struct intel_screen
*screen
, int param
)
1334 if (intel_get_param(screen
, param
, &value
) == 0)
1341 intelDestroyScreen(__DRIscreen
* sPriv
)
1343 struct intel_screen
*screen
= sPriv
->driverPrivate
;
1345 brw_bufmgr_destroy(screen
->bufmgr
);
1346 driDestroyOptionInfo(&screen
->optionCache
);
1348 ralloc_free(screen
);
1349 sPriv
->driverPrivate
= NULL
;
1354 * Create a gl_framebuffer and attach it to __DRIdrawable::driverPrivate.
1356 *_This implements driDriverAPI::createNewDrawable, which the DRI layer calls
1357 * when creating a EGLSurface, GLXDrawable, or GLXPixmap. Despite the name,
1358 * this does not allocate GPU memory.
1361 intelCreateBuffer(__DRIscreen
*dri_screen
,
1362 __DRIdrawable
* driDrawPriv
,
1363 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
1365 struct intel_renderbuffer
*rb
;
1366 struct intel_screen
*screen
= (struct intel_screen
*)
1367 dri_screen
->driverPrivate
;
1368 mesa_format rgbFormat
;
1369 unsigned num_samples
=
1370 intel_quantize_num_samples(screen
, mesaVis
->samples
);
1375 struct gl_framebuffer
*fb
= CALLOC_STRUCT(gl_framebuffer
);
1379 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
1381 if (screen
->winsys_msaa_samples_override
!= -1) {
1382 num_samples
= screen
->winsys_msaa_samples_override
;
1383 fb
->Visual
.samples
= num_samples
;
1386 if (mesaVis
->redBits
== 5) {
1387 rgbFormat
= mesaVis
->redMask
== 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1388 : MESA_FORMAT_B5G6R5_UNORM
;
1389 } else if (mesaVis
->sRGBCapable
) {
1390 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1391 : MESA_FORMAT_B8G8R8A8_SRGB
;
1392 } else if (mesaVis
->alphaBits
== 0) {
1393 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8X8_UNORM
1394 : MESA_FORMAT_B8G8R8X8_UNORM
;
1396 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1397 : MESA_FORMAT_B8G8R8A8_SRGB
;
1398 fb
->Visual
.sRGBCapable
= true;
1401 /* setup the hardware-based renderbuffers */
1402 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1403 _mesa_attach_and_own_rb(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
1405 if (mesaVis
->doubleBufferMode
) {
1406 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1407 _mesa_attach_and_own_rb(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1411 * Assert here that the gl_config has an expected depth/stencil bit
1412 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1413 * which constructs the advertised configs.)
1415 if (mesaVis
->depthBits
== 24) {
1416 assert(mesaVis
->stencilBits
== 8);
1418 if (screen
->devinfo
.has_hiz_and_separate_stencil
) {
1419 rb
= intel_create_private_renderbuffer(screen
,
1420 MESA_FORMAT_Z24_UNORM_X8_UINT
,
1422 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1423 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_S_UINT8
,
1425 _mesa_attach_and_own_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1428 * Use combined depth/stencil. Note that the renderbuffer is
1429 * attached to two attachment points.
1431 rb
= intel_create_private_renderbuffer(screen
,
1432 MESA_FORMAT_Z24_UNORM_S8_UINT
,
1434 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1435 _mesa_attach_and_reference_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1438 else if (mesaVis
->depthBits
== 16) {
1439 assert(mesaVis
->stencilBits
== 0);
1440 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_Z_UNORM16
,
1442 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1445 assert(mesaVis
->depthBits
== 0);
1446 assert(mesaVis
->stencilBits
== 0);
1449 /* now add any/all software-based renderbuffers we may need */
1450 _swrast_add_soft_renderbuffers(fb
,
1451 false, /* never sw color */
1452 false, /* never sw depth */
1453 false, /* never sw stencil */
1454 mesaVis
->accumRedBits
> 0,
1455 false, /* never sw alpha */
1456 false /* never sw aux */ );
1457 driDrawPriv
->driverPrivate
= fb
;
1463 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1465 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1467 _mesa_reference_framebuffer(&fb
, NULL
);
1471 intel_detect_sseu(struct intel_screen
*screen
)
1473 assert(screen
->devinfo
.gen
>= 8);
1476 screen
->subslice_total
= -1;
1477 screen
->eu_total
= -1;
1479 ret
= intel_get_param(screen
, I915_PARAM_SUBSLICE_TOTAL
,
1480 &screen
->subslice_total
);
1481 if (ret
< 0 && ret
!= -EINVAL
)
1484 ret
= intel_get_param(screen
,
1485 I915_PARAM_EU_TOTAL
, &screen
->eu_total
);
1486 if (ret
< 0 && ret
!= -EINVAL
)
1489 /* Without this information, we cannot get the right Braswell brandstrings,
1490 * and we have to use conservative numbers for GPGPU on many platforms, but
1491 * otherwise, things will just work.
1493 if (screen
->subslice_total
< 1 || screen
->eu_total
< 1)
1495 "Kernel 4.1 required to properly query GPU properties.\n");
1500 screen
->subslice_total
= -1;
1501 screen
->eu_total
= -1;
1502 _mesa_warning(NULL
, "Failed to query GPU properties (%s).\n", strerror(-ret
));
1506 intel_init_bufmgr(struct intel_screen
*screen
)
1508 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1510 if (getenv("INTEL_NO_HW") != NULL
)
1511 screen
->no_hw
= true;
1513 screen
->bufmgr
= brw_bufmgr_init(&screen
->devinfo
, dri_screen
->fd
, BATCH_SZ
);
1514 if (screen
->bufmgr
== NULL
) {
1515 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1516 __func__
, __LINE__
);
1520 if (!intel_get_boolean(screen
, I915_PARAM_HAS_WAIT_TIMEOUT
)) {
1521 fprintf(stderr
, "[%s: %u] Kernel 3.6 required.\n", __func__
, __LINE__
);
1529 intel_detect_swizzling(struct intel_screen
*screen
)
1531 struct brw_bo
*buffer
;
1533 uint32_t aligned_pitch
;
1534 uint32_t tiling
= I915_TILING_X
;
1535 uint32_t swizzle_mode
= 0;
1537 buffer
= brw_bo_alloc_tiled_2d(screen
->bufmgr
, "swizzle test",
1538 64, 64, 4, tiling
, &aligned_pitch
, flags
);
1542 brw_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1543 brw_bo_unreference(buffer
);
1545 if (swizzle_mode
== I915_BIT_6_SWIZZLE_NONE
)
1552 intel_detect_timestamp(struct intel_screen
*screen
)
1554 uint64_t dummy
= 0, last
= 0;
1555 int upper
, lower
, loops
;
1557 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1558 * TIMESTAMP register being shifted and the low 32bits always zero.
1560 * More recent kernels offer an interface to read the full 36bits
1563 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &dummy
) == 0)
1566 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1567 * upper 32bits for a rapidly changing timestamp.
1569 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &last
))
1573 for (loops
= 0; loops
< 10; loops
++) {
1574 /* The TIMESTAMP should change every 80ns, so several round trips
1575 * through the kernel should be enough to advance it.
1577 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &dummy
))
1580 upper
+= (dummy
>> 32) != (last
>> 32);
1581 if (upper
> 1) /* beware 32bit counter overflow */
1582 return 2; /* upper dword holds the low 32bits of the timestamp */
1584 lower
+= (dummy
& 0xffffffff) != (last
& 0xffffffff);
1586 return 1; /* timestamp is unshifted */
1591 /* No advancement? No timestamp! */
1596 * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
1598 * Some combinations of hardware and kernel versions allow this feature,
1599 * while others don't. Instead of trying to enumerate every case, just
1600 * try and write a register and see if works.
1603 intel_detect_pipelined_register(struct intel_screen
*screen
,
1604 int reg
, uint32_t expected_value
, bool reset
)
1609 struct brw_bo
*results
, *bo
;
1611 uint32_t offset
= 0;
1613 bool success
= false;
1615 /* Create a zero'ed temporary buffer for reading our results */
1616 results
= brw_bo_alloc(screen
->bufmgr
, "registers", 4096, 0);
1617 if (results
== NULL
)
1620 bo
= brw_bo_alloc(screen
->bufmgr
, "batchbuffer", 4096, 0);
1624 map
= brw_bo_map(NULL
, bo
, MAP_WRITE
);
1630 /* Write the register. */
1631 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1633 *batch
++ = expected_value
;
1635 /* Save the register's value back to the buffer. */
1636 *batch
++ = MI_STORE_REGISTER_MEM
| (3 - 2);
1638 struct drm_i915_gem_relocation_entry reloc
= {
1639 .offset
= (char *) batch
- (char *) map
,
1640 .delta
= offset
* sizeof(uint32_t),
1641 .target_handle
= results
->gem_handle
,
1642 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
1643 .write_domain
= I915_GEM_DOMAIN_INSTRUCTION
,
1645 *batch
++ = reloc
.presumed_offset
+ reloc
.delta
;
1647 /* And afterwards clear the register */
1649 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1654 *batch
++ = MI_BATCH_BUFFER_END
;
1656 struct drm_i915_gem_exec_object2 exec_objects
[2] = {
1658 .handle
= results
->gem_handle
,
1661 .handle
= bo
->gem_handle
,
1662 .relocation_count
= 1,
1663 .relocs_ptr
= (uintptr_t) &reloc
,
1667 struct drm_i915_gem_execbuffer2 execbuf
= {
1668 .buffers_ptr
= (uintptr_t) exec_objects
,
1670 .batch_len
= ALIGN((char *) batch
- (char *) map
, 8),
1671 .flags
= I915_EXEC_RENDER
,
1674 /* Don't bother with error checking - if the execbuf fails, the
1675 * value won't be written and we'll just report that there's no access.
1677 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1678 drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GEM_EXECBUFFER2
, &execbuf
);
1680 /* Check whether the value got written. */
1681 void *results_map
= brw_bo_map(NULL
, results
, MAP_READ
);
1683 success
= *((uint32_t *)results_map
+ offset
) == expected_value
;
1684 brw_bo_unmap(results
);
1688 brw_bo_unreference(bo
);
1690 brw_bo_unreference(results
);
1696 intel_detect_pipelined_so(struct intel_screen
*screen
)
1698 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1700 /* Supposedly, Broadwell just works. */
1701 if (devinfo
->gen
>= 8)
1704 if (devinfo
->gen
<= 6)
1707 /* See the big explanation about command parser versions below */
1708 if (screen
->cmd_parser_version
>= (devinfo
->is_haswell
? 7 : 2))
1711 /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
1712 * statistics registers), and we already reset it to zero before using it.
1714 return intel_detect_pipelined_register(screen
,
1715 GEN7_SO_WRITE_OFFSET(0),
1721 * Return array of MSAA modes supported by the hardware. The array is
1722 * zero-terminated and sorted in decreasing order.
1725 intel_supported_msaa_modes(const struct intel_screen
*screen
)
1727 static const int gen9_modes
[] = {16, 8, 4, 2, 0, -1};
1728 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
1729 static const int gen7_modes
[] = {8, 4, 0, -1};
1730 static const int gen6_modes
[] = {4, 0, -1};
1731 static const int gen4_modes
[] = {0, -1};
1733 if (screen
->devinfo
.gen
>= 9) {
1735 } else if (screen
->devinfo
.gen
>= 8) {
1737 } else if (screen
->devinfo
.gen
>= 7) {
1739 } else if (screen
->devinfo
.gen
== 6) {
1746 static __DRIconfig
**
1747 intel_screen_make_configs(__DRIscreen
*dri_screen
)
1749 static const mesa_format formats
[] = {
1750 MESA_FORMAT_B5G6R5_UNORM
,
1751 MESA_FORMAT_B8G8R8A8_UNORM
,
1752 MESA_FORMAT_B8G8R8X8_UNORM
,
1754 /* The 32-bit RGBA format must not precede the 32-bit BGRA format.
1755 * Likewise for RGBX and BGRX. Otherwise, the GLX client and the GLX
1756 * server may disagree on which format the GLXFBConfig represents,
1757 * resulting in swapped color channels.
1759 * The problem, as of 2017-05-30:
1760 * When matching a GLXFBConfig to a __DRIconfig, GLX ignores the channel
1761 * order and chooses the first __DRIconfig with the expected channel
1762 * sizes. Specifically, GLX compares the GLXFBConfig's and __DRIconfig's
1763 * __DRI_ATTRIB_{CHANNEL}_SIZE but ignores __DRI_ATTRIB_{CHANNEL}_MASK.
1765 * EGL does not suffer from this problem. It correctly compares the
1766 * channel masks when matching EGLConfig to __DRIconfig.
1769 /* Required by Android, for HAL_PIXEL_FORMAT_RGBA_8888. */
1770 MESA_FORMAT_R8G8B8A8_UNORM
,
1772 /* Required by Android, for HAL_PIXEL_FORMAT_RGBX_8888. */
1773 MESA_FORMAT_R8G8B8X8_UNORM
,
1776 /* GLX_SWAP_COPY_OML is not supported due to page flipping. */
1777 static const GLenum back_buffer_modes
[] = {
1778 GLX_SWAP_UNDEFINED_OML
, GLX_NONE
,
1781 static const uint8_t singlesample_samples
[1] = {0};
1782 static const uint8_t multisample_samples
[2] = {4, 8};
1784 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1785 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1786 uint8_t depth_bits
[4], stencil_bits
[4];
1787 __DRIconfig
**configs
= NULL
;
1789 /* Generate singlesample configs without accumulation buffer. */
1790 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1791 __DRIconfig
**new_configs
;
1792 int num_depth_stencil_bits
= 2;
1794 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
1795 * buffer that has a different number of bits per pixel than the color
1796 * buffer, gen >= 6 supports this.
1799 stencil_bits
[0] = 0;
1801 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1803 stencil_bits
[1] = 0;
1804 if (devinfo
->gen
>= 6) {
1806 stencil_bits
[2] = 8;
1807 num_depth_stencil_bits
= 3;
1811 stencil_bits
[1] = 8;
1814 new_configs
= driCreateConfigs(formats
[i
],
1817 num_depth_stencil_bits
,
1818 back_buffer_modes
, 2,
1819 singlesample_samples
, 1,
1821 configs
= driConcatConfigs(configs
, new_configs
);
1824 /* Generate the minimum possible set of configs that include an
1825 * accumulation buffer.
1827 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1828 __DRIconfig
**new_configs
;
1830 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1832 stencil_bits
[0] = 0;
1835 stencil_bits
[0] = 8;
1838 new_configs
= driCreateConfigs(formats
[i
],
1839 depth_bits
, stencil_bits
, 1,
1840 back_buffer_modes
, 1,
1841 singlesample_samples
, 1,
1843 configs
= driConcatConfigs(configs
, new_configs
);
1846 /* Generate multisample configs.
1848 * This loop breaks early, and hence is a no-op, on gen < 6.
1850 * Multisample configs must follow the singlesample configs in order to
1851 * work around an X server bug present in 1.12. The X server chooses to
1852 * associate the first listed RGBA888-Z24S8 config, regardless of its
1853 * sample count, with the 32-bit depth visual used for compositing.
1855 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
1856 * supported. Singlebuffer configs are not supported because no one wants
1859 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1860 if (devinfo
->gen
< 6)
1863 __DRIconfig
**new_configs
;
1864 const int num_depth_stencil_bits
= 2;
1865 int num_msaa_modes
= 0;
1868 stencil_bits
[0] = 0;
1870 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1872 stencil_bits
[1] = 0;
1875 stencil_bits
[1] = 8;
1878 if (devinfo
->gen
>= 7)
1880 else if (devinfo
->gen
== 6)
1883 new_configs
= driCreateConfigs(formats
[i
],
1886 num_depth_stencil_bits
,
1887 back_buffer_modes
, 1,
1888 multisample_samples
,
1891 configs
= driConcatConfigs(configs
, new_configs
);
1894 if (configs
== NULL
) {
1895 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
1904 set_max_gl_versions(struct intel_screen
*screen
)
1906 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1907 const bool has_astc
= screen
->devinfo
.gen
>= 9;
1909 switch (screen
->devinfo
.gen
) {
1913 dri_screen
->max_gl_core_version
= 45;
1914 dri_screen
->max_gl_compat_version
= 30;
1915 dri_screen
->max_gl_es1_version
= 11;
1916 dri_screen
->max_gl_es2_version
= has_astc
? 32 : 31;
1919 dri_screen
->max_gl_core_version
= 33;
1920 if (can_do_pipelined_register_writes(screen
)) {
1921 dri_screen
->max_gl_core_version
= 42;
1922 if (screen
->devinfo
.is_haswell
&& can_do_compute_dispatch(screen
))
1923 dri_screen
->max_gl_core_version
= 43;
1924 if (screen
->devinfo
.is_haswell
&& can_do_mi_math_and_lrr(screen
))
1925 dri_screen
->max_gl_core_version
= 45;
1927 dri_screen
->max_gl_compat_version
= 30;
1928 dri_screen
->max_gl_es1_version
= 11;
1929 dri_screen
->max_gl_es2_version
= screen
->devinfo
.is_haswell
? 31 : 30;
1932 dri_screen
->max_gl_core_version
= 33;
1933 dri_screen
->max_gl_compat_version
= 30;
1934 dri_screen
->max_gl_es1_version
= 11;
1935 dri_screen
->max_gl_es2_version
= 30;
1939 dri_screen
->max_gl_core_version
= 0;
1940 dri_screen
->max_gl_compat_version
= 21;
1941 dri_screen
->max_gl_es1_version
= 11;
1942 dri_screen
->max_gl_es2_version
= 20;
1945 unreachable("unrecognized intel_screen::gen");
1950 * Return the revision (generally the revid field of the PCI header) of the
1953 * XXX: This function is useful to keep around even if it is not currently in
1954 * use. It is necessary for new platforms and revision specific workarounds or
1955 * features. Please don't remove it so that we know it at least continues to
1958 static __attribute__((__unused__
)) int
1959 brw_get_revision(int fd
)
1961 struct drm_i915_getparam gp
;
1965 memset(&gp
, 0, sizeof(gp
));
1966 gp
.param
= I915_PARAM_REVISION
;
1967 gp
.value
= &revision
;
1969 ret
= drmCommandWriteRead(fd
, DRM_I915_GETPARAM
, &gp
, sizeof(gp
));
1977 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
1979 struct brw_context
*brw
= (struct brw_context
*)data
;
1982 va_start(args
, fmt
);
1984 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
1985 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
1986 MESA_DEBUG_TYPE_OTHER
,
1987 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
1992 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
1994 struct brw_context
*brw
= (struct brw_context
*)data
;
1997 va_start(args
, fmt
);
1999 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
2001 va_copy(args_copy
, args
);
2002 vfprintf(stderr
, fmt
, args_copy
);
2006 if (brw
->perf_debug
) {
2008 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
2009 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
2010 MESA_DEBUG_TYPE_PERFORMANCE
,
2011 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
2017 parse_devid_override(const char *devid_override
)
2019 static const struct {
2036 for (unsigned i
= 0; i
< ARRAY_SIZE(name_map
); i
++) {
2037 if (!strcmp(name_map
[i
].name
, devid_override
))
2038 return name_map
[i
].pci_id
;
2041 return strtol(devid_override
, NULL
, 0);
2045 * Get the PCI ID for the device. This can be overridden by setting the
2046 * INTEL_DEVID_OVERRIDE environment variable to the desired ID.
2048 * Returns -1 on ioctl failure.
2051 get_pci_device_id(struct intel_screen
*screen
)
2053 if (geteuid() == getuid()) {
2054 char *devid_override
= getenv("INTEL_DEVID_OVERRIDE");
2055 if (devid_override
) {
2056 screen
->no_hw
= true;
2057 return parse_devid_override(devid_override
);
2061 return intel_get_integer(screen
, I915_PARAM_CHIPSET_ID
);
2065 * This is the driver specific part of the createNewScreen entry point.
2066 * Called when using DRI2.
2068 * \return the struct gl_config supported by this driver
2071 __DRIconfig
**intelInitScreen2(__DRIscreen
*dri_screen
)
2073 struct intel_screen
*screen
;
2075 if (dri_screen
->image
.loader
) {
2076 } else if (dri_screen
->dri2
.loader
->base
.version
<= 2 ||
2077 dri_screen
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
2079 "\nERROR! DRI2 loader with getBuffersWithFormat() "
2080 "support required\n");
2084 /* Allocate the private area */
2085 screen
= rzalloc(NULL
, struct intel_screen
);
2087 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
2090 /* parse information in __driConfigOptions */
2091 driParseOptionInfo(&screen
->optionCache
, brw_config_options
.xml
);
2093 screen
->driScrnPriv
= dri_screen
;
2094 dri_screen
->driverPrivate
= (void *) screen
;
2096 screen
->deviceID
= get_pci_device_id(screen
);
2098 if (!gen_get_device_info(screen
->deviceID
, &screen
->devinfo
))
2101 if (!intel_init_bufmgr(screen
))
2104 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2106 brw_process_intel_debug_variable();
2108 if ((INTEL_DEBUG
& DEBUG_SHADER_TIME
) && devinfo
->gen
< 7) {
2110 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
2111 INTEL_DEBUG
&= ~DEBUG_SHADER_TIME
;
2114 if (intel_get_integer(screen
, I915_PARAM_MMAP_GTT_VERSION
) >= 1) {
2115 /* Theorectically unlimited! At least for individual objects...
2117 * Currently the entire (global) address space for all GTT maps is
2118 * limited to 64bits. That is all objects on the system that are
2119 * setup for GTT mmapping must fit within 64bits. An attempt to use
2120 * one that exceeds the limit with fail in brw_bo_map_gtt().
2122 * Long before we hit that limit, we will be practically limited by
2123 * that any single object must fit in physical memory (RAM). The upper
2124 * limit on the CPU's address space is currently 48bits (Skylake), of
2125 * which only 39bits can be physical memory. (The GPU itself also has
2126 * a 48bit addressable virtual space.) We can fit over 32 million
2127 * objects of the current maximum allocable size before running out
2130 screen
->max_gtt_map_object_size
= UINT64_MAX
;
2132 /* Estimate the size of the mappable aperture into the GTT. There's an
2133 * ioctl to get the whole GTT size, but not one to get the mappable subset.
2134 * It turns out it's basically always 256MB, though some ancient hardware
2137 uint32_t gtt_size
= 256 * 1024 * 1024;
2139 /* We don't want to map two objects such that a memcpy between them would
2140 * just fault one mapping in and then the other over and over forever. So
2141 * we would need to divide the GTT size by 2. Additionally, some GTT is
2142 * taken up by things like the framebuffer and the ringbuffer and such, so
2143 * be more conservative.
2145 screen
->max_gtt_map_object_size
= gtt_size
/ 4;
2148 screen
->aperture_threshold
= get_aperture_size(dri_screen
->fd
) * 3 / 4;
2150 screen
->hw_has_swizzling
= intel_detect_swizzling(screen
);
2151 screen
->hw_has_timestamp
= intel_detect_timestamp(screen
);
2153 isl_device_init(&screen
->isl_dev
, &screen
->devinfo
,
2154 screen
->hw_has_swizzling
);
2156 /* GENs prior to 8 do not support EU/Subslice info */
2157 if (devinfo
->gen
>= 8) {
2158 intel_detect_sseu(screen
);
2159 } else if (devinfo
->gen
== 7) {
2160 screen
->subslice_total
= 1 << (devinfo
->gt
- 1);
2163 /* Gen7-7.5 kernel requirements / command parser saga:
2166 * Haswell and Baytrail cannot use any privileged batchbuffer features.
2168 * Ivybridge has aliasing PPGTT on by default, which accidentally marks
2169 * all batches secure, allowing them to use any feature with no checking.
2170 * This is effectively equivalent to a command parser version of
2171 * \infinity - everything is possible.
2173 * The command parser does not exist, and querying the version will
2177 * The kernel enables the command parser by default, for systems with
2178 * aliasing PPGTT enabled (Ivybridge and Haswell). However, the
2179 * hardware checker is still enabled, so Haswell and Baytrail cannot
2182 * Ivybridge goes from "everything is possible" to "only what the
2183 * command parser allows" (if the user boots with i915.cmd_parser=0,
2184 * then everything is possible again). We can only safely use features
2185 * allowed by the supported command parser version.
2187 * Annoyingly, I915_PARAM_CMD_PARSER_VERSION reports the static version
2188 * implemented by the kernel, even if it's turned off. So, checking
2189 * for version > 0 does not mean that you can write registers. We have
2190 * to try it and see. The version does, however, indicate the age of
2193 * Instead of matching the hardware checker's behavior of converting
2194 * privileged commands to MI_NOOP, it makes execbuf2 start returning
2195 * -EINVAL, making it dangerous to try and use privileged features.
2197 * Effective command parser versions:
2198 * - Haswell: 0 (reporting 1, writes don't work)
2199 * - Baytrail: 0 (reporting 1, writes don't work)
2200 * - Ivybridge: 1 (enabled) or infinite (disabled)
2203 * Baytrail aliasing PPGTT is enabled, making it like Ivybridge:
2204 * effectively version 1 (enabled) or infinite (disabled).
2206 * - v3.19: f1f55cc0556031c8ee3fe99dae7251e78b9b653b
2207 * Command parser v2 supports predicate writes.
2209 * - Haswell: 0 (reporting 1, writes don't work)
2210 * - Baytrail: 2 (enabled) or infinite (disabled)
2211 * - Ivybridge: 2 (enabled) or infinite (disabled)
2213 * So version >= 2 is enough to know that Ivybridge and Baytrail
2214 * will work. Haswell still can't do anything.
2216 * - v4.0: Version 3 happened. Largely not relevant.
2218 * - v4.1: 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b
2219 * L3 config registers are properly saved and restored as part
2220 * of the hardware context. We can approximately detect this point
2221 * in time by checking if I915_PARAM_REVISION is recognized - it
2222 * landed in a later commit, but in the same release cycle.
2224 * - v4.2: 245054a1fe33c06ad233e0d58a27ec7b64db9284
2225 * Command parser finally gains secure batch promotion. On Haswell,
2226 * the hardware checker gets disabled, which finally allows it to do
2227 * privileged commands.
2229 * I915_PARAM_CMD_PARSER_VERSION reports 3. Effective versions:
2230 * - Haswell: 3 (enabled) or 0 (disabled)
2231 * - Baytrail: 3 (enabled) or infinite (disabled)
2232 * - Ivybridge: 3 (enabled) or infinite (disabled)
2234 * Unfortunately, detecting this point in time is tricky, because
2235 * no version bump happened when this important change occurred.
2236 * On Haswell, if we can write any register, then the kernel is at
2237 * least this new, and we can start trusting the version number.
2239 * - v4.4: 2bbe6bbb0dc94fd4ce287bdac9e1bd184e23057b and
2240 * Command parser reaches version 4, allowing access to Haswell
2241 * atomic scratch and chicken3 registers. If version >= 4, we know
2242 * the kernel is new enough to support privileged features on all
2243 * hardware. However, the user might have disabled it...and the
2244 * kernel will still report version 4. So we still have to guess
2247 * - v4.4: 7b9748cb513a6bef4af87b79f0da3ff7e8b56cd8
2248 * Command parser v5 whitelists indirect compute shader dispatch
2249 * registers, needed for OpenGL 4.3 and later.
2252 * Command parser v7 lets us use MI_MATH on Haswell.
2254 * Additionally, the kernel begins reporting version 0 when
2255 * the command parser is disabled, allowing us to skip the
2256 * guess-and-check step on Haswell. Unfortunately, this also
2257 * means that we can no longer use it as an indicator of the
2258 * age of the kernel.
2260 if (intel_get_param(screen
, I915_PARAM_CMD_PARSER_VERSION
,
2261 &screen
->cmd_parser_version
) < 0) {
2262 /* Command parser does not exist - getparam is unrecognized */
2263 screen
->cmd_parser_version
= 0;
2266 /* Kernel 4.13 retuired for exec object capture */
2267 #ifndef I915_PARAM_HAS_EXEC_CAPTURE
2268 #define I915_PARAM_HAS_EXEC_CAPTURE 45
2270 if (intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_CAPTURE
)) {
2271 screen
->kernel_features
|= KERNEL_ALLOWS_EXEC_CAPTURE
;
2274 if (!intel_detect_pipelined_so(screen
)) {
2275 /* We can't do anything, so the effective version is 0. */
2276 screen
->cmd_parser_version
= 0;
2278 screen
->kernel_features
|= KERNEL_ALLOWS_SOL_OFFSET_WRITES
;
2281 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 2)
2282 screen
->kernel_features
|= KERNEL_ALLOWS_PREDICATE_WRITES
;
2284 /* Haswell requires command parser version 4 in order to have L3
2285 * atomic scratch1 and chicken3 bits
2287 if (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 4) {
2288 screen
->kernel_features
|=
2289 KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3
;
2292 /* Haswell requires command parser version 6 in order to write to the
2293 * MI_MATH GPR registers, and version 7 in order to use
2294 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
2296 if (devinfo
->gen
>= 8 ||
2297 (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 7)) {
2298 screen
->kernel_features
|= KERNEL_ALLOWS_MI_MATH_AND_LRR
;
2301 /* Gen7 needs at least command parser version 5 to support compute */
2302 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 5)
2303 screen
->kernel_features
|= KERNEL_ALLOWS_COMPUTE_DISPATCH
;
2305 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
2307 screen
->winsys_msaa_samples_override
=
2308 intel_quantize_num_samples(screen
, atoi(force_msaa
));
2309 printf("Forcing winsys sample count to %d\n",
2310 screen
->winsys_msaa_samples_override
);
2312 screen
->winsys_msaa_samples_override
= -1;
2315 set_max_gl_versions(screen
);
2317 /* Notification of GPU resets requires hardware contexts and a kernel new
2318 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
2319 * supported, calling it with a context of 0 will either generate EPERM or
2320 * no error. If the ioctl is not supported, it always generate EINVAL.
2321 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
2322 * extension to the loader.
2324 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
2326 if (devinfo
->gen
>= 6) {
2327 struct drm_i915_reset_stats stats
;
2328 memset(&stats
, 0, sizeof(stats
));
2330 const int ret
= drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
2332 screen
->has_context_reset_notification
=
2333 (ret
!= -1 || errno
!= EINVAL
);
2336 dri_screen
->extensions
= !screen
->has_context_reset_notification
2337 ? screenExtensions
: intelRobustScreenExtensions
;
2339 screen
->compiler
= brw_compiler_create(screen
, devinfo
);
2340 screen
->compiler
->shader_debug_log
= shader_debug_log_mesa
;
2341 screen
->compiler
->shader_perf_log
= shader_perf_log_mesa
;
2342 screen
->compiler
->constant_buffer_0_is_relative
= devinfo
->gen
< 8;
2343 screen
->program_id
= 1;
2345 screen
->has_exec_fence
=
2346 intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_FENCE
);
2348 intel_screen_init_surface_formats(screen
);
2350 return (const __DRIconfig
**) intel_screen_make_configs(dri_screen
);
2353 struct intel_buffer
{
2358 static __DRIbuffer
*
2359 intelAllocateBuffer(__DRIscreen
*dri_screen
,
2360 unsigned attachment
, unsigned format
,
2361 int width
, int height
)
2363 struct intel_buffer
*intelBuffer
;
2364 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2366 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
2367 attachment
== __DRI_BUFFER_BACK_LEFT
);
2369 intelBuffer
= calloc(1, sizeof *intelBuffer
);
2370 if (intelBuffer
== NULL
)
2373 /* The front and back buffers are color buffers, which are X tiled. GEN9+
2374 * supports Y tiled and compressed buffers, but there is no way to plumb that
2375 * through to here. */
2377 int cpp
= format
/ 8;
2378 intelBuffer
->bo
= brw_bo_alloc_tiled_2d(screen
->bufmgr
,
2379 "intelAllocateBuffer",
2383 I915_TILING_X
, &pitch
,
2384 BO_ALLOC_FOR_RENDER
);
2386 if (intelBuffer
->bo
== NULL
) {
2391 brw_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
2393 intelBuffer
->base
.attachment
= attachment
;
2394 intelBuffer
->base
.cpp
= cpp
;
2395 intelBuffer
->base
.pitch
= pitch
;
2397 return &intelBuffer
->base
;
2401 intelReleaseBuffer(__DRIscreen
*dri_screen
, __DRIbuffer
*buffer
)
2403 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
2405 brw_bo_unreference(intelBuffer
->bo
);
2409 static const struct __DriverAPIRec brw_driver_api
= {
2410 .InitScreen
= intelInitScreen2
,
2411 .DestroyScreen
= intelDestroyScreen
,
2412 .CreateContext
= brwCreateContext
,
2413 .DestroyContext
= intelDestroyContext
,
2414 .CreateBuffer
= intelCreateBuffer
,
2415 .DestroyBuffer
= intelDestroyBuffer
,
2416 .MakeCurrent
= intelMakeCurrent
,
2417 .UnbindContext
= intelUnbindContext
,
2418 .AllocateBuffer
= intelAllocateBuffer
,
2419 .ReleaseBuffer
= intelReleaseBuffer
2422 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
2423 .base
= { __DRI_DRIVER_VTABLE
, 1 },
2424 .vtable
= &brw_driver_api
,
2427 static const __DRIextension
*brw_driver_extensions
[] = {
2428 &driCoreExtension
.base
,
2429 &driImageDriverExtension
.base
,
2430 &driDRI2Extension
.base
,
2432 &brw_config_options
.base
,
2436 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
2438 globalDriverAPI
= &brw_driver_api
;
2440 return brw_driver_extensions
;