2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "main/context.h"
30 #include "main/framebuffer.h"
31 #include "main/renderbuffer.h"
32 #include "main/texobj.h"
33 #include "main/hash.h"
34 #include "main/fbobject.h"
35 #include "main/version.h"
36 #include "swrast/s_renderbuffer.h"
37 #include "util/ralloc.h"
38 #include "brw_shader.h"
39 #include "compiler/nir/nir.h"
44 static const __DRIconfigOptionsExtension brw_config_options
= {
45 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
48 DRI_CONF_SECTION_PERFORMANCE
49 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_ALWAYS_SYNC
)
50 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
51 * DRI_CONF_BO_REUSE_ALL
53 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
54 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
55 DRI_CONF_ENUM(0, "Disable buffer object reuse")
56 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
60 DRI_CONF_OPT_BEGIN_B(hiz
, "true")
61 DRI_CONF_DESC(en
, "Enable Hierarchical Z on gen6+")
65 DRI_CONF_SECTION_QUALITY
66 DRI_CONF_FORCE_S3TC_ENABLE("false")
68 DRI_CONF_PRECISE_TRIG("false")
70 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
71 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
72 "given integer. If negative, then do not clamp.")
76 DRI_CONF_SECTION_DEBUG
77 DRI_CONF_NO_RAST("false")
78 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
79 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
80 DRI_CONF_DISABLE_THROTTLING("false")
81 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
82 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
83 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
84 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
85 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
87 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
88 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
94 #include "intel_batchbuffer.h"
95 #include "intel_buffers.h"
96 #include "intel_bufmgr.h"
97 #include "intel_fbo.h"
98 #include "intel_mipmap_tree.h"
99 #include "intel_screen.h"
100 #include "intel_tex.h"
101 #include "intel_image.h"
103 #include "brw_context.h"
105 #include "i915_drm.h"
108 * For debugging purposes, this returns a time in seconds.
115 clock_gettime(CLOCK_MONOTONIC
, &tp
);
117 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
121 aub_dump_bmp(struct gl_context
*ctx
)
123 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
125 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
126 struct intel_renderbuffer
*irb
=
127 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
129 if (irb
&& irb
->mt
) {
130 enum aub_dump_bmp_format format
;
132 switch (irb
->Base
.Base
.Format
) {
133 case MESA_FORMAT_B8G8R8A8_UNORM
:
134 case MESA_FORMAT_B8G8R8X8_UNORM
:
135 format
= AUB_DUMP_BMP_FORMAT_ARGB_8888
;
141 drm_intel_gem_bo_aub_dump_bmp(irb
->mt
->bo
,
144 irb
->Base
.Base
.Width
,
145 irb
->Base
.Base
.Height
,
153 static const __DRItexBufferExtension intelTexBufferExtension
= {
154 .base
= { __DRI_TEX_BUFFER
, 3 },
156 .setTexBuffer
= intelSetTexBuffer
,
157 .setTexBuffer2
= intelSetTexBuffer2
,
158 .releaseTexBuffer
= NULL
,
162 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
163 __DRIdrawable
*dPriv
,
165 enum __DRI2throttleReason reason
)
167 struct brw_context
*brw
= cPriv
->driverPrivate
;
172 struct gl_context
*ctx
= &brw
->ctx
;
174 FLUSH_VERTICES(ctx
, 0);
176 if (flags
& __DRI2_FLUSH_DRAWABLE
)
177 intel_resolve_for_dri2_flush(brw
, dPriv
);
179 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
)
180 brw
->need_swap_throttle
= true;
181 if (reason
== __DRI2_THROTTLE_FLUSHFRONT
)
182 brw
->need_flush_throttle
= true;
184 intel_batchbuffer_flush(brw
);
186 if (INTEL_DEBUG
& DEBUG_AUB
) {
192 * Provides compatibility with loaders that only support the older (version
193 * 1-3) flush interface.
195 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
198 intel_dri2_flush(__DRIdrawable
*drawable
)
200 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
201 __DRI2_FLUSH_DRAWABLE
,
202 __DRI2_THROTTLE_SWAPBUFFER
);
205 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
206 .base
= { __DRI2_FLUSH
, 4 },
208 .flush
= intel_dri2_flush
,
209 .invalidate
= dri2InvalidateDrawable
,
210 .flush_with_flags
= intel_dri2_flush_with_flags
,
213 static struct intel_image_format intel_image_formats
[] = {
214 { __DRI_IMAGE_FOURCC_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
215 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
217 { __DRI_IMAGE_FOURCC_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
218 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
220 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
221 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
223 { __DRI_IMAGE_FOURCC_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
224 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
226 { __DRI_IMAGE_FOURCC_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
227 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
229 { __DRI_IMAGE_FOURCC_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
230 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
232 { __DRI_IMAGE_FOURCC_R8
, __DRI_IMAGE_COMPONENTS_R
, 1,
233 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 }, } },
235 { __DRI_IMAGE_FOURCC_GR88
, __DRI_IMAGE_COMPONENTS_RG
, 1,
236 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 }, } },
238 { __DRI_IMAGE_FOURCC_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
239 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
240 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
241 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
243 { __DRI_IMAGE_FOURCC_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
244 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
245 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
246 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
248 { __DRI_IMAGE_FOURCC_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
249 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
250 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
251 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
253 { __DRI_IMAGE_FOURCC_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
254 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
255 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
256 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
258 { __DRI_IMAGE_FOURCC_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
259 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
260 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
261 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
263 { __DRI_IMAGE_FOURCC_YVU410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
264 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
265 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
266 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
268 { __DRI_IMAGE_FOURCC_YVU411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
269 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
270 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
271 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
273 { __DRI_IMAGE_FOURCC_YVU420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
274 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
275 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
276 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
278 { __DRI_IMAGE_FOURCC_YVU422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
279 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
280 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
281 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
283 { __DRI_IMAGE_FOURCC_YVU444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
284 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
285 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
286 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
288 { __DRI_IMAGE_FOURCC_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
289 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
290 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
292 { __DRI_IMAGE_FOURCC_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
293 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
294 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
296 /* For YUYV buffers, we set up two overlapping DRI images and treat
297 * them as planar buffers in the compositors. Plane 0 is GR88 and
298 * samples YU or YV pairs and places Y into the R component, while
299 * plane 1 is ARGB and samples YUYV clusters and places pairs and
300 * places U into the G component and V into A. This lets the
301 * texture sampler interpolate the Y components correctly when
302 * sampling from plane 0, and interpolate U and V correctly when
303 * sampling from plane 1. */
304 { __DRI_IMAGE_FOURCC_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
305 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
306 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } }
310 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
312 uint32_t tiling
, swizzle
;
313 drm_intel_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
315 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
316 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
317 func
, image
->offset
);
321 static struct intel_image_format
*
322 intel_image_format_lookup(int fourcc
)
324 struct intel_image_format
*f
= NULL
;
326 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
327 if (intel_image_formats
[i
].fourcc
== fourcc
) {
328 f
= &intel_image_formats
[i
];
336 static boolean
intel_lookup_fourcc(int dri_format
, int *fourcc
)
338 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
339 if (intel_image_formats
[i
].planes
[0].dri_format
== dri_format
) {
340 *fourcc
= intel_image_formats
[i
].fourcc
;
348 intel_allocate_image(int dri_format
, void *loaderPrivate
)
352 image
= calloc(1, sizeof *image
);
356 image
->dri_format
= dri_format
;
359 image
->format
= driImageFormatToGLFormat(dri_format
);
360 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
361 image
->format
== MESA_FORMAT_NONE
) {
366 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
367 image
->data
= loaderPrivate
;
373 * Sets up a DRIImage structure to point to a slice out of a miptree.
376 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
377 struct intel_mipmap_tree
*mt
, GLuint level
,
380 intel_miptree_make_shareable(brw
, mt
);
382 intel_miptree_check_level_layer(mt
, level
, zoffset
);
384 image
->width
= minify(mt
->physical_width0
, level
- mt
->first_level
);
385 image
->height
= minify(mt
->physical_height0
, level
- mt
->first_level
);
386 image
->pitch
= mt
->pitch
;
388 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
392 drm_intel_bo_unreference(image
->bo
);
394 drm_intel_bo_reference(mt
->bo
);
398 intel_create_image_from_name(__DRIscreen
*screen
,
399 int width
, int height
, int format
,
400 int name
, int pitch
, void *loaderPrivate
)
402 struct intel_screen
*intelScreen
= screen
->driverPrivate
;
406 image
= intel_allocate_image(format
, loaderPrivate
);
410 if (image
->format
== MESA_FORMAT_NONE
)
413 cpp
= _mesa_get_format_bytes(image
->format
);
415 image
->width
= width
;
416 image
->height
= height
;
417 image
->pitch
= pitch
* cpp
;
418 image
->bo
= drm_intel_bo_gem_create_from_name(intelScreen
->bufmgr
, "image",
429 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
430 int renderbuffer
, void *loaderPrivate
)
433 struct brw_context
*brw
= context
->driverPrivate
;
434 struct gl_context
*ctx
= &brw
->ctx
;
435 struct gl_renderbuffer
*rb
;
436 struct intel_renderbuffer
*irb
;
438 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
440 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
444 irb
= intel_renderbuffer(rb
);
445 intel_miptree_make_shareable(brw
, irb
->mt
);
446 image
= calloc(1, sizeof *image
);
450 image
->internal_format
= rb
->InternalFormat
;
451 image
->format
= rb
->Format
;
453 image
->data
= loaderPrivate
;
454 drm_intel_bo_unreference(image
->bo
);
455 image
->bo
= irb
->mt
->bo
;
456 drm_intel_bo_reference(irb
->mt
->bo
);
457 image
->width
= rb
->Width
;
458 image
->height
= rb
->Height
;
459 image
->pitch
= irb
->mt
->pitch
;
460 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
461 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
463 rb
->NeedsFinishRenderTexture
= true;
468 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
469 unsigned texture
, int zoffset
,
475 struct brw_context
*brw
= context
->driverPrivate
;
476 struct gl_texture_object
*obj
;
477 struct intel_texture_object
*iobj
;
480 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
481 if (!obj
|| obj
->Target
!= target
) {
482 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
486 if (target
== GL_TEXTURE_CUBE_MAP
)
489 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
490 iobj
= intel_texture_object(obj
);
491 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
492 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
496 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
497 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
501 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
502 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
505 image
= calloc(1, sizeof *image
);
507 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
511 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
512 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
513 image
->data
= loaderPrivate
;
514 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
515 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
516 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
517 if (image
->dri_format
== MESA_FORMAT_NONE
) {
518 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
523 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
528 intel_destroy_image(__DRIimage
*image
)
530 drm_intel_bo_unreference(image
->bo
);
535 intel_create_image(__DRIscreen
*screen
,
536 int width
, int height
, int format
,
541 struct intel_screen
*intelScreen
= screen
->driverPrivate
;
546 tiling
= I915_TILING_X
;
547 if (use
& __DRI_IMAGE_USE_CURSOR
) {
548 if (width
!= 64 || height
!= 64)
550 tiling
= I915_TILING_NONE
;
553 if (use
& __DRI_IMAGE_USE_LINEAR
)
554 tiling
= I915_TILING_NONE
;
556 image
= intel_allocate_image(format
, loaderPrivate
);
560 cpp
= _mesa_get_format_bytes(image
->format
);
561 image
->bo
= drm_intel_bo_alloc_tiled(intelScreen
->bufmgr
, "image",
562 width
, height
, cpp
, &tiling
,
564 if (image
->bo
== NULL
) {
568 image
->width
= width
;
569 image
->height
= height
;
570 image
->pitch
= pitch
;
576 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
579 case __DRI_IMAGE_ATTRIB_STRIDE
:
580 *value
= image
->pitch
;
582 case __DRI_IMAGE_ATTRIB_HANDLE
:
583 *value
= image
->bo
->handle
;
585 case __DRI_IMAGE_ATTRIB_NAME
:
586 return !drm_intel_bo_flink(image
->bo
, (uint32_t *) value
);
587 case __DRI_IMAGE_ATTRIB_FORMAT
:
588 *value
= image
->dri_format
;
590 case __DRI_IMAGE_ATTRIB_WIDTH
:
591 *value
= image
->width
;
593 case __DRI_IMAGE_ATTRIB_HEIGHT
:
594 *value
= image
->height
;
596 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
597 if (image
->planar_format
== NULL
)
599 *value
= image
->planar_format
->components
;
601 case __DRI_IMAGE_ATTRIB_FD
:
602 if (drm_intel_bo_gem_export_to_prime(image
->bo
, value
) == 0)
605 case __DRI_IMAGE_ATTRIB_FOURCC
:
606 if (intel_lookup_fourcc(image
->dri_format
, value
))
609 case __DRI_IMAGE_ATTRIB_NUM_PLANES
:
619 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
623 image
= calloc(1, sizeof *image
);
627 drm_intel_bo_reference(orig_image
->bo
);
628 image
->bo
= orig_image
->bo
;
629 image
->internal_format
= orig_image
->internal_format
;
630 image
->planar_format
= orig_image
->planar_format
;
631 image
->dri_format
= orig_image
->dri_format
;
632 image
->format
= orig_image
->format
;
633 image
->offset
= orig_image
->offset
;
634 image
->width
= orig_image
->width
;
635 image
->height
= orig_image
->height
;
636 image
->pitch
= orig_image
->pitch
;
637 image
->tile_x
= orig_image
->tile_x
;
638 image
->tile_y
= orig_image
->tile_y
;
639 image
->has_depthstencil
= orig_image
->has_depthstencil
;
640 image
->data
= loaderPrivate
;
642 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
643 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
649 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
651 if (use
& __DRI_IMAGE_USE_CURSOR
) {
652 if (image
->width
!= 64 || image
->height
!= 64)
660 intel_create_image_from_names(__DRIscreen
*screen
,
661 int width
, int height
, int fourcc
,
662 int *names
, int num_names
,
663 int *strides
, int *offsets
,
666 struct intel_image_format
*f
= NULL
;
670 if (screen
== NULL
|| names
== NULL
|| num_names
!= 1)
673 f
= intel_image_format_lookup(fourcc
);
677 image
= intel_create_image_from_name(screen
, width
, height
,
678 __DRI_IMAGE_FORMAT_NONE
,
679 names
[0], strides
[0],
685 image
->planar_format
= f
;
686 for (i
= 0; i
< f
->nplanes
; i
++) {
687 index
= f
->planes
[i
].buffer_index
;
688 image
->offsets
[index
] = offsets
[index
];
689 image
->strides
[index
] = strides
[index
];
696 intel_create_image_from_fds(__DRIscreen
*screen
,
697 int width
, int height
, int fourcc
,
698 int *fds
, int num_fds
, int *strides
, int *offsets
,
701 struct intel_screen
*intelScreen
= screen
->driverPrivate
;
702 struct intel_image_format
*f
;
706 if (fds
== NULL
|| num_fds
< 1)
709 /* We only support all planes from the same bo */
710 for (i
= 0; i
< num_fds
; i
++)
711 if (fds
[0] != fds
[i
])
714 f
= intel_image_format_lookup(fourcc
);
719 image
= intel_allocate_image(f
->planes
[0].dri_format
, loaderPrivate
);
721 image
= intel_allocate_image(__DRI_IMAGE_FORMAT_NONE
, loaderPrivate
);
726 image
->width
= width
;
727 image
->height
= height
;
728 image
->pitch
= strides
[0];
730 image
->planar_format
= f
;
732 for (i
= 0; i
< f
->nplanes
; i
++) {
733 index
= f
->planes
[i
].buffer_index
;
734 image
->offsets
[index
] = offsets
[index
];
735 image
->strides
[index
] = strides
[index
];
737 const int plane_height
= height
>> f
->planes
[i
].height_shift
;
738 const int end
= offsets
[index
] + plane_height
* strides
[index
];
743 image
->bo
= drm_intel_bo_gem_create_from_prime(intelScreen
->bufmgr
,
745 if (image
->bo
== NULL
) {
750 if (f
->nplanes
== 1) {
751 image
->offset
= image
->offsets
[0];
752 intel_image_warn_if_unaligned(image
, __func__
);
759 intel_create_image_from_dma_bufs(__DRIscreen
*screen
,
760 int width
, int height
, int fourcc
,
761 int *fds
, int num_fds
,
762 int *strides
, int *offsets
,
763 enum __DRIYUVColorSpace yuv_color_space
,
764 enum __DRISampleRange sample_range
,
765 enum __DRIChromaSiting horizontal_siting
,
766 enum __DRIChromaSiting vertical_siting
,
771 struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
774 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
778 image
= intel_create_image_from_fds(screen
, width
, height
, fourcc
, fds
,
779 num_fds
, strides
, offsets
,
783 * Invalid parameters and any inconsistencies between are assumed to be
784 * checked by the caller. Therefore besides unsupported formats one can fail
785 * only in allocation.
788 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
792 image
->dma_buf_imported
= true;
793 image
->yuv_color_space
= yuv_color_space
;
794 image
->sample_range
= sample_range
;
795 image
->horizontal_siting
= horizontal_siting
;
796 image
->vertical_siting
= vertical_siting
;
798 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
803 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
805 int width
, height
, offset
, stride
, dri_format
, index
;
806 struct intel_image_format
*f
;
809 if (parent
== NULL
|| parent
->planar_format
== NULL
)
812 f
= parent
->planar_format
;
814 if (plane
>= f
->nplanes
)
817 width
= parent
->width
>> f
->planes
[plane
].width_shift
;
818 height
= parent
->height
>> f
->planes
[plane
].height_shift
;
819 dri_format
= f
->planes
[plane
].dri_format
;
820 index
= f
->planes
[plane
].buffer_index
;
821 offset
= parent
->offsets
[index
];
822 stride
= parent
->strides
[index
];
824 image
= intel_allocate_image(dri_format
, loaderPrivate
);
828 if (offset
+ height
* stride
> parent
->bo
->size
) {
829 _mesa_warning(NULL
, "intel_create_sub_image: subimage out of bounds");
834 image
->bo
= parent
->bo
;
835 drm_intel_bo_reference(parent
->bo
);
837 image
->width
= width
;
838 image
->height
= height
;
839 image
->pitch
= stride
;
840 image
->offset
= offset
;
842 intel_image_warn_if_unaligned(image
, __func__
);
847 static const __DRIimageExtension intelImageExtension
= {
848 .base
= { __DRI_IMAGE
, 11 },
850 .createImageFromName
= intel_create_image_from_name
,
851 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
852 .destroyImage
= intel_destroy_image
,
853 .createImage
= intel_create_image
,
854 .queryImage
= intel_query_image
,
855 .dupImage
= intel_dup_image
,
856 .validateUsage
= intel_validate_usage
,
857 .createImageFromNames
= intel_create_image_from_names
,
858 .fromPlanar
= intel_from_planar
,
859 .createImageFromTexture
= intel_create_image_from_texture
,
860 .createImageFromFds
= intel_create_image_from_fds
,
861 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
,
863 .getCapabilities
= NULL
867 brw_query_renderer_integer(__DRIscreen
*psp
, int param
, unsigned int *value
)
869 const struct intel_screen
*const intelScreen
=
870 (struct intel_screen
*) psp
->driverPrivate
;
873 case __DRI2_RENDERER_VENDOR_ID
:
876 case __DRI2_RENDERER_DEVICE_ID
:
877 value
[0] = intelScreen
->deviceID
;
879 case __DRI2_RENDERER_ACCELERATED
:
882 case __DRI2_RENDERER_VIDEO_MEMORY
: {
883 /* Once a batch uses more than 75% of the maximum mappable size, we
884 * assume that there's some fragmentation, and we start doing extra
885 * flushing, etc. That's the big cliff apps will care about.
888 size_t mappable_size
;
890 drm_intel_get_aperture_sizes(psp
->fd
, &mappable_size
, &aper_size
);
892 const unsigned gpu_mappable_megabytes
=
893 (aper_size
/ (1024 * 1024)) * 3 / 4;
895 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
896 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
898 if (system_memory_pages
<= 0 || system_page_size
<= 0)
901 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
902 * (uint64_t) system_page_size
;
904 const unsigned system_memory_megabytes
=
905 (unsigned) (system_memory_bytes
/ (1024 * 1024));
907 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
910 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
914 return driQueryRendererIntegerCommon(psp
, param
, value
);
921 brw_query_renderer_string(__DRIscreen
*psp
, int param
, const char **value
)
923 const struct intel_screen
*intelScreen
=
924 (struct intel_screen
*) psp
->driverPrivate
;
927 case __DRI2_RENDERER_VENDOR_ID
:
928 value
[0] = brw_vendor_string
;
930 case __DRI2_RENDERER_DEVICE_ID
:
931 value
[0] = brw_get_renderer_string(intelScreen
);
940 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
941 .base
= { __DRI2_RENDERER_QUERY
, 1 },
943 .queryInteger
= brw_query_renderer_integer
,
944 .queryString
= brw_query_renderer_string
947 static const __DRIrobustnessExtension dri2Robustness
= {
948 .base
= { __DRI2_ROBUSTNESS
, 1 }
951 static const __DRIextension
*intelScreenExtensions
[] = {
952 &intelTexBufferExtension
.base
,
953 &intelFenceExtension
.base
,
954 &intelFlushExtension
.base
,
955 &intelImageExtension
.base
,
956 &intelRendererQueryExtension
.base
,
957 &dri2ConfigQueryExtension
.base
,
961 static const __DRIextension
*intelRobustScreenExtensions
[] = {
962 &intelTexBufferExtension
.base
,
963 &intelFenceExtension
.base
,
964 &intelFlushExtension
.base
,
965 &intelImageExtension
.base
,
966 &intelRendererQueryExtension
.base
,
967 &dri2ConfigQueryExtension
.base
,
968 &dri2Robustness
.base
,
973 intel_get_param(struct intel_screen
*screen
, int param
, int *value
)
976 struct drm_i915_getparam gp
;
978 memset(&gp
, 0, sizeof(gp
));
982 ret
= drmCommandWriteRead(screen
->driScrnPriv
->fd
,
983 DRM_I915_GETPARAM
, &gp
, sizeof(gp
));
984 if (ret
< 0 && ret
!= -EINVAL
)
985 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
991 intel_get_boolean(struct intel_screen
*screen
, int param
)
994 return (intel_get_param(screen
, param
, &value
) == 0) && value
;
998 intelDestroyScreen(__DRIscreen
* sPriv
)
1000 struct intel_screen
*intelScreen
= sPriv
->driverPrivate
;
1002 dri_bufmgr_destroy(intelScreen
->bufmgr
);
1003 driDestroyOptionInfo(&intelScreen
->optionCache
);
1005 ralloc_free(intelScreen
);
1006 sPriv
->driverPrivate
= NULL
;
1011 * This is called when we need to set up GL rendering to a new X window.
1014 intelCreateBuffer(__DRIscreen
* driScrnPriv
,
1015 __DRIdrawable
* driDrawPriv
,
1016 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
1018 struct intel_renderbuffer
*rb
;
1019 struct intel_screen
*screen
= (struct intel_screen
*) driScrnPriv
->driverPrivate
;
1020 mesa_format rgbFormat
;
1021 unsigned num_samples
= intel_quantize_num_samples(screen
, mesaVis
->samples
);
1022 struct gl_framebuffer
*fb
;
1027 fb
= CALLOC_STRUCT(gl_framebuffer
);
1031 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
1033 if (screen
->winsys_msaa_samples_override
!= -1) {
1034 num_samples
= screen
->winsys_msaa_samples_override
;
1035 fb
->Visual
.samples
= num_samples
;
1038 if (mesaVis
->redBits
== 5) {
1039 rgbFormat
= mesaVis
->redMask
== 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1040 : MESA_FORMAT_B5G6R5_UNORM
;
1041 } else if (mesaVis
->sRGBCapable
) {
1042 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1043 : MESA_FORMAT_B8G8R8A8_SRGB
;
1044 } else if (mesaVis
->alphaBits
== 0) {
1045 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8X8_UNORM
1046 : MESA_FORMAT_B8G8R8X8_UNORM
;
1048 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1049 : MESA_FORMAT_B8G8R8A8_SRGB
;
1050 fb
->Visual
.sRGBCapable
= true;
1053 /* setup the hardware-based renderbuffers */
1054 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
1055 _mesa_add_renderbuffer(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
1057 if (mesaVis
->doubleBufferMode
) {
1058 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
1059 _mesa_add_renderbuffer(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1063 * Assert here that the gl_config has an expected depth/stencil bit
1064 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1065 * which constructs the advertised configs.)
1067 if (mesaVis
->depthBits
== 24) {
1068 assert(mesaVis
->stencilBits
== 8);
1070 if (screen
->devinfo
->has_hiz_and_separate_stencil
) {
1071 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_X8_UINT
,
1073 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1074 rb
= intel_create_private_renderbuffer(MESA_FORMAT_S_UINT8
,
1076 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1079 * Use combined depth/stencil. Note that the renderbuffer is
1080 * attached to two attachment points.
1082 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_S8_UINT
,
1084 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1085 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1088 else if (mesaVis
->depthBits
== 16) {
1089 assert(mesaVis
->stencilBits
== 0);
1090 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z_UNORM16
,
1092 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1095 assert(mesaVis
->depthBits
== 0);
1096 assert(mesaVis
->stencilBits
== 0);
1099 /* now add any/all software-based renderbuffers we may need */
1100 _swrast_add_soft_renderbuffers(fb
,
1101 false, /* never sw color */
1102 false, /* never sw depth */
1103 false, /* never sw stencil */
1104 mesaVis
->accumRedBits
> 0,
1105 false, /* never sw alpha */
1106 false /* never sw aux */ );
1107 driDrawPriv
->driverPrivate
= fb
;
1113 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1115 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1117 _mesa_reference_framebuffer(&fb
, NULL
);
1121 intel_detect_sseu(struct intel_screen
*intelScreen
)
1123 assert(intelScreen
->devinfo
->gen
>= 8);
1126 intelScreen
->subslice_total
= -1;
1127 intelScreen
->eu_total
= -1;
1129 ret
= intel_get_param(intelScreen
, I915_PARAM_SUBSLICE_TOTAL
,
1130 &intelScreen
->subslice_total
);
1131 if (ret
< 0 && ret
!= -EINVAL
)
1134 ret
= intel_get_param(intelScreen
,
1135 I915_PARAM_EU_TOTAL
, &intelScreen
->eu_total
);
1136 if (ret
< 0 && ret
!= -EINVAL
)
1139 /* Without this information, we cannot get the right Braswell brandstrings,
1140 * and we have to use conservative numbers for GPGPU on many platforms, but
1141 * otherwise, things will just work.
1143 if (intelScreen
->subslice_total
< 1 || intelScreen
->eu_total
< 1)
1145 "Kernel 4.1 required to properly query GPU properties.\n");
1150 intelScreen
->subslice_total
= -1;
1151 intelScreen
->eu_total
= -1;
1152 _mesa_warning(NULL
, "Failed to query GPU properties (%s).\n", strerror(-ret
));
1156 intel_init_bufmgr(struct intel_screen
*intelScreen
)
1158 __DRIscreen
*spriv
= intelScreen
->driScrnPriv
;
1160 intelScreen
->no_hw
= getenv("INTEL_NO_HW") != NULL
;
1162 intelScreen
->bufmgr
= intel_bufmgr_gem_init(spriv
->fd
, BATCH_SZ
);
1163 if (intelScreen
->bufmgr
== NULL
) {
1164 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1165 __func__
, __LINE__
);
1169 drm_intel_bufmgr_gem_enable_fenced_relocs(intelScreen
->bufmgr
);
1171 if (!intel_get_boolean(intelScreen
, I915_PARAM_HAS_RELAXED_DELTA
)) {
1172 fprintf(stderr
, "[%s: %u] Kernel 2.6.39 required.\n", __func__
, __LINE__
);
1180 intel_detect_swizzling(struct intel_screen
*screen
)
1182 drm_intel_bo
*buffer
;
1183 unsigned long flags
= 0;
1184 unsigned long aligned_pitch
;
1185 uint32_t tiling
= I915_TILING_X
;
1186 uint32_t swizzle_mode
= 0;
1188 buffer
= drm_intel_bo_alloc_tiled(screen
->bufmgr
, "swizzle test",
1190 &tiling
, &aligned_pitch
, flags
);
1194 drm_intel_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1195 drm_intel_bo_unreference(buffer
);
1197 if (swizzle_mode
== I915_BIT_6_SWIZZLE_NONE
)
1204 intel_detect_timestamp(struct intel_screen
*screen
)
1206 uint64_t dummy
= 0, last
= 0;
1207 int upper
, lower
, loops
;
1209 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1210 * TIMESTAMP register being shifted and the low 32bits always zero.
1212 * More recent kernels offer an interface to read the full 36bits
1215 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &dummy
) == 0)
1218 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1219 * upper 32bits for a rapidly changing timestamp.
1221 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
, &last
))
1225 for (loops
= 0; loops
< 10; loops
++) {
1226 /* The TIMESTAMP should change every 80ns, so several round trips
1227 * through the kernel should be enough to advance it.
1229 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
, &dummy
))
1232 upper
+= (dummy
>> 32) != (last
>> 32);
1233 if (upper
> 1) /* beware 32bit counter overflow */
1234 return 2; /* upper dword holds the low 32bits of the timestamp */
1236 lower
+= (dummy
& 0xffffffff) != (last
& 0xffffffff);
1238 return 1; /* timestamp is unshifted */
1243 /* No advancement? No timestamp! */
1248 * Return array of MSAA modes supported by the hardware. The array is
1249 * zero-terminated and sorted in decreasing order.
1252 intel_supported_msaa_modes(const struct intel_screen
*screen
)
1254 static const int gen9_modes
[] = {16, 8, 4, 2, 0, -1};
1255 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
1256 static const int gen7_modes
[] = {8, 4, 0, -1};
1257 static const int gen6_modes
[] = {4, 0, -1};
1258 static const int gen4_modes
[] = {0, -1};
1260 if (screen
->devinfo
->gen
>= 9) {
1262 } else if (screen
->devinfo
->gen
>= 8) {
1264 } else if (screen
->devinfo
->gen
>= 7) {
1266 } else if (screen
->devinfo
->gen
== 6) {
1273 static __DRIconfig
**
1274 intel_screen_make_configs(__DRIscreen
*dri_screen
)
1276 static const mesa_format formats
[] = {
1277 MESA_FORMAT_B5G6R5_UNORM
,
1278 MESA_FORMAT_B8G8R8A8_UNORM
,
1279 MESA_FORMAT_B8G8R8X8_UNORM
1282 /* GLX_SWAP_COPY_OML is not supported due to page flipping. */
1283 static const GLenum back_buffer_modes
[] = {
1284 GLX_SWAP_UNDEFINED_OML
, GLX_NONE
,
1287 static const uint8_t singlesample_samples
[1] = {0};
1288 static const uint8_t multisample_samples
[2] = {4, 8};
1290 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1291 const struct brw_device_info
*devinfo
= screen
->devinfo
;
1292 uint8_t depth_bits
[4], stencil_bits
[4];
1293 __DRIconfig
**configs
= NULL
;
1295 /* Generate singlesample configs without accumulation buffer. */
1296 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1297 __DRIconfig
**new_configs
;
1298 int num_depth_stencil_bits
= 2;
1300 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
1301 * buffer that has a different number of bits per pixel than the color
1302 * buffer, gen >= 6 supports this.
1305 stencil_bits
[0] = 0;
1307 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1309 stencil_bits
[1] = 0;
1310 if (devinfo
->gen
>= 6) {
1312 stencil_bits
[2] = 8;
1313 num_depth_stencil_bits
= 3;
1317 stencil_bits
[1] = 8;
1320 new_configs
= driCreateConfigs(formats
[i
],
1323 num_depth_stencil_bits
,
1324 back_buffer_modes
, 2,
1325 singlesample_samples
, 1,
1327 configs
= driConcatConfigs(configs
, new_configs
);
1330 /* Generate the minimum possible set of configs that include an
1331 * accumulation buffer.
1333 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1334 __DRIconfig
**new_configs
;
1336 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1338 stencil_bits
[0] = 0;
1341 stencil_bits
[0] = 8;
1344 new_configs
= driCreateConfigs(formats
[i
],
1345 depth_bits
, stencil_bits
, 1,
1346 back_buffer_modes
, 1,
1347 singlesample_samples
, 1,
1349 configs
= driConcatConfigs(configs
, new_configs
);
1352 /* Generate multisample configs.
1354 * This loop breaks early, and hence is a no-op, on gen < 6.
1356 * Multisample configs must follow the singlesample configs in order to
1357 * work around an X server bug present in 1.12. The X server chooses to
1358 * associate the first listed RGBA888-Z24S8 config, regardless of its
1359 * sample count, with the 32-bit depth visual used for compositing.
1361 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
1362 * supported. Singlebuffer configs are not supported because no one wants
1365 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1366 if (devinfo
->gen
< 6)
1369 __DRIconfig
**new_configs
;
1370 const int num_depth_stencil_bits
= 2;
1371 int num_msaa_modes
= 0;
1374 stencil_bits
[0] = 0;
1376 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1378 stencil_bits
[1] = 0;
1381 stencil_bits
[1] = 8;
1384 if (devinfo
->gen
>= 7)
1386 else if (devinfo
->gen
== 6)
1389 new_configs
= driCreateConfigs(formats
[i
],
1392 num_depth_stencil_bits
,
1393 back_buffer_modes
, 1,
1394 multisample_samples
,
1397 configs
= driConcatConfigs(configs
, new_configs
);
1400 if (configs
== NULL
) {
1401 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
1410 set_max_gl_versions(struct intel_screen
*screen
)
1412 __DRIscreen
*psp
= screen
->driScrnPriv
;
1414 switch (screen
->devinfo
->gen
) {
1417 psp
->max_gl_core_version
= 43;
1418 psp
->max_gl_compat_version
= 30;
1419 psp
->max_gl_es1_version
= 11;
1420 psp
->max_gl_es2_version
= 31;
1424 psp
->max_gl_core_version
= 33;
1425 psp
->max_gl_compat_version
= 30;
1426 psp
->max_gl_es1_version
= 11;
1427 psp
->max_gl_es2_version
= 30;
1431 psp
->max_gl_core_version
= 0;
1432 psp
->max_gl_compat_version
= 21;
1433 psp
->max_gl_es1_version
= 11;
1434 psp
->max_gl_es2_version
= 20;
1437 unreachable("unrecognized intel_screen::gen");
1442 * Return the revision (generally the revid field of the PCI header) of the
1445 * XXX: This function is useful to keep around even if it is not currently in
1446 * use. It is necessary for new platforms and revision specific workarounds or
1447 * features. Please don't remove it so that we know it at least continues to
1450 static __attribute__((__unused__
)) int
1451 brw_get_revision(int fd
)
1453 struct drm_i915_getparam gp
;
1457 memset(&gp
, 0, sizeof(gp
));
1458 gp
.param
= I915_PARAM_REVISION
;
1459 gp
.value
= &revision
;
1461 ret
= drmCommandWriteRead(fd
, DRM_I915_GETPARAM
, &gp
, sizeof(gp
));
1468 /* Drop when RS headers get pulled to libdrm */
1469 #ifndef I915_PARAM_HAS_RESOURCE_STREAMER
1470 #define I915_PARAM_HAS_RESOURCE_STREAMER 36
1474 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
1476 struct brw_context
*brw
= (struct brw_context
*)data
;
1479 va_start(args
, fmt
);
1481 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
1482 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
1483 MESA_DEBUG_TYPE_OTHER
,
1484 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
1489 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
1491 struct brw_context
*brw
= (struct brw_context
*)data
;
1494 va_start(args
, fmt
);
1496 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
1498 va_copy(args_copy
, args
);
1499 vfprintf(stderr
, fmt
, args_copy
);
1503 if (brw
->perf_debug
) {
1505 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
1506 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
1507 MESA_DEBUG_TYPE_PERFORMANCE
,
1508 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
1514 * This is the driver specific part of the createNewScreen entry point.
1515 * Called when using DRI2.
1517 * \return the struct gl_config supported by this driver
1520 __DRIconfig
**intelInitScreen2(__DRIscreen
*psp
)
1522 struct intel_screen
*intelScreen
;
1524 if (psp
->image
.loader
) {
1525 } else if (psp
->dri2
.loader
->base
.version
<= 2 ||
1526 psp
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
1528 "\nERROR! DRI2 loader with getBuffersWithFormat() "
1529 "support required\n");
1533 /* Allocate the private area */
1534 intelScreen
= rzalloc(NULL
, struct intel_screen
);
1536 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
1539 /* parse information in __driConfigOptions */
1540 driParseOptionInfo(&intelScreen
->optionCache
, brw_config_options
.xml
);
1542 intelScreen
->driScrnPriv
= psp
;
1543 psp
->driverPrivate
= (void *) intelScreen
;
1545 if (!intel_init_bufmgr(intelScreen
))
1548 intelScreen
->deviceID
= drm_intel_bufmgr_gem_get_devid(intelScreen
->bufmgr
);
1549 intelScreen
->devinfo
= brw_get_device_info(intelScreen
->deviceID
);
1550 if (!intelScreen
->devinfo
)
1553 brw_process_intel_debug_variable();
1555 if (INTEL_DEBUG
& DEBUG_BUFMGR
)
1556 dri_bufmgr_set_debug(intelScreen
->bufmgr
, true);
1558 if ((INTEL_DEBUG
& DEBUG_SHADER_TIME
) && intelScreen
->devinfo
->gen
< 7) {
1560 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
1561 INTEL_DEBUG
&= ~DEBUG_SHADER_TIME
;
1564 if (INTEL_DEBUG
& DEBUG_AUB
)
1565 drm_intel_bufmgr_gem_set_aub_dump(intelScreen
->bufmgr
, true);
1567 intelScreen
->hw_has_swizzling
= intel_detect_swizzling(intelScreen
);
1568 intelScreen
->hw_has_timestamp
= intel_detect_timestamp(intelScreen
);
1570 /* GENs prior to 8 do not support EU/Subslice info */
1571 if (intelScreen
->devinfo
->gen
>= 8) {
1572 intel_detect_sseu(intelScreen
);
1573 } else if (intelScreen
->devinfo
->gen
== 7) {
1574 intelScreen
->subslice_total
= 1 << (intelScreen
->devinfo
->gt
- 1);
1577 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
1579 intelScreen
->winsys_msaa_samples_override
=
1580 intel_quantize_num_samples(intelScreen
, atoi(force_msaa
));
1581 printf("Forcing winsys sample count to %d\n",
1582 intelScreen
->winsys_msaa_samples_override
);
1584 intelScreen
->winsys_msaa_samples_override
= -1;
1587 set_max_gl_versions(intelScreen
);
1589 /* Notification of GPU resets requires hardware contexts and a kernel new
1590 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
1591 * supported, calling it with a context of 0 will either generate EPERM or
1592 * no error. If the ioctl is not supported, it always generate EINVAL.
1593 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
1594 * extension to the loader.
1596 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
1598 if (intelScreen
->devinfo
->gen
>= 6) {
1599 struct drm_i915_reset_stats stats
;
1600 memset(&stats
, 0, sizeof(stats
));
1602 const int ret
= drmIoctl(psp
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
1604 intelScreen
->has_context_reset_notification
=
1605 (ret
!= -1 || errno
!= EINVAL
);
1608 if (intel_get_param(intelScreen
, I915_PARAM_CMD_PARSER_VERSION
,
1609 &intelScreen
->cmd_parser_version
) < 0) {
1610 intelScreen
->cmd_parser_version
= 0;
1613 /* Haswell requires command parser version 6 in order to write to the
1614 * MI_MATH GPR registers, and version 7 in order to use
1615 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
1617 intelScreen
->has_mi_math_and_lrr
= intelScreen
->devinfo
->gen
>= 8 ||
1618 (intelScreen
->devinfo
->is_haswell
&&
1619 intelScreen
->cmd_parser_version
>= 7);
1621 psp
->extensions
= !intelScreen
->has_context_reset_notification
1622 ? intelScreenExtensions
: intelRobustScreenExtensions
;
1624 intelScreen
->compiler
= brw_compiler_create(intelScreen
,
1625 intelScreen
->devinfo
);
1626 intelScreen
->compiler
->shader_debug_log
= shader_debug_log_mesa
;
1627 intelScreen
->compiler
->shader_perf_log
= shader_perf_log_mesa
;
1628 intelScreen
->program_id
= 1;
1630 if (intelScreen
->devinfo
->has_resource_streamer
) {
1631 intelScreen
->has_resource_streamer
=
1632 intel_get_boolean(intelScreen
, I915_PARAM_HAS_RESOURCE_STREAMER
);
1635 return (const __DRIconfig
**) intel_screen_make_configs(psp
);
1638 struct intel_buffer
{
1643 static __DRIbuffer
*
1644 intelAllocateBuffer(__DRIscreen
*screen
,
1645 unsigned attachment
, unsigned format
,
1646 int width
, int height
)
1648 struct intel_buffer
*intelBuffer
;
1649 struct intel_screen
*intelScreen
= screen
->driverPrivate
;
1651 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
1652 attachment
== __DRI_BUFFER_BACK_LEFT
);
1654 intelBuffer
= calloc(1, sizeof *intelBuffer
);
1655 if (intelBuffer
== NULL
)
1658 /* The front and back buffers are color buffers, which are X tiled. */
1659 uint32_t tiling
= I915_TILING_X
;
1660 unsigned long pitch
;
1661 int cpp
= format
/ 8;
1662 intelBuffer
->bo
= drm_intel_bo_alloc_tiled(intelScreen
->bufmgr
,
1663 "intelAllocateBuffer",
1668 BO_ALLOC_FOR_RENDER
);
1670 if (intelBuffer
->bo
== NULL
) {
1675 drm_intel_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
1677 intelBuffer
->base
.attachment
= attachment
;
1678 intelBuffer
->base
.cpp
= cpp
;
1679 intelBuffer
->base
.pitch
= pitch
;
1681 return &intelBuffer
->base
;
1685 intelReleaseBuffer(__DRIscreen
*screen
, __DRIbuffer
*buffer
)
1687 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
1689 drm_intel_bo_unreference(intelBuffer
->bo
);
1693 static const struct __DriverAPIRec brw_driver_api
= {
1694 .InitScreen
= intelInitScreen2
,
1695 .DestroyScreen
= intelDestroyScreen
,
1696 .CreateContext
= brwCreateContext
,
1697 .DestroyContext
= intelDestroyContext
,
1698 .CreateBuffer
= intelCreateBuffer
,
1699 .DestroyBuffer
= intelDestroyBuffer
,
1700 .MakeCurrent
= intelMakeCurrent
,
1701 .UnbindContext
= intelUnbindContext
,
1702 .AllocateBuffer
= intelAllocateBuffer
,
1703 .ReleaseBuffer
= intelReleaseBuffer
1706 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
1707 .base
= { __DRI_DRIVER_VTABLE
, 1 },
1708 .vtable
= &brw_driver_api
,
1711 static const __DRIextension
*brw_driver_extensions
[] = {
1712 &driCoreExtension
.base
,
1713 &driImageDriverExtension
.base
,
1714 &driDRI2Extension
.base
,
1716 &brw_config_options
.base
,
1720 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
1722 globalDriverAPI
= &brw_driver_api
;
1724 return brw_driver_extensions
;