2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "main/context.h"
30 #include "main/framebuffer.h"
31 #include "main/renderbuffer.h"
32 #include "main/texobj.h"
33 #include "main/hash.h"
34 #include "main/fbobject.h"
35 #include "main/version.h"
36 #include "swrast/s_renderbuffer.h"
37 #include "util/ralloc.h"
38 #include "brw_shader.h"
39 #include "compiler/nir/nir.h"
44 static const __DRIconfigOptionsExtension brw_config_options
= {
45 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
48 DRI_CONF_SECTION_PERFORMANCE
49 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_ALWAYS_SYNC
)
50 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
51 * DRI_CONF_BO_REUSE_ALL
53 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
54 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
55 DRI_CONF_ENUM(0, "Disable buffer object reuse")
56 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
60 DRI_CONF_OPT_BEGIN_B(hiz
, "true")
61 DRI_CONF_DESC(en
, "Enable Hierarchical Z on gen6+")
65 DRI_CONF_SECTION_QUALITY
66 DRI_CONF_FORCE_S3TC_ENABLE("false")
68 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
69 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
70 "given integer. If negative, then do not clamp.")
74 DRI_CONF_SECTION_DEBUG
75 DRI_CONF_NO_RAST("false")
76 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
77 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
78 DRI_CONF_DISABLE_THROTTLING("false")
79 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
80 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
81 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
82 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
83 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
85 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
86 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
92 #include "intel_batchbuffer.h"
93 #include "intel_buffers.h"
94 #include "intel_bufmgr.h"
95 #include "intel_fbo.h"
96 #include "intel_mipmap_tree.h"
97 #include "intel_screen.h"
98 #include "intel_tex.h"
99 #include "intel_image.h"
101 #include "brw_context.h"
103 #include "i915_drm.h"
106 * For debugging purposes, this returns a time in seconds.
113 clock_gettime(CLOCK_MONOTONIC
, &tp
);
115 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
119 aub_dump_bmp(struct gl_context
*ctx
)
121 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
123 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
124 struct intel_renderbuffer
*irb
=
125 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
127 if (irb
&& irb
->mt
) {
128 enum aub_dump_bmp_format format
;
130 switch (irb
->Base
.Base
.Format
) {
131 case MESA_FORMAT_B8G8R8A8_UNORM
:
132 case MESA_FORMAT_B8G8R8X8_UNORM
:
133 format
= AUB_DUMP_BMP_FORMAT_ARGB_8888
;
139 drm_intel_gem_bo_aub_dump_bmp(irb
->mt
->bo
,
142 irb
->Base
.Base
.Width
,
143 irb
->Base
.Base
.Height
,
151 static const __DRItexBufferExtension intelTexBufferExtension
= {
152 .base
= { __DRI_TEX_BUFFER
, 3 },
154 .setTexBuffer
= intelSetTexBuffer
,
155 .setTexBuffer2
= intelSetTexBuffer2
,
156 .releaseTexBuffer
= NULL
,
160 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
161 __DRIdrawable
*dPriv
,
163 enum __DRI2throttleReason reason
)
165 struct brw_context
*brw
= cPriv
->driverPrivate
;
170 struct gl_context
*ctx
= &brw
->ctx
;
172 FLUSH_VERTICES(ctx
, 0);
174 if (flags
& __DRI2_FLUSH_DRAWABLE
)
175 intel_resolve_for_dri2_flush(brw
, dPriv
);
177 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
)
178 brw
->need_swap_throttle
= true;
179 if (reason
== __DRI2_THROTTLE_FLUSHFRONT
)
180 brw
->need_flush_throttle
= true;
182 intel_batchbuffer_flush(brw
);
184 if (INTEL_DEBUG
& DEBUG_AUB
) {
190 * Provides compatibility with loaders that only support the older (version
191 * 1-3) flush interface.
193 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
196 intel_dri2_flush(__DRIdrawable
*drawable
)
198 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
199 __DRI2_FLUSH_DRAWABLE
,
200 __DRI2_THROTTLE_SWAPBUFFER
);
203 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
204 .base
= { __DRI2_FLUSH
, 4 },
206 .flush
= intel_dri2_flush
,
207 .invalidate
= dri2InvalidateDrawable
,
208 .flush_with_flags
= intel_dri2_flush_with_flags
,
211 static struct intel_image_format intel_image_formats
[] = {
212 { __DRI_IMAGE_FOURCC_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
213 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
215 { __DRI_IMAGE_FOURCC_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
216 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
218 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
219 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
221 { __DRI_IMAGE_FOURCC_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
222 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
224 { __DRI_IMAGE_FOURCC_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
225 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
227 { __DRI_IMAGE_FOURCC_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
228 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
230 { __DRI_IMAGE_FOURCC_R8
, __DRI_IMAGE_COMPONENTS_R
, 1,
231 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 }, } },
233 { __DRI_IMAGE_FOURCC_GR88
, __DRI_IMAGE_COMPONENTS_RG
, 1,
234 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 }, } },
236 { __DRI_IMAGE_FOURCC_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
237 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
238 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
239 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
241 { __DRI_IMAGE_FOURCC_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
242 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
243 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
244 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
246 { __DRI_IMAGE_FOURCC_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
247 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
248 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
249 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
251 { __DRI_IMAGE_FOURCC_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
252 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
253 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
254 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
256 { __DRI_IMAGE_FOURCC_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
257 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
258 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
259 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
261 { __DRI_IMAGE_FOURCC_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
262 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
263 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
265 { __DRI_IMAGE_FOURCC_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
266 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
267 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
269 /* For YUYV buffers, we set up two overlapping DRI images and treat
270 * them as planar buffers in the compositors. Plane 0 is GR88 and
271 * samples YU or YV pairs and places Y into the R component, while
272 * plane 1 is ARGB and samples YUYV clusters and places pairs and
273 * places U into the G component and V into A. This lets the
274 * texture sampler interpolate the Y components correctly when
275 * sampling from plane 0, and interpolate U and V correctly when
276 * sampling from plane 1. */
277 { __DRI_IMAGE_FOURCC_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
278 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
279 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } }
283 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
285 uint32_t tiling
, swizzle
;
286 drm_intel_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
288 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
289 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
290 func
, image
->offset
);
294 static struct intel_image_format
*
295 intel_image_format_lookup(int fourcc
)
297 struct intel_image_format
*f
= NULL
;
299 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
300 if (intel_image_formats
[i
].fourcc
== fourcc
) {
301 f
= &intel_image_formats
[i
];
309 static boolean
intel_lookup_fourcc(int dri_format
, int *fourcc
)
311 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
312 if (intel_image_formats
[i
].planes
[0].dri_format
== dri_format
) {
313 *fourcc
= intel_image_formats
[i
].fourcc
;
321 intel_allocate_image(int dri_format
, void *loaderPrivate
)
325 image
= calloc(1, sizeof *image
);
329 image
->dri_format
= dri_format
;
332 image
->format
= driImageFormatToGLFormat(dri_format
);
333 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
334 image
->format
== MESA_FORMAT_NONE
) {
339 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
340 image
->data
= loaderPrivate
;
346 * Sets up a DRIImage structure to point to a slice out of a miptree.
349 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
350 struct intel_mipmap_tree
*mt
, GLuint level
,
353 intel_miptree_make_shareable(brw
, mt
);
355 intel_miptree_check_level_layer(mt
, level
, zoffset
);
357 image
->width
= minify(mt
->physical_width0
, level
- mt
->first_level
);
358 image
->height
= minify(mt
->physical_height0
, level
- mt
->first_level
);
359 image
->pitch
= mt
->pitch
;
361 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
365 drm_intel_bo_unreference(image
->bo
);
367 drm_intel_bo_reference(mt
->bo
);
371 intel_create_image_from_name(__DRIscreen
*screen
,
372 int width
, int height
, int format
,
373 int name
, int pitch
, void *loaderPrivate
)
375 struct intel_screen
*intelScreen
= screen
->driverPrivate
;
379 image
= intel_allocate_image(format
, loaderPrivate
);
383 if (image
->format
== MESA_FORMAT_NONE
)
386 cpp
= _mesa_get_format_bytes(image
->format
);
388 image
->width
= width
;
389 image
->height
= height
;
390 image
->pitch
= pitch
* cpp
;
391 image
->bo
= drm_intel_bo_gem_create_from_name(intelScreen
->bufmgr
, "image",
402 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
403 int renderbuffer
, void *loaderPrivate
)
406 struct brw_context
*brw
= context
->driverPrivate
;
407 struct gl_context
*ctx
= &brw
->ctx
;
408 struct gl_renderbuffer
*rb
;
409 struct intel_renderbuffer
*irb
;
411 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
413 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
417 irb
= intel_renderbuffer(rb
);
418 intel_miptree_make_shareable(brw
, irb
->mt
);
419 image
= calloc(1, sizeof *image
);
423 image
->internal_format
= rb
->InternalFormat
;
424 image
->format
= rb
->Format
;
426 image
->data
= loaderPrivate
;
427 drm_intel_bo_unreference(image
->bo
);
428 image
->bo
= irb
->mt
->bo
;
429 drm_intel_bo_reference(irb
->mt
->bo
);
430 image
->width
= rb
->Width
;
431 image
->height
= rb
->Height
;
432 image
->pitch
= irb
->mt
->pitch
;
433 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
434 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
436 rb
->NeedsFinishRenderTexture
= true;
441 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
442 unsigned texture
, int zoffset
,
448 struct brw_context
*brw
= context
->driverPrivate
;
449 struct gl_texture_object
*obj
;
450 struct intel_texture_object
*iobj
;
453 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
454 if (!obj
|| obj
->Target
!= target
) {
455 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
459 if (target
== GL_TEXTURE_CUBE_MAP
)
462 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
463 iobj
= intel_texture_object(obj
);
464 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
465 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
469 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
470 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
474 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
475 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
478 image
= calloc(1, sizeof *image
);
480 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
484 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
485 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
486 image
->data
= loaderPrivate
;
487 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
488 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
489 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
490 if (image
->dri_format
== MESA_FORMAT_NONE
) {
491 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
496 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
501 intel_destroy_image(__DRIimage
*image
)
503 drm_intel_bo_unreference(image
->bo
);
508 intel_create_image(__DRIscreen
*screen
,
509 int width
, int height
, int format
,
514 struct intel_screen
*intelScreen
= screen
->driverPrivate
;
519 tiling
= I915_TILING_X
;
520 if (use
& __DRI_IMAGE_USE_CURSOR
) {
521 if (width
!= 64 || height
!= 64)
523 tiling
= I915_TILING_NONE
;
526 if (use
& __DRI_IMAGE_USE_LINEAR
)
527 tiling
= I915_TILING_NONE
;
529 image
= intel_allocate_image(format
, loaderPrivate
);
533 cpp
= _mesa_get_format_bytes(image
->format
);
534 image
->bo
= drm_intel_bo_alloc_tiled(intelScreen
->bufmgr
, "image",
535 width
, height
, cpp
, &tiling
,
537 if (image
->bo
== NULL
) {
541 image
->width
= width
;
542 image
->height
= height
;
543 image
->pitch
= pitch
;
549 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
552 case __DRI_IMAGE_ATTRIB_STRIDE
:
553 *value
= image
->pitch
;
555 case __DRI_IMAGE_ATTRIB_HANDLE
:
556 *value
= image
->bo
->handle
;
558 case __DRI_IMAGE_ATTRIB_NAME
:
559 return !drm_intel_bo_flink(image
->bo
, (uint32_t *) value
);
560 case __DRI_IMAGE_ATTRIB_FORMAT
:
561 *value
= image
->dri_format
;
563 case __DRI_IMAGE_ATTRIB_WIDTH
:
564 *value
= image
->width
;
566 case __DRI_IMAGE_ATTRIB_HEIGHT
:
567 *value
= image
->height
;
569 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
570 if (image
->planar_format
== NULL
)
572 *value
= image
->planar_format
->components
;
574 case __DRI_IMAGE_ATTRIB_FD
:
575 if (drm_intel_bo_gem_export_to_prime(image
->bo
, value
) == 0)
578 case __DRI_IMAGE_ATTRIB_FOURCC
:
579 if (intel_lookup_fourcc(image
->dri_format
, value
))
582 case __DRI_IMAGE_ATTRIB_NUM_PLANES
:
592 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
596 image
= calloc(1, sizeof *image
);
600 drm_intel_bo_reference(orig_image
->bo
);
601 image
->bo
= orig_image
->bo
;
602 image
->internal_format
= orig_image
->internal_format
;
603 image
->planar_format
= orig_image
->planar_format
;
604 image
->dri_format
= orig_image
->dri_format
;
605 image
->format
= orig_image
->format
;
606 image
->offset
= orig_image
->offset
;
607 image
->width
= orig_image
->width
;
608 image
->height
= orig_image
->height
;
609 image
->pitch
= orig_image
->pitch
;
610 image
->tile_x
= orig_image
->tile_x
;
611 image
->tile_y
= orig_image
->tile_y
;
612 image
->has_depthstencil
= orig_image
->has_depthstencil
;
613 image
->data
= loaderPrivate
;
615 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
616 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
622 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
624 if (use
& __DRI_IMAGE_USE_CURSOR
) {
625 if (image
->width
!= 64 || image
->height
!= 64)
633 intel_create_image_from_names(__DRIscreen
*screen
,
634 int width
, int height
, int fourcc
,
635 int *names
, int num_names
,
636 int *strides
, int *offsets
,
639 struct intel_image_format
*f
= NULL
;
643 if (screen
== NULL
|| names
== NULL
|| num_names
!= 1)
646 f
= intel_image_format_lookup(fourcc
);
650 image
= intel_create_image_from_name(screen
, width
, height
,
651 __DRI_IMAGE_FORMAT_NONE
,
652 names
[0], strides
[0],
658 image
->planar_format
= f
;
659 for (i
= 0; i
< f
->nplanes
; i
++) {
660 index
= f
->planes
[i
].buffer_index
;
661 image
->offsets
[index
] = offsets
[index
];
662 image
->strides
[index
] = strides
[index
];
669 intel_create_image_from_fds(__DRIscreen
*screen
,
670 int width
, int height
, int fourcc
,
671 int *fds
, int num_fds
, int *strides
, int *offsets
,
674 struct intel_screen
*intelScreen
= screen
->driverPrivate
;
675 struct intel_image_format
*f
;
679 if (fds
== NULL
|| num_fds
!= 1)
682 f
= intel_image_format_lookup(fourcc
);
687 image
= intel_allocate_image(f
->planes
[0].dri_format
, loaderPrivate
);
689 image
= intel_allocate_image(__DRI_IMAGE_FORMAT_NONE
, loaderPrivate
);
694 image
->bo
= drm_intel_bo_gem_create_from_prime(intelScreen
->bufmgr
,
696 height
* strides
[0]);
697 if (image
->bo
== NULL
) {
701 image
->width
= width
;
702 image
->height
= height
;
703 image
->pitch
= strides
[0];
705 image
->planar_format
= f
;
706 for (i
= 0; i
< f
->nplanes
; i
++) {
707 index
= f
->planes
[i
].buffer_index
;
708 image
->offsets
[index
] = offsets
[index
];
709 image
->strides
[index
] = strides
[index
];
712 if (f
->nplanes
== 1) {
713 image
->offset
= image
->offsets
[0];
714 intel_image_warn_if_unaligned(image
, __func__
);
721 intel_create_image_from_dma_bufs(__DRIscreen
*screen
,
722 int width
, int height
, int fourcc
,
723 int *fds
, int num_fds
,
724 int *strides
, int *offsets
,
725 enum __DRIYUVColorSpace yuv_color_space
,
726 enum __DRISampleRange sample_range
,
727 enum __DRIChromaSiting horizontal_siting
,
728 enum __DRIChromaSiting vertical_siting
,
733 struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
735 /* For now only packed formats that have native sampling are supported. */
736 if (!f
|| f
->nplanes
!= 1) {
737 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
741 image
= intel_create_image_from_fds(screen
, width
, height
, fourcc
, fds
,
742 num_fds
, strides
, offsets
,
746 * Invalid parameters and any inconsistencies between are assumed to be
747 * checked by the caller. Therefore besides unsupported formats one can fail
748 * only in allocation.
751 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
755 image
->dma_buf_imported
= true;
756 image
->yuv_color_space
= yuv_color_space
;
757 image
->sample_range
= sample_range
;
758 image
->horizontal_siting
= horizontal_siting
;
759 image
->vertical_siting
= vertical_siting
;
761 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
766 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
768 int width
, height
, offset
, stride
, dri_format
, index
;
769 struct intel_image_format
*f
;
772 if (parent
== NULL
|| parent
->planar_format
== NULL
)
775 f
= parent
->planar_format
;
777 if (plane
>= f
->nplanes
)
780 width
= parent
->width
>> f
->planes
[plane
].width_shift
;
781 height
= parent
->height
>> f
->planes
[plane
].height_shift
;
782 dri_format
= f
->planes
[plane
].dri_format
;
783 index
= f
->planes
[plane
].buffer_index
;
784 offset
= parent
->offsets
[index
];
785 stride
= parent
->strides
[index
];
787 image
= intel_allocate_image(dri_format
, loaderPrivate
);
791 if (offset
+ height
* stride
> parent
->bo
->size
) {
792 _mesa_warning(NULL
, "intel_create_sub_image: subimage out of bounds");
797 image
->bo
= parent
->bo
;
798 drm_intel_bo_reference(parent
->bo
);
800 image
->width
= width
;
801 image
->height
= height
;
802 image
->pitch
= stride
;
803 image
->offset
= offset
;
805 intel_image_warn_if_unaligned(image
, __func__
);
810 static const __DRIimageExtension intelImageExtension
= {
811 .base
= { __DRI_IMAGE
, 11 },
813 .createImageFromName
= intel_create_image_from_name
,
814 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
815 .destroyImage
= intel_destroy_image
,
816 .createImage
= intel_create_image
,
817 .queryImage
= intel_query_image
,
818 .dupImage
= intel_dup_image
,
819 .validateUsage
= intel_validate_usage
,
820 .createImageFromNames
= intel_create_image_from_names
,
821 .fromPlanar
= intel_from_planar
,
822 .createImageFromTexture
= intel_create_image_from_texture
,
823 .createImageFromFds
= intel_create_image_from_fds
,
824 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
,
826 .getCapabilities
= NULL
830 brw_query_renderer_integer(__DRIscreen
*psp
, int param
, unsigned int *value
)
832 const struct intel_screen
*const intelScreen
=
833 (struct intel_screen
*) psp
->driverPrivate
;
836 case __DRI2_RENDERER_VENDOR_ID
:
839 case __DRI2_RENDERER_DEVICE_ID
:
840 value
[0] = intelScreen
->deviceID
;
842 case __DRI2_RENDERER_ACCELERATED
:
845 case __DRI2_RENDERER_VIDEO_MEMORY
: {
846 /* Once a batch uses more than 75% of the maximum mappable size, we
847 * assume that there's some fragmentation, and we start doing extra
848 * flushing, etc. That's the big cliff apps will care about.
851 size_t mappable_size
;
853 drm_intel_get_aperture_sizes(psp
->fd
, &mappable_size
, &aper_size
);
855 const unsigned gpu_mappable_megabytes
=
856 (aper_size
/ (1024 * 1024)) * 3 / 4;
858 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
859 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
861 if (system_memory_pages
<= 0 || system_page_size
<= 0)
864 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
865 * (uint64_t) system_page_size
;
867 const unsigned system_memory_megabytes
=
868 (unsigned) (system_memory_bytes
/ (1024 * 1024));
870 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
873 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
877 return driQueryRendererIntegerCommon(psp
, param
, value
);
884 brw_query_renderer_string(__DRIscreen
*psp
, int param
, const char **value
)
886 const struct intel_screen
*intelScreen
=
887 (struct intel_screen
*) psp
->driverPrivate
;
890 case __DRI2_RENDERER_VENDOR_ID
:
891 value
[0] = brw_vendor_string
;
893 case __DRI2_RENDERER_DEVICE_ID
:
894 value
[0] = brw_get_renderer_string(intelScreen
);
903 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
904 .base
= { __DRI2_RENDERER_QUERY
, 1 },
906 .queryInteger
= brw_query_renderer_integer
,
907 .queryString
= brw_query_renderer_string
910 static const __DRIrobustnessExtension dri2Robustness
= {
911 .base
= { __DRI2_ROBUSTNESS
, 1 }
914 static const __DRIextension
*intelScreenExtensions
[] = {
915 &intelTexBufferExtension
.base
,
916 &intelFenceExtension
.base
,
917 &intelFlushExtension
.base
,
918 &intelImageExtension
.base
,
919 &intelRendererQueryExtension
.base
,
920 &dri2ConfigQueryExtension
.base
,
924 static const __DRIextension
*intelRobustScreenExtensions
[] = {
925 &intelTexBufferExtension
.base
,
926 &intelFenceExtension
.base
,
927 &intelFlushExtension
.base
,
928 &intelImageExtension
.base
,
929 &intelRendererQueryExtension
.base
,
930 &dri2ConfigQueryExtension
.base
,
931 &dri2Robustness
.base
,
936 intel_get_param(__DRIscreen
*psp
, int param
, int *value
)
939 struct drm_i915_getparam gp
;
941 memset(&gp
, 0, sizeof(gp
));
945 ret
= drmCommandWriteRead(psp
->fd
, DRM_I915_GETPARAM
, &gp
, sizeof(gp
));
948 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
956 intel_get_boolean(__DRIscreen
*psp
, int param
)
959 return intel_get_param(psp
, param
, &value
) && value
;
963 intelDestroyScreen(__DRIscreen
* sPriv
)
965 struct intel_screen
*intelScreen
= sPriv
->driverPrivate
;
967 dri_bufmgr_destroy(intelScreen
->bufmgr
);
968 driDestroyOptionInfo(&intelScreen
->optionCache
);
970 ralloc_free(intelScreen
);
971 sPriv
->driverPrivate
= NULL
;
976 * This is called when we need to set up GL rendering to a new X window.
979 intelCreateBuffer(__DRIscreen
* driScrnPriv
,
980 __DRIdrawable
* driDrawPriv
,
981 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
983 struct intel_renderbuffer
*rb
;
984 struct intel_screen
*screen
= (struct intel_screen
*) driScrnPriv
->driverPrivate
;
985 mesa_format rgbFormat
;
986 unsigned num_samples
= intel_quantize_num_samples(screen
, mesaVis
->samples
);
987 struct gl_framebuffer
*fb
;
992 fb
= CALLOC_STRUCT(gl_framebuffer
);
996 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
998 if (screen
->winsys_msaa_samples_override
!= -1) {
999 num_samples
= screen
->winsys_msaa_samples_override
;
1000 fb
->Visual
.samples
= num_samples
;
1003 if (mesaVis
->redBits
== 5) {
1004 rgbFormat
= mesaVis
->redMask
== 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1005 : MESA_FORMAT_B5G6R5_UNORM
;
1006 } else if (mesaVis
->sRGBCapable
) {
1007 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1008 : MESA_FORMAT_B8G8R8A8_SRGB
;
1009 } else if (mesaVis
->alphaBits
== 0) {
1010 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8X8_UNORM
1011 : MESA_FORMAT_B8G8R8X8_UNORM
;
1013 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1014 : MESA_FORMAT_B8G8R8A8_SRGB
;
1015 fb
->Visual
.sRGBCapable
= true;
1018 /* setup the hardware-based renderbuffers */
1019 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
1020 _mesa_add_renderbuffer(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
1022 if (mesaVis
->doubleBufferMode
) {
1023 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
1024 _mesa_add_renderbuffer(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1028 * Assert here that the gl_config has an expected depth/stencil bit
1029 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1030 * which constructs the advertised configs.)
1032 if (mesaVis
->depthBits
== 24) {
1033 assert(mesaVis
->stencilBits
== 8);
1035 if (screen
->devinfo
->has_hiz_and_separate_stencil
) {
1036 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_X8_UINT
,
1038 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1039 rb
= intel_create_private_renderbuffer(MESA_FORMAT_S_UINT8
,
1041 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1044 * Use combined depth/stencil. Note that the renderbuffer is
1045 * attached to two attachment points.
1047 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_S8_UINT
,
1049 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1050 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1053 else if (mesaVis
->depthBits
== 16) {
1054 assert(mesaVis
->stencilBits
== 0);
1055 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z_UNORM16
,
1057 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1060 assert(mesaVis
->depthBits
== 0);
1061 assert(mesaVis
->stencilBits
== 0);
1064 /* now add any/all software-based renderbuffers we may need */
1065 _swrast_add_soft_renderbuffers(fb
,
1066 false, /* never sw color */
1067 false, /* never sw depth */
1068 false, /* never sw stencil */
1069 mesaVis
->accumRedBits
> 0,
1070 false, /* never sw alpha */
1071 false /* never sw aux */ );
1072 driDrawPriv
->driverPrivate
= fb
;
1078 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1080 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1082 _mesa_reference_framebuffer(&fb
, NULL
);
1086 intel_detect_sseu(struct intel_screen
*intelScreen
)
1088 assert(intelScreen
->devinfo
->gen
>= 8);
1091 intelScreen
->subslice_total
= -1;
1092 intelScreen
->eu_total
= -1;
1094 ret
= intel_get_param(intelScreen
->driScrnPriv
, I915_PARAM_SUBSLICE_TOTAL
,
1095 &intelScreen
->subslice_total
);
1099 ret
= intel_get_param(intelScreen
->driScrnPriv
,
1100 I915_PARAM_EU_TOTAL
, &intelScreen
->eu_total
);
1104 /* Without this information, we cannot get the right Braswell brandstrings,
1105 * and we have to use conservative numbers for GPGPU on many platforms, but
1106 * otherwise, things will just work.
1108 if (intelScreen
->subslice_total
< 1 || intelScreen
->eu_total
< 1)
1110 "Kernel 4.1 required to properly query GPU properties.\n");
1115 intelScreen
->subslice_total
= -1;
1116 intelScreen
->eu_total
= -1;
1117 _mesa_warning(NULL
, "Failed to query GPU properties.\n");
1121 intel_init_bufmgr(struct intel_screen
*intelScreen
)
1123 __DRIscreen
*spriv
= intelScreen
->driScrnPriv
;
1125 intelScreen
->no_hw
= getenv("INTEL_NO_HW") != NULL
;
1127 intelScreen
->bufmgr
= intel_bufmgr_gem_init(spriv
->fd
, BATCH_SZ
);
1128 if (intelScreen
->bufmgr
== NULL
) {
1129 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1130 __func__
, __LINE__
);
1134 drm_intel_bufmgr_gem_enable_fenced_relocs(intelScreen
->bufmgr
);
1136 if (!intel_get_boolean(spriv
, I915_PARAM_HAS_RELAXED_DELTA
)) {
1137 fprintf(stderr
, "[%s: %u] Kernel 2.6.39 required.\n", __func__
, __LINE__
);
1145 intel_detect_swizzling(struct intel_screen
*screen
)
1147 drm_intel_bo
*buffer
;
1148 unsigned long flags
= 0;
1149 unsigned long aligned_pitch
;
1150 uint32_t tiling
= I915_TILING_X
;
1151 uint32_t swizzle_mode
= 0;
1153 buffer
= drm_intel_bo_alloc_tiled(screen
->bufmgr
, "swizzle test",
1155 &tiling
, &aligned_pitch
, flags
);
1159 drm_intel_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1160 drm_intel_bo_unreference(buffer
);
1162 if (swizzle_mode
== I915_BIT_6_SWIZZLE_NONE
)
1169 intel_detect_timestamp(struct intel_screen
*screen
)
1171 uint64_t dummy
= 0, last
= 0;
1172 int upper
, lower
, loops
;
1174 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1175 * TIMESTAMP register being shifted and the low 32bits always zero.
1177 * More recent kernels offer an interface to read the full 36bits
1180 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &dummy
) == 0)
1183 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1184 * upper 32bits for a rapidly changing timestamp.
1186 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
, &last
))
1190 for (loops
= 0; loops
< 10; loops
++) {
1191 /* The TIMESTAMP should change every 80ns, so several round trips
1192 * through the kernel should be enough to advance it.
1194 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
, &dummy
))
1197 upper
+= (dummy
>> 32) != (last
>> 32);
1198 if (upper
> 1) /* beware 32bit counter overflow */
1199 return 2; /* upper dword holds the low 32bits of the timestamp */
1201 lower
+= (dummy
& 0xffffffff) != (last
& 0xffffffff);
1203 return 1; /* timestamp is unshifted */
1208 /* No advancement? No timestamp! */
1213 * Return array of MSAA modes supported by the hardware. The array is
1214 * zero-terminated and sorted in decreasing order.
1217 intel_supported_msaa_modes(const struct intel_screen
*screen
)
1219 static const int gen9_modes
[] = {16, 8, 4, 2, 0, -1};
1220 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
1221 static const int gen7_modes
[] = {8, 4, 0, -1};
1222 static const int gen6_modes
[] = {4, 0, -1};
1223 static const int gen4_modes
[] = {0, -1};
1225 if (screen
->devinfo
->gen
>= 9) {
1227 } else if (screen
->devinfo
->gen
>= 8) {
1229 } else if (screen
->devinfo
->gen
>= 7) {
1231 } else if (screen
->devinfo
->gen
== 6) {
1238 static __DRIconfig
**
1239 intel_screen_make_configs(__DRIscreen
*dri_screen
)
1241 static const mesa_format formats
[] = {
1242 MESA_FORMAT_B5G6R5_UNORM
,
1243 MESA_FORMAT_B8G8R8A8_UNORM
,
1244 MESA_FORMAT_B8G8R8X8_UNORM
1247 /* GLX_SWAP_COPY_OML is not supported due to page flipping. */
1248 static const GLenum back_buffer_modes
[] = {
1249 GLX_SWAP_UNDEFINED_OML
, GLX_NONE
,
1252 static const uint8_t singlesample_samples
[1] = {0};
1253 static const uint8_t multisample_samples
[2] = {4, 8};
1255 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1256 const struct brw_device_info
*devinfo
= screen
->devinfo
;
1257 uint8_t depth_bits
[4], stencil_bits
[4];
1258 __DRIconfig
**configs
= NULL
;
1260 /* Generate singlesample configs without accumulation buffer. */
1261 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1262 __DRIconfig
**new_configs
;
1263 int num_depth_stencil_bits
= 2;
1265 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
1266 * buffer that has a different number of bits per pixel than the color
1267 * buffer, gen >= 6 supports this.
1270 stencil_bits
[0] = 0;
1272 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1274 stencil_bits
[1] = 0;
1275 if (devinfo
->gen
>= 6) {
1277 stencil_bits
[2] = 8;
1278 num_depth_stencil_bits
= 3;
1282 stencil_bits
[1] = 8;
1285 new_configs
= driCreateConfigs(formats
[i
],
1288 num_depth_stencil_bits
,
1289 back_buffer_modes
, 2,
1290 singlesample_samples
, 1,
1292 configs
= driConcatConfigs(configs
, new_configs
);
1295 /* Generate the minimum possible set of configs that include an
1296 * accumulation buffer.
1298 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1299 __DRIconfig
**new_configs
;
1301 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1303 stencil_bits
[0] = 0;
1306 stencil_bits
[0] = 8;
1309 new_configs
= driCreateConfigs(formats
[i
],
1310 depth_bits
, stencil_bits
, 1,
1311 back_buffer_modes
, 1,
1312 singlesample_samples
, 1,
1314 configs
= driConcatConfigs(configs
, new_configs
);
1317 /* Generate multisample configs.
1319 * This loop breaks early, and hence is a no-op, on gen < 6.
1321 * Multisample configs must follow the singlesample configs in order to
1322 * work around an X server bug present in 1.12. The X server chooses to
1323 * associate the first listed RGBA888-Z24S8 config, regardless of its
1324 * sample count, with the 32-bit depth visual used for compositing.
1326 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
1327 * supported. Singlebuffer configs are not supported because no one wants
1330 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1331 if (devinfo
->gen
< 6)
1334 __DRIconfig
**new_configs
;
1335 const int num_depth_stencil_bits
= 2;
1336 int num_msaa_modes
= 0;
1339 stencil_bits
[0] = 0;
1341 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1343 stencil_bits
[1] = 0;
1346 stencil_bits
[1] = 8;
1349 if (devinfo
->gen
>= 7)
1351 else if (devinfo
->gen
== 6)
1354 new_configs
= driCreateConfigs(formats
[i
],
1357 num_depth_stencil_bits
,
1358 back_buffer_modes
, 1,
1359 multisample_samples
,
1362 configs
= driConcatConfigs(configs
, new_configs
);
1365 if (configs
== NULL
) {
1366 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
1375 set_max_gl_versions(struct intel_screen
*screen
)
1377 __DRIscreen
*psp
= screen
->driScrnPriv
;
1379 switch (screen
->devinfo
->gen
) {
1382 psp
->max_gl_core_version
= 33;
1383 psp
->max_gl_compat_version
= 30;
1384 psp
->max_gl_es1_version
= 11;
1385 psp
->max_gl_es2_version
= 31;
1389 psp
->max_gl_core_version
= 33;
1390 psp
->max_gl_compat_version
= 30;
1391 psp
->max_gl_es1_version
= 11;
1392 psp
->max_gl_es2_version
= 30;
1396 psp
->max_gl_core_version
= 0;
1397 psp
->max_gl_compat_version
= 21;
1398 psp
->max_gl_es1_version
= 11;
1399 psp
->max_gl_es2_version
= 20;
1402 unreachable("unrecognized intel_screen::gen");
1407 * Return the revision (generally the revid field of the PCI header) of the
1410 * XXX: This function is useful to keep around even if it is not currently in
1411 * use. It is necessary for new platforms and revision specific workarounds or
1412 * features. Please don't remove it so that we know it at least continues to
1415 static __attribute__((__unused__
)) int
1416 brw_get_revision(int fd
)
1418 struct drm_i915_getparam gp
;
1422 memset(&gp
, 0, sizeof(gp
));
1423 gp
.param
= I915_PARAM_REVISION
;
1424 gp
.value
= &revision
;
1426 ret
= drmCommandWriteRead(fd
, DRM_I915_GETPARAM
, &gp
, sizeof(gp
));
1433 /* Drop when RS headers get pulled to libdrm */
1434 #ifndef I915_PARAM_HAS_RESOURCE_STREAMER
1435 #define I915_PARAM_HAS_RESOURCE_STREAMER 36
1439 * This is the driver specific part of the createNewScreen entry point.
1440 * Called when using DRI2.
1442 * \return the struct gl_config supported by this driver
1445 __DRIconfig
**intelInitScreen2(__DRIscreen
*psp
)
1447 struct intel_screen
*intelScreen
;
1449 if (psp
->image
.loader
) {
1450 } else if (psp
->dri2
.loader
->base
.version
<= 2 ||
1451 psp
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
1453 "\nERROR! DRI2 loader with getBuffersWithFormat() "
1454 "support required\n");
1458 /* Allocate the private area */
1459 intelScreen
= rzalloc(NULL
, struct intel_screen
);
1461 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
1464 /* parse information in __driConfigOptions */
1465 driParseOptionInfo(&intelScreen
->optionCache
, brw_config_options
.xml
);
1467 intelScreen
->driScrnPriv
= psp
;
1468 psp
->driverPrivate
= (void *) intelScreen
;
1470 if (!intel_init_bufmgr(intelScreen
))
1473 intelScreen
->deviceID
= drm_intel_bufmgr_gem_get_devid(intelScreen
->bufmgr
);
1474 intelScreen
->devinfo
= brw_get_device_info(intelScreen
->deviceID
);
1475 if (!intelScreen
->devinfo
)
1478 brw_process_intel_debug_variable();
1480 if (INTEL_DEBUG
& DEBUG_BUFMGR
)
1481 dri_bufmgr_set_debug(intelScreen
->bufmgr
, true);
1483 if ((INTEL_DEBUG
& DEBUG_SHADER_TIME
) && intelScreen
->devinfo
->gen
< 7) {
1485 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
1486 INTEL_DEBUG
&= ~DEBUG_SHADER_TIME
;
1489 if (INTEL_DEBUG
& DEBUG_AUB
)
1490 drm_intel_bufmgr_gem_set_aub_dump(intelScreen
->bufmgr
, true);
1492 intelScreen
->hw_has_swizzling
= intel_detect_swizzling(intelScreen
);
1493 intelScreen
->hw_has_timestamp
= intel_detect_timestamp(intelScreen
);
1495 /* GENs prior to 8 do not support EU/Subslice info */
1496 if (intelScreen
->devinfo
->gen
>= 8)
1497 intel_detect_sseu(intelScreen
);
1499 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
1501 intelScreen
->winsys_msaa_samples_override
=
1502 intel_quantize_num_samples(intelScreen
, atoi(force_msaa
));
1503 printf("Forcing winsys sample count to %d\n",
1504 intelScreen
->winsys_msaa_samples_override
);
1506 intelScreen
->winsys_msaa_samples_override
= -1;
1509 set_max_gl_versions(intelScreen
);
1511 /* Notification of GPU resets requires hardware contexts and a kernel new
1512 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
1513 * supported, calling it with a context of 0 will either generate EPERM or
1514 * no error. If the ioctl is not supported, it always generate EINVAL.
1515 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
1516 * extension to the loader.
1518 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
1520 if (intelScreen
->devinfo
->gen
>= 6) {
1521 struct drm_i915_reset_stats stats
;
1522 memset(&stats
, 0, sizeof(stats
));
1524 const int ret
= drmIoctl(psp
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
1526 intelScreen
->has_context_reset_notification
=
1527 (ret
!= -1 || errno
!= EINVAL
);
1530 struct drm_i915_getparam getparam
;
1531 getparam
.param
= I915_PARAM_CMD_PARSER_VERSION
;
1532 getparam
.value
= &intelScreen
->cmd_parser_version
;
1533 const int ret
= drmIoctl(psp
->fd
, DRM_IOCTL_I915_GETPARAM
, &getparam
);
1535 intelScreen
->cmd_parser_version
= 0;
1537 psp
->extensions
= !intelScreen
->has_context_reset_notification
1538 ? intelScreenExtensions
: intelRobustScreenExtensions
;
1540 intelScreen
->compiler
= brw_compiler_create(intelScreen
,
1541 intelScreen
->devinfo
);
1542 intelScreen
->program_id
= 1;
1544 if (intelScreen
->devinfo
->has_resource_streamer
) {
1546 getparam
.param
= I915_PARAM_HAS_RESOURCE_STREAMER
;
1547 getparam
.value
= &val
;
1549 drmIoctl(psp
->fd
, DRM_IOCTL_I915_GETPARAM
, &getparam
);
1550 intelScreen
->has_resource_streamer
= val
> 0;
1553 return (const __DRIconfig
**) intel_screen_make_configs(psp
);
1556 struct intel_buffer
{
1561 static __DRIbuffer
*
1562 intelAllocateBuffer(__DRIscreen
*screen
,
1563 unsigned attachment
, unsigned format
,
1564 int width
, int height
)
1566 struct intel_buffer
*intelBuffer
;
1567 struct intel_screen
*intelScreen
= screen
->driverPrivate
;
1569 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
1570 attachment
== __DRI_BUFFER_BACK_LEFT
);
1572 intelBuffer
= calloc(1, sizeof *intelBuffer
);
1573 if (intelBuffer
== NULL
)
1576 /* The front and back buffers are color buffers, which are X tiled. */
1577 uint32_t tiling
= I915_TILING_X
;
1578 unsigned long pitch
;
1579 int cpp
= format
/ 8;
1580 intelBuffer
->bo
= drm_intel_bo_alloc_tiled(intelScreen
->bufmgr
,
1581 "intelAllocateBuffer",
1586 BO_ALLOC_FOR_RENDER
);
1588 if (intelBuffer
->bo
== NULL
) {
1593 drm_intel_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
1595 intelBuffer
->base
.attachment
= attachment
;
1596 intelBuffer
->base
.cpp
= cpp
;
1597 intelBuffer
->base
.pitch
= pitch
;
1599 return &intelBuffer
->base
;
1603 intelReleaseBuffer(__DRIscreen
*screen
, __DRIbuffer
*buffer
)
1605 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
1607 drm_intel_bo_unreference(intelBuffer
->bo
);
1611 static const struct __DriverAPIRec brw_driver_api
= {
1612 .InitScreen
= intelInitScreen2
,
1613 .DestroyScreen
= intelDestroyScreen
,
1614 .CreateContext
= brwCreateContext
,
1615 .DestroyContext
= intelDestroyContext
,
1616 .CreateBuffer
= intelCreateBuffer
,
1617 .DestroyBuffer
= intelDestroyBuffer
,
1618 .MakeCurrent
= intelMakeCurrent
,
1619 .UnbindContext
= intelUnbindContext
,
1620 .AllocateBuffer
= intelAllocateBuffer
,
1621 .ReleaseBuffer
= intelReleaseBuffer
1624 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
1625 .base
= { __DRI_DRIVER_VTABLE
, 1 },
1626 .vtable
= &brw_driver_api
,
1629 static const __DRIextension
*brw_driver_extensions
[] = {
1630 &driCoreExtension
.base
,
1631 &driImageDriverExtension
.base
,
1632 &driDRI2Extension
.base
,
1634 &brw_config_options
.base
,
1638 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
1640 globalDriverAPI
= &brw_driver_api
;
1642 return brw_driver_extensions
;