1 /**************************************************************************
3 * Copyright 2003 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
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23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #ifndef _INTEL_INIT_H_
29 #define _INTEL_INIT_H_
34 #include "intel_bufmgr.h"
35 #include "brw_device_info.h"
37 #include "xmlconfig.h"
42 const struct brw_device_info
*devinfo
;
44 __DRIscreen
*driScrnPriv
;
48 bool hw_must_use_separate_stencil
;
50 bool hw_has_swizzling
;
53 * Does the kernel support context reset notifications?
55 bool has_context_reset_notification
;
60 * A unique ID for shader programs.
64 int winsys_msaa_samples_override
;
70 * Array of the ra classes for the unaligned contiguous register
76 * Mapping for register-allocated objects in *regs to the first
77 * GRF for that object.
79 uint8_t *ra_reg_to_grf
;
86 * Array of the ra classes for the unaligned contiguous register
87 * block sizes used, indexed by register size.
92 * Mapping from classes to ra_reg ranges. Each of the per-size
93 * classes corresponds to a range of ra_reg nodes. This array stores
94 * those ranges in the form of first ra_reg in each class and the
95 * total number of ra_reg elements in the last array element. This
96 * way the range of the i'th class is given by:
97 * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
99 int class_to_ra_reg_range
[17];
102 * Mapping for register-allocated objects in *regs to the first
103 * GRF for that object.
105 uint8_t *ra_reg_to_grf
;
108 * ra class for the aligned pairs we use for PLN, which doesn't
109 * appear in *classes.
111 int aligned_pairs_class
;
115 * Configuration cache with default values for all contexts
117 driOptionCache optionCache
;
120 extern void intelDestroyContext(__DRIcontext
* driContextPriv
);
122 extern GLboolean
intelUnbindContext(__DRIcontext
* driContextPriv
);
124 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void);
127 intelMakeCurrent(__DRIcontext
* driContextPriv
,
128 __DRIdrawable
* driDrawPriv
,
129 __DRIdrawable
* driReadPriv
);
131 double get_time(void);
132 void aub_dump_bmp(struct gl_context
*ctx
);
135 intel_supported_msaa_modes(const struct intel_screen
*screen
);