src/mesa/drivers/dri/i965/intel_screen.h

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 VMware, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
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  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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  25  *
  26  **************************************************************************/
  27
  28 #ifndef _INTEL_INIT_H_
  29 #define _INTEL_INIT_H_
  30
  31 #include <stdbool.h>
  32 #include <sys/time.h>
  33 #include "dri_util.h"
  34 #include "intel_bufmgr.h"
  35 #include "intel_chipset.h"
  36 #include "brw_device_info.h"
  37 #include "i915_drm.h"
  38 #include "xmlconfig.h"
  39
  40 struct intel_screen
  41 {
  42    int deviceID;
  43    const struct brw_device_info *devinfo;
  44
  45    __DRIscreen *driScrnPriv;
  46
  47    bool no_hw;
  48
  49    bool hw_must_use_separate_stencil;
  50
  51    bool hw_has_swizzling;
  52
  53    /**
  54     * Does the kernel support context reset notifications?
  55     */
  56    bool has_context_reset_notification;
  57
  58    dri_bufmgr *bufmgr;
  59
  60    /**
  61     * A unique ID for shader programs.
  62     */
  63    unsigned program_id;
  64
  65    int winsys_msaa_samples_override;
  66
  67    struct {
  68       struct ra_regs *regs;
  69
  70       /**
  71        * Array of the ra classes for the unaligned contiguous register
  72        * block sizes used.
  73        */
  74       int *classes;
  75
  76       /**
  77        * Mapping for register-allocated objects in *regs to the first
  78        * GRF for that object.
  79        */
  80       uint8_t *ra_reg_to_grf;
  81    } vec4_reg_set;
  82
  83    struct {
  84       struct ra_regs *regs;
  85
  86       /**
  87        * Array of the ra classes for the unaligned contiguous register
  88        * block sizes used, indexed by register size.
  89        */
  90       int classes[16];
  91
  92       /**
  93        * Mapping for register-allocated objects in *regs to the first
  94        * GRF for that object.
  95        */
  96       uint8_t *ra_reg_to_grf;
  97
  98       /**
  99        * ra class for the aligned pairs we use for PLN, which doesn't
 100        * appear in *classes.
 101        */
 102       int aligned_pairs_class;
 103    } wm_reg_sets[2];
 104
 105    /**
 106    * Configuration cache with default values for all contexts
 107    */
 108    driOptionCache optionCache;
 109 };
 110
 111 extern void intelDestroyContext(__DRIcontext * driContextPriv);
 112
 113 extern GLboolean intelUnbindContext(__DRIcontext * driContextPriv);
 114
 115 PUBLIC const __DRIextension **__driDriverGetExtensions_i965(void);
 116
 117 extern GLboolean
 118 intelMakeCurrent(__DRIcontext * driContextPriv,
 119                  __DRIdrawable * driDrawPriv,
 120                  __DRIdrawable * driReadPriv);
 121
 122 double get_time(void);
 123 void aub_dump_bmp(struct gl_context *ctx);
 124
 125 const int*
 126 intel_supported_msaa_modes(const struct intel_screen  *screen);
 127
 128 #endif