src/mesa/drivers/dri/i965/intel_screen.h

   1 /*
   2  * Copyright 2003 VMware, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial portions
  15  * of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #ifndef _INTEL_INIT_H_
  27 #define _INTEL_INIT_H_
  28
  29 #include <stdbool.h>
  30 #include <sys/time.h>
  31
  32 #include <GL/internal/dri_interface.h>
  33
  34 #include "dri_util.h"
  35 #include "intel_bufmgr.h"
  36 #include "common/gen_device_info.h"
  37 #include "i915_drm.h"
  38 #include "xmlconfig.h"
  39
  40 struct intel_screen
  41 {
  42    int deviceID;
  43    struct gen_device_info devinfo;
  44
  45    __DRIscreen *driScrnPriv;
  46
  47    uint64_t max_gtt_map_object_size;
  48
  49    bool no_hw;
  50
  51    bool hw_has_swizzling;
  52
  53    int hw_has_timestamp;
  54
  55    /**
  56     * Does the kernel support resource streamer?
  57     */
  58    bool has_resource_streamer;
  59
  60    /**
  61     * Does the current hardware and kernel support MI_MATH and
  62     * MI_LOAD_REGISTER_REG?
  63     */
  64    bool has_mi_math_and_lrr;
  65
  66    /**
  67     * Does the kernel support context reset notifications?
  68     */
  69    bool has_context_reset_notification;
  70
  71    /**
  72     * Does the kernel support pipelined register access?
  73     * Due to whitelisting we need to do seperate checks
  74     * for each register.
  75     */
  76    unsigned hw_has_pipelined_register;
  77 #define HW_HAS_PIPELINED_SOL_OFFSET (1<<0)
  78
  79    dri_bufmgr *bufmgr;
  80
  81    /**
  82     * A unique ID for shader programs.
  83     */
  84    unsigned program_id;
  85
  86    int winsys_msaa_samples_override;
  87
  88    struct brw_compiler *compiler;
  89
  90    /**
  91    * Configuration cache with default values for all contexts
  92    */
  93    driOptionCache optionCache;
  94
  95    /**
  96     * Version of the command parser reported by the
  97     * I915_PARAM_CMD_PARSER_VERSION parameter
  98     */
  99    int cmd_parser_version;
 100
 101    /**
 102     * Number of subslices reported by the I915_PARAM_SUBSLICE_TOTAL parameter
 103     */
 104    int subslice_total;
 105
 106    /**
 107     * Number of EUs reported by the I915_PARAM_EU_TOTAL parameter
 108     */
 109    int eu_total;
 110 };
 111
 112 extern void intelDestroyContext(__DRIcontext * driContextPriv);
 113
 114 extern GLboolean intelUnbindContext(__DRIcontext * driContextPriv);
 115
 116 PUBLIC const __DRIextension **__driDriverGetExtensions_i965(void);
 117 extern const __DRI2fenceExtension intelFenceExtension;
 118
 119 extern GLboolean
 120 intelMakeCurrent(__DRIcontext * driContextPriv,
 121                  __DRIdrawable * driDrawPriv,
 122                  __DRIdrawable * driReadPriv);
 123
 124 double get_time(void);
 125 void aub_dump_bmp(struct gl_context *ctx);
 126
 127 const int*
 128 intel_supported_msaa_modes(const struct intel_screen  *screen);
 129
 130 static inline bool
 131 can_do_pipelined_register_writes(const struct intel_screen *screen)
 132 {
 133    return screen->hw_has_pipelined_register & HW_HAS_PIPELINED_SOL_OFFSET;
 134 }
 135
 136 #endif