i965/fs: Use the GRF for FB writes on gen >= 7
[mesa.git] / src / mesa / drivers / dri / i965 / intel_screen.h
1 /**************************************************************************
2 *
3 * Copyright 2003 VMware, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
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11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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27
28 #ifndef _INTEL_INIT_H_
29 #define _INTEL_INIT_H_
30
31 #include <stdbool.h>
32 #include <sys/time.h>
33 #include "dri_util.h"
34 #include "intel_bufmgr.h"
35 #include "brw_device_info.h"
36 #include "i915_drm.h"
37 #include "xmlconfig.h"
38
39 struct intel_screen
40 {
41 int deviceID;
42 const struct brw_device_info *devinfo;
43
44 __DRIscreen *driScrnPriv;
45
46 bool no_hw;
47
48 bool hw_must_use_separate_stencil;
49
50 bool hw_has_swizzling;
51
52 /**
53 * Does the kernel support context reset notifications?
54 */
55 bool has_context_reset_notification;
56
57 dri_bufmgr *bufmgr;
58
59 /**
60 * A unique ID for shader programs.
61 */
62 unsigned program_id;
63
64 int winsys_msaa_samples_override;
65
66 struct {
67 struct ra_regs *regs;
68
69 /**
70 * Array of the ra classes for the unaligned contiguous register
71 * block sizes used.
72 */
73 int *classes;
74
75 /**
76 * Mapping for register-allocated objects in *regs to the first
77 * GRF for that object.
78 */
79 uint8_t *ra_reg_to_grf;
80 } vec4_reg_set;
81
82 struct {
83 struct ra_regs *regs;
84
85 /**
86 * Array of the ra classes for the unaligned contiguous register
87 * block sizes used, indexed by register size.
88 */
89 int classes[16];
90
91 /**
92 * Mapping from classes to ra_reg ranges. Each of the per-size
93 * classes corresponds to a range of ra_reg nodes. This array stores
94 * those ranges in the form of first ra_reg in each class and the
95 * total number of ra_reg elements in the last array element. This
96 * way the range of the i'th class is given by:
97 * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
98 */
99 int class_to_ra_reg_range[17];
100
101 /**
102 * Mapping for register-allocated objects in *regs to the first
103 * GRF for that object.
104 */
105 uint8_t *ra_reg_to_grf;
106
107 /**
108 * ra class for the aligned pairs we use for PLN, which doesn't
109 * appear in *classes.
110 */
111 int aligned_pairs_class;
112 } wm_reg_sets[2];
113
114 /**
115 * Configuration cache with default values for all contexts
116 */
117 driOptionCache optionCache;
118 };
119
120 extern void intelDestroyContext(__DRIcontext * driContextPriv);
121
122 extern GLboolean intelUnbindContext(__DRIcontext * driContextPriv);
123
124 PUBLIC const __DRIextension **__driDriverGetExtensions_i965(void);
125
126 extern GLboolean
127 intelMakeCurrent(__DRIcontext * driContextPriv,
128 __DRIdrawable * driDrawPriv,
129 __DRIdrawable * driReadPriv);
130
131 double get_time(void);
132 void aub_dump_bmp(struct gl_context *ctx);
133
134 const int*
135 intel_supported_msaa_modes(const struct intel_screen *screen);
136
137 #endif