4 #include "xf86drm.h" /* drm_handle_t, etc */
8 #define PCI_CHIP_I810 0x7121
9 #define PCI_CHIP_I810_DC100 0x7123
10 #define PCI_CHIP_I810_E 0x7125
11 #define PCI_CHIP_I815 0x1132
12 #define PCI_CHIP_I810_BRIDGE 0x7120
13 #define PCI_CHIP_I810_DC100_BRIDGE 0x7122
14 #define PCI_CHIP_I810_E_BRIDGE 0x7124
15 #define PCI_CHIP_I815_BRIDGE 0x1130
18 #define PCI_CHIP_845_G 0x2562
19 #define PCI_CHIP_I830_M 0x3577
21 #ifndef PCI_CHIP_I855_GM
22 #define PCI_CHIP_I855_GM 0x3582
23 #define PCI_CHIP_I855_GM_BRIDGE 0x3580
26 #ifndef PCI_CHIP_I865_G
27 #define PCI_CHIP_I865_G 0x2572
28 #define PCI_CHIP_I865_G_BRIDGE 0x2570
31 #ifndef PCI_CHIP_I915_G
32 #define PCI_CHIP_I915_G 0x2582
33 #define PCI_CHIP_I915_G_BRIDGE 0x2580
36 #ifndef PCI_CHIP_I915_GM
37 #define PCI_CHIP_I915_GM 0x2592
38 #define PCI_CHIP_I915_GM_BRIDGE 0x2590
41 #ifndef PCI_CHIP_E7221_G
42 #define PCI_CHIP_E7221_G 0x258A
43 /* Same as I915_G_BRIDGE */
44 #define PCI_CHIP_E7221_G_BRIDGE 0x2580
47 #ifndef PCI_CHIP_I945_G
48 #define PCI_CHIP_I945_G 0x2772
49 #define PCI_CHIP_I945_G_BRIDGE 0x2770
52 #ifndef PCI_CHIP_I945_GM
53 #define PCI_CHIP_I945_GM 0x27A2
54 #define PCI_CHIP_I945_GM_BRIDGE 0x27A0
57 #define IS_I810(pI810) (pI810->Chipset == PCI_CHIP_I810 || \
58 pI810->Chipset == PCI_CHIP_I810_DC100 || \
59 pI810->Chipset == PCI_CHIP_I810_E)
60 #define IS_I815(pI810) (pI810->Chipset == PCI_CHIP_I815)
61 #define IS_I830(pI810) (pI810->Chipset == PCI_CHIP_I830_M)
62 #define IS_845G(pI810) (pI810->Chipset == PCI_CHIP_845_G)
63 #define IS_I85X(pI810) (pI810->Chipset == PCI_CHIP_I855_GM)
64 #define IS_I852(pI810) (pI810->Chipset == PCI_CHIP_I855_GM && (pI810->variant == I852_GM || pI810->variant == I852_GME))
65 #define IS_I855(pI810) (pI810->Chipset == PCI_CHIP_I855_GM && (pI810->variant == I855_GM || pI810->variant == I855_GME))
66 #define IS_I865G(pI810) (pI810->Chipset == PCI_CHIP_I865_G)
68 #define IS_I915G(pI810) (pI810->Chipset == PCI_CHIP_I915_G || pI810->Chipset == PCI_CHIP_E7221_G)
69 #define IS_I915GM(pI810) (pI810->Chipset == PCI_CHIP_I915_GM)
70 #define IS_I945G(pI810) (pI810->Chipset == PCI_CHIP_I945_G)
71 #define IS_I945GM(pI810) (pI810->Chipset == PCI_CHIP_I945_GM)
72 #define IS_I9XX(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810))
74 #define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810))
76 #define I830_GMCH_CTRL 0x52
79 #define I830_GMCH_GMS_MASK 0x70
80 #define I830_GMCH_GMS_DISABLED 0x00
81 #define I830_GMCH_GMS_LOCAL 0x10
82 #define I830_GMCH_GMS_STOLEN_512 0x20
83 #define I830_GMCH_GMS_STOLEN_1024 0x30
84 #define I830_GMCH_GMS_STOLEN_8192 0x40
86 #define I855_GMCH_GMS_MASK (0x7 << 4)
87 #define I855_GMCH_GMS_DISABLED 0x00
88 #define I855_GMCH_GMS_STOLEN_1M (0x1 << 4)
89 #define I855_GMCH_GMS_STOLEN_4M (0x2 << 4)
90 #define I855_GMCH_GMS_STOLEN_8M (0x3 << 4)
91 #define I855_GMCH_GMS_STOLEN_16M (0x4 << 4)
92 #define I855_GMCH_GMS_STOLEN_32M (0x5 << 4)
93 #define I915G_GMCH_GMS_STOLEN_48M (0x6 << 4)
94 #define I915G_GMCH_GMS_STOLEN_64M (0x7 << 4)
96 typedef unsigned char Bool
;
100 #define PIPE_NONE 0<<0
101 #define PIPE_CRT 1<<0
103 #define PIPE_DFP 1<<2
104 #define PIPE_LFP 1<<3
105 #define PIPE_CRT2 1<<4
106 #define PIPE_TV2 1<<5
107 #define PIPE_DFP2 1<<6
108 #define PIPE_LFP2 1<<7
110 typedef struct _I830MemPool
*I830MemPoolPtr
;
111 typedef struct _I830MemRange
*I830MemRangePtr
;
112 typedef struct _I830MemRange
{
116 unsigned long Physical
;
117 unsigned long Offset
; /* Offset of AGP-allocated portion */
118 unsigned long Alignment
;
120 unsigned long Pitch
; // add pitch
124 typedef struct _I830MemPool
{
128 I830MemRange Allocated
;
134 unsigned char *virtual_start
;
140 typedef struct _I830Rec
{
141 unsigned char *MMIOBase
;
142 unsigned char *FbBase
;
145 unsigned int bios_version
;
147 /* These are set in PreInit and never changed. */
150 I830MemRange StolenMemory
; /* pre-allocated memory */
151 long BIOSMemorySize
; /* min stolen pool size */
154 /* These change according to what has been allocated. */
156 I830MemRange MemoryAperture
;
157 I830MemPool StolenPool
;
158 long allocatedMemory
;
160 /* Regions allocated either from the above pools, or from agpgart. */
161 /* for single and dual head configurations */
162 I830MemRange FrontBuffer
;
163 I830MemRange FrontBuffer2
;
164 I830MemRange Scratch
;
165 I830MemRange Scratch2
;
167 I830RingBuffer
*LpRing
;
169 I830MemRange BackBuffer
;
170 I830MemRange DepthBuffer
;
173 I830MemRange ContextMem
;
177 Bool NeedRingBufferLow
;
182 unsigned long LinearAddr
;
183 unsigned long MMIOAddr
;
185 drmSize registerSize
; /**< \brief MMIO register map size */
186 drm_handle_t registerHandle
; /**< \brief MMIO register map handle */
188 int irq
; /**< \brief IRQ number */
191 drm_handle_t ring_map
;
192 unsigned int Fence
[8];
197 * 12288 is set as the maximum, chosen because it is enough for
198 * 1920x1440@32bpp with a 2048 pixel line pitch with some to spare.
200 #define I830_MAXIMUM_VBIOS_MEM 12288
201 #define I830_DEFAULT_VIDEOMEM_2D (MB(32) / 1024)
202 #define I830_DEFAULT_VIDEOMEM_3D (MB(64) / 1024)
204 /* Flags for memory allocation function */
205 #define FROM_ANYWHERE 0x00000000
206 #define FROM_POOL_ONLY 0x00000001
207 #define FROM_NEW_ONLY 0x00000002
208 #define FROM_MASK 0x0000000f
210 #define ALLOCATE_AT_TOP 0x00000010
211 #define ALLOCATE_AT_BOTTOM 0x00000020
212 #define FORCE_GAPS 0x00000040
214 #define NEED_PHYSICAL_ADDR 0x00000100
215 #define ALIGN_BOTH_ENDS 0x00000200
216 #define FORCE_LOW 0x00000400
218 #define ALLOC_NO_TILING 0x00001000
219 #define ALLOC_INITIAL 0x00002000
221 #define ALLOCATE_DRY_RUN 0x80000000
223 /* Chipset registers for VIDEO BIOS memory RW access */
224 #define _855_DRAM_RW_CONTROL 0x58
225 #define _845_DRAM_RW_CONTROL 0x90
226 #define DRAM_WRITE 0x33330000
228 #define KB(x) ((x) * 1024)
229 #define MB(x) ((x) * KB(1024))
231 #define GTT_PAGE_SIZE KB(4)
232 #define ROUND_TO(x, y) (((x) + (y) - 1) / (y) * (y))
233 #define ROUND_DOWN_TO(x, y) ((x) / (y) * (y))
234 #define ROUND_TO_PAGE(x) ROUND_TO((x), GTT_PAGE_SIZE)
235 #define ROUND_TO_MB(x) ROUND_TO((x), MB(1))
236 #define PRIMARY_RINGBUFFER_SIZE KB(128)
239 /* Ring buffer registers, p277, overview p19
241 #define LP_RING 0x2030
242 #define HP_RING 0x2040
244 #define RING_TAIL 0x00
245 #define TAIL_ADDR 0x000FFFF8
246 #define I830_TAIL_MASK 0x001FFFF8
248 #define RING_HEAD 0x04
249 #define HEAD_WRAP_COUNT 0xFFE00000
250 #define HEAD_WRAP_ONE 0x00200000
251 #define HEAD_ADDR 0x001FFFFC
252 #define I830_HEAD_MASK 0x001FFFFC
254 #define RING_START 0x08
255 #define START_ADDR 0x03FFFFF8
256 #define I830_RING_START_MASK 0xFFFFF000
258 #define RING_LEN 0x0C
259 #define RING_NR_PAGES 0x001FF000
260 #define I830_RING_NR_PAGES 0x001FF000
261 #define RING_REPORT_MASK 0x00000006
262 #define RING_REPORT_64K 0x00000002
263 #define RING_REPORT_128K 0x00000004
264 #define RING_NO_REPORT 0x00000000
265 #define RING_VALID_MASK 0x00000001
266 #define RING_VALID 0x00000001
267 #define RING_INVALID 0x00000000
270 /* Fence/Tiling ranges [0..7]
275 #define I915G_FENCE_START_MASK 0x0ff00000
277 #define I830_FENCE_START_MASK 0x07f80000
279 #define FENCE_START_MASK 0x03F80000
280 #define FENCE_X_MAJOR 0x00000000
281 #define FENCE_Y_MAJOR 0x00001000
282 #define FENCE_SIZE_MASK 0x00000700
283 #define FENCE_SIZE_512K 0x00000000
284 #define FENCE_SIZE_1M 0x00000100
285 #define FENCE_SIZE_2M 0x00000200
286 #define FENCE_SIZE_4M 0x00000300
287 #define FENCE_SIZE_8M 0x00000400
288 #define FENCE_SIZE_16M 0x00000500
289 #define FENCE_SIZE_32M 0x00000600
290 #define FENCE_SIZE_64M 0x00000700
291 #define I915G_FENCE_SIZE_1M 0x00000000
292 #define I915G_FENCE_SIZE_2M 0x00000100
293 #define I915G_FENCE_SIZE_4M 0x00000200
294 #define I915G_FENCE_SIZE_8M 0x00000300
295 #define I915G_FENCE_SIZE_16M 0x00000400
296 #define I915G_FENCE_SIZE_32M 0x00000500
297 #define I915G_FENCE_SIZE_64M 0x00000600
298 #define I915G_FENCE_SIZE_128M 0x00000700
299 #define FENCE_PITCH_1 0x00000000
300 #define FENCE_PITCH_2 0x00000010
301 #define FENCE_PITCH_4 0x00000020
302 #define FENCE_PITCH_8 0x00000030
303 #define FENCE_PITCH_16 0x00000040
304 #define FENCE_PITCH_32 0x00000050
305 #define FENCE_PITCH_64 0x00000060
306 #define FENCE_VALID 0x00000001
310 # define MMIO_IN8(base, offset) \
311 *(volatile unsigned char *)(((unsigned char*)(base)) + (offset))
312 # define MMIO_IN32(base, offset) \
313 read_MMIO_LE32(base, offset)
314 # define MMIO_OUT8(base, offset, val) \
315 *(volatile unsigned char *)(((unsigned char*)(base)) + (offset)) = (val)
316 # define MMIO_OUT32(base, offset, val) \
317 *(volatile unsigned int *)(void *)(((unsigned char*)(base)) + (offset)) = CPU_TO_LE32(val)
320 /* Memory mapped register access macros */
321 #define INREG8(addr) MMIO_IN8(MMIO, addr)
322 #define INREG(addr) MMIO_IN32(MMIO, addr)
323 #define OUTREG8(addr, val) MMIO_OUT8(MMIO, addr, val)
324 #define OUTREG(addr, val) MMIO_OUT32(MMIO, addr, val)
326 #define DSPABASE 0x70184