src/mesa/drivers/dri/i965/test_eu_compact.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdlib.h>
  25 #include <stdio.h>
  26 #include <stdbool.h>
  27 #include "glsl/ralloc.h"
  28 #include "brw_context.h"
  29 #include "brw_eu.h"
  30
  31 static bool
  32 test_compact_instruction(struct brw_compile *p, struct brw_instruction src)
  33 {
  34    struct brw_context *brw = p->brw;
  35    struct intel_context *intel = &brw->intel;
  36
  37    struct brw_compact_instruction dst;
  38    memset(&dst, 0xd0, sizeof(dst));
  39
  40    if (brw_try_compact_instruction(p, &dst, &src)) {
  41       struct brw_instruction uncompacted;
  42
  43       brw_uncompact_instruction(intel, &uncompacted, &dst);
  44       if (memcmp(&uncompacted, &src, sizeof(src))) {
  45          brw_debug_compact_uncompact(intel, &src, &uncompacted);
  46          return false;
  47       }
  48    } else {
  49       struct brw_compact_instruction unchanged;
  50       memset(&unchanged, 0xd0, sizeof(unchanged));
  51       /* It's not supposed to change dst unless it compacted. */
  52       if (memcmp(&unchanged, &dst, sizeof(dst))) {
  53          fprintf(stderr, "Failed to compact, but dst changed\n");
  54          fprintf(stderr, "  Instruction: ");
  55          brw_disasm(stderr, &src, intel->gen);
  56          return false;
  57       }
  58    }
  59
  60    return true;
  61 }
  62
  63 /**
  64  * When doing fuzz testing, pad bits won't round-trip.
  65  *
  66  * This sort of a superset of skip_bit, which is testing for changing bits that
  67  * aren't worth testing for fuzzing.  We also just want to clear bits that
  68  * become meaningless once fuzzing twiddles a related bit.
  69  */
  70 static void
  71 clear_pad_bits(struct brw_instruction *inst)
  72 {
  73    if (inst->header.opcode != BRW_OPCODE_SEND &&
  74        inst->header.opcode != BRW_OPCODE_SENDC &&
  75        inst->header.opcode != BRW_OPCODE_BREAK &&
  76        inst->header.opcode != BRW_OPCODE_CONTINUE &&
  77        inst->bits1.da1.src0_reg_file != BRW_IMMEDIATE_VALUE &&
  78        inst->bits1.da1.src1_reg_file != BRW_IMMEDIATE_VALUE) {
  79       if (inst->bits3.da1.src1_address_mode)
  80          inst->bits3.ia1.pad1 = 0;
  81       else
  82          inst->bits3.da1.pad0 = 0;
  83    }
  84 }
  85
  86 static bool
  87 skip_bit(struct brw_instruction *src, int bit)
  88 {
  89    /* pad bit */
  90    if (bit == 7)
  91       return true;
  92
  93    /* The compact bit -- uncompacted can't have it set. */
  94    if (bit == 29)
  95       return true;
  96
  97    /* pad bit */
  98    if (bit == 47)
  99       return true;
 100
 101    /* pad bits */
 102    if (bit >= 90 && bit <= 95)
 103       return true;
 104
 105    /* sometimes these are pad bits. */
 106    if (src->header.opcode != BRW_OPCODE_SEND &&
 107        src->header.opcode != BRW_OPCODE_SENDC &&
 108        src->header.opcode != BRW_OPCODE_BREAK &&
 109        src->header.opcode != BRW_OPCODE_CONTINUE &&
 110        src->bits1.da1.src0_reg_file != BRW_IMMEDIATE_VALUE &&
 111        src->bits1.da1.src1_reg_file != BRW_IMMEDIATE_VALUE &&
 112        bit >= 121) {
 113       return true;
 114    }
 115
 116    return false;
 117 }
 118
 119 static bool
 120 test_fuzz_compact_instruction(struct brw_compile *p,
 121                               struct brw_instruction src)
 122 {
 123    for (int bit0 = 0; bit0 < 128; bit0++) {
 124       if (skip_bit(&src, bit0))
 125          continue;
 126
 127       for (int bit1 = 0; bit1 < 128; bit1++) {
 128          struct brw_instruction instr = src;
 129          uint32_t *bits = (uint32_t *)&instr;
 130
 131          if (skip_bit(&src, bit1))
 132             continue;
 133
 134          bits[bit0 / 32] ^= (1 << (bit0 & 31));
 135          bits[bit1 / 32] ^= (1 << (bit1 & 31));
 136
 137          clear_pad_bits(&instr);
 138
 139          if (!test_compact_instruction(p, instr)) {
 140             printf("  twiddled bits for fuzzing %d, %d\n", bit0, bit1);
 141             return false;
 142          }
 143       }
 144    }
 145
 146    return true;
 147 }
 148
 149 static void
 150 gen_ADD_GRF_GRF_GRF(struct brw_compile *p)
 151 {
 152    struct brw_reg g0 = brw_vec8_grf(0, 0);
 153    struct brw_reg g2 = brw_vec8_grf(2, 0);
 154    struct brw_reg g4 = brw_vec8_grf(4, 0);
 155
 156    brw_ADD(p, g0, g2, g4);
 157 }
 158
 159 static void
 160 gen_ADD_GRF_GRF_IMM(struct brw_compile *p)
 161 {
 162    struct brw_reg g0 = brw_vec8_grf(0, 0);
 163    struct brw_reg g2 = brw_vec8_grf(2, 0);
 164
 165    brw_ADD(p, g0, g2, brw_imm_f(1.0));
 166 }
 167
 168 static void
 169 gen_ADD_GRF_GRF_IMM_d(struct brw_compile *p)
 170 {
 171    struct brw_reg g0 = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_D);
 172    struct brw_reg g2 = retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_D);
 173
 174    brw_ADD(p, g0, g2, brw_imm_d(1));
 175 }
 176
 177 static void
 178 gen_MOV_GRF_GRF(struct brw_compile *p)
 179 {
 180    struct brw_reg g0 = brw_vec8_grf(0, 0);
 181    struct brw_reg g2 = brw_vec8_grf(2, 0);
 182
 183    brw_MOV(p, g0, g2);
 184 }
 185
 186 static void
 187 gen_ADD_MRF_GRF_GRF(struct brw_compile *p)
 188 {
 189    struct brw_reg m6 = brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE, 6, 0);
 190    struct brw_reg g2 = brw_vec8_grf(2, 0);
 191    struct brw_reg g4 = brw_vec8_grf(4, 0);
 192
 193    brw_ADD(p, m6, g2, g4);
 194 }
 195
 196 static void
 197 gen_ADD_vec1_GRF_GRF_GRF(struct brw_compile *p)
 198 {
 199    struct brw_reg g0 = brw_vec1_grf(0, 0);
 200    struct brw_reg g2 = brw_vec1_grf(2, 0);
 201    struct brw_reg g4 = brw_vec1_grf(4, 0);
 202
 203    brw_ADD(p, g0, g2, g4);
 204 }
 205
 206 static void
 207 gen_PLN_MRF_GRF_GRF(struct brw_compile *p)
 208 {
 209    struct brw_reg m6 = brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE, 6, 0);
 210    struct brw_reg interp = brw_vec1_grf(2, 0);
 211    struct brw_reg g4 = brw_vec8_grf(4, 0);
 212
 213    brw_PLN(p, m6, interp, g4);
 214 }
 215
 216 static void
 217 gen_f0_0_MOV_GRF_GRF(struct brw_compile *p)
 218 {
 219    struct brw_reg g0 = brw_vec8_grf(0, 0);
 220    struct brw_reg g2 = brw_vec8_grf(2, 0);
 221
 222    brw_push_insn_state(p);
 223    brw_set_predicate_control(p, true);
 224    brw_MOV(p, g0, g2);
 225    brw_pop_insn_state(p);
 226 }
 227
 228 /* The handling of f0.1 vs f0.0 changes between gen6 and gen7.  Explicitly test
 229  * it, so that we run the fuzzing can run over all the other bits that might
 230  * interact with it.
 231  */
 232 static void
 233 gen_f0_1_MOV_GRF_GRF(struct brw_compile *p)
 234 {
 235    struct brw_reg g0 = brw_vec8_grf(0, 0);
 236    struct brw_reg g2 = brw_vec8_grf(2, 0);
 237
 238    brw_push_insn_state(p);
 239    brw_set_predicate_control(p, true);
 240    current_insn(p)->bits2.da1.flag_subreg_nr = 1;
 241    brw_MOV(p, g0, g2);
 242    brw_pop_insn_state(p);
 243 }
 244
 245 struct {
 246    void (*func)(struct brw_compile *p);
 247 } tests[] = {
 248    { gen_MOV_GRF_GRF },
 249    { gen_ADD_GRF_GRF_GRF },
 250    { gen_ADD_GRF_GRF_IMM },
 251    { gen_ADD_GRF_GRF_IMM_d },
 252    { gen_ADD_MRF_GRF_GRF },
 253    { gen_ADD_vec1_GRF_GRF_GRF },
 254    { gen_PLN_MRF_GRF_GRF },
 255    { gen_f0_0_MOV_GRF_GRF },
 256    { gen_f0_1_MOV_GRF_GRF },
 257 };
 258
 259 static bool
 260 run_tests(struct brw_context *brw)
 261 {
 262    bool fail = false;
 263
 264    for (int i = 0; i < ARRAY_SIZE(tests); i++) {
 265       for (int align_16 = 0; align_16 <= 1; align_16++) {
 266          struct brw_compile *p = rzalloc(NULL, struct brw_compile);
 267          brw_init_compile(brw, p, p);
 268
 269          brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 270          if (align_16)
 271             brw_set_access_mode(p, BRW_ALIGN_16);
 272          else
 273             brw_set_access_mode(p, BRW_ALIGN_1);
 274
 275          tests[i].func(p);
 276          assert(p->nr_insn == 1);
 277
 278          if (!test_compact_instruction(p, p->store[0])) {
 279             fail = true;
 280             continue;
 281          }
 282
 283          if (!test_fuzz_compact_instruction(p, p->store[0])) {
 284             fail = true;
 285             continue;
 286          }
 287
 288          ralloc_free(p);
 289       }
 290    }
 291
 292    return fail;
 293 }
 294
 295 int
 296 main(int argc, char **argv)
 297 {
 298    struct brw_context *brw = calloc(1, sizeof(*brw));
 299    struct intel_context *intel = &brw->intel;
 300    intel->gen = 6;
 301    bool fail = false;
 302
 303    for (intel->gen = 6; intel->gen <= 7; intel->gen++) {
 304       fail |= run_tests(brw);
 305    }
 306
 307    return fail;
 308 }