2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "util/ralloc.h"
28 #include "brw_context.h"
32 test_compact_instruction(struct brw_compile
*p
, brw_inst src
)
34 struct brw_context
*brw
= p
->brw
;
37 memset(&dst
, 0xd0, sizeof(dst
));
39 if (brw_try_compact_instruction(brw
, &dst
, &src
)) {
42 brw_uncompact_instruction(brw
, &uncompacted
, &dst
);
43 if (memcmp(&uncompacted
, &src
, sizeof(src
))) {
44 brw_debug_compact_uncompact(brw
, &src
, &uncompacted
);
48 brw_compact_inst unchanged
;
49 memset(&unchanged
, 0xd0, sizeof(unchanged
));
50 /* It's not supposed to change dst unless it compacted. */
51 if (memcmp(&unchanged
, &dst
, sizeof(dst
))) {
52 fprintf(stderr
, "Failed to compact, but dst changed\n");
53 fprintf(stderr
, " Instruction: ");
54 brw_disassemble_inst(stderr
, brw
, &src
, false);
63 * When doing fuzz testing, pad bits won't round-trip.
65 * This sort of a superset of skip_bit, which is testing for changing bits that
66 * aren't worth testing for fuzzing. We also just want to clear bits that
67 * become meaningless once fuzzing twiddles a related bit.
70 clear_pad_bits(const struct brw_context
*brw
, brw_inst
*inst
)
72 if (brw_inst_opcode(brw
, inst
) != BRW_OPCODE_SEND
&&
73 brw_inst_opcode(brw
, inst
) != BRW_OPCODE_SENDC
&&
74 brw_inst_opcode(brw
, inst
) != BRW_OPCODE_BREAK
&&
75 brw_inst_opcode(brw
, inst
) != BRW_OPCODE_CONTINUE
&&
76 brw_inst_src0_reg_file(brw
, inst
) != BRW_IMMEDIATE_VALUE
&&
77 brw_inst_src1_reg_file(brw
, inst
) != BRW_IMMEDIATE_VALUE
) {
78 brw_inst_set_bits(inst
, 127, 111, 0);
83 skip_bit(const struct brw_context
*brw
, brw_inst
*src
, int bit
)
89 /* The compact bit -- uncompacted can't have it set. */
98 if (bit
>= 90 && bit
<= 95)
101 /* sometimes these are pad bits. */
102 if (brw_inst_opcode(brw
, src
) != BRW_OPCODE_SEND
&&
103 brw_inst_opcode(brw
, src
) != BRW_OPCODE_SENDC
&&
104 brw_inst_opcode(brw
, src
) != BRW_OPCODE_BREAK
&&
105 brw_inst_opcode(brw
, src
) != BRW_OPCODE_CONTINUE
&&
106 brw_inst_src0_reg_file(brw
, src
) != BRW_IMMEDIATE_VALUE
&&
107 brw_inst_src1_reg_file(brw
, src
) != BRW_IMMEDIATE_VALUE
&&
116 test_fuzz_compact_instruction(struct brw_compile
*p
, brw_inst src
)
118 for (int bit0
= 0; bit0
< 128; bit0
++) {
119 if (skip_bit(p
->brw
, &src
, bit0
))
122 for (int bit1
= 0; bit1
< 128; bit1
++) {
123 brw_inst instr
= src
;
124 uint32_t *bits
= (uint32_t *)&instr
;
126 if (skip_bit(p
->brw
, &src
, bit1
))
129 bits
[bit0
/ 32] ^= (1 << (bit0
& 31));
130 bits
[bit1
/ 32] ^= (1 << (bit1
& 31));
132 clear_pad_bits(p
->brw
, &instr
);
134 if (!test_compact_instruction(p
, instr
)) {
135 printf(" twiddled bits for fuzzing %d, %d\n", bit0
, bit1
);
145 gen_ADD_GRF_GRF_GRF(struct brw_compile
*p
)
147 struct brw_reg g0
= brw_vec8_grf(0, 0);
148 struct brw_reg g2
= brw_vec8_grf(2, 0);
149 struct brw_reg g4
= brw_vec8_grf(4, 0);
151 brw_ADD(p
, g0
, g2
, g4
);
155 gen_ADD_GRF_GRF_IMM(struct brw_compile
*p
)
157 struct brw_reg g0
= brw_vec8_grf(0, 0);
158 struct brw_reg g2
= brw_vec8_grf(2, 0);
160 brw_ADD(p
, g0
, g2
, brw_imm_f(1.0));
164 gen_ADD_GRF_GRF_IMM_d(struct brw_compile
*p
)
166 struct brw_reg g0
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_D
);
167 struct brw_reg g2
= retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_D
);
169 brw_ADD(p
, g0
, g2
, brw_imm_d(1));
173 gen_MOV_GRF_GRF(struct brw_compile
*p
)
175 struct brw_reg g0
= brw_vec8_grf(0, 0);
176 struct brw_reg g2
= brw_vec8_grf(2, 0);
182 gen_ADD_MRF_GRF_GRF(struct brw_compile
*p
)
184 struct brw_reg m6
= brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE
, 6, 0);
185 struct brw_reg g2
= brw_vec8_grf(2, 0);
186 struct brw_reg g4
= brw_vec8_grf(4, 0);
188 brw_ADD(p
, m6
, g2
, g4
);
192 gen_ADD_vec1_GRF_GRF_GRF(struct brw_compile
*p
)
194 struct brw_reg g0
= brw_vec1_grf(0, 0);
195 struct brw_reg g2
= brw_vec1_grf(2, 0);
196 struct brw_reg g4
= brw_vec1_grf(4, 0);
198 brw_ADD(p
, g0
, g2
, g4
);
202 gen_PLN_MRF_GRF_GRF(struct brw_compile
*p
)
204 struct brw_reg m6
= brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE
, 6, 0);
205 struct brw_reg interp
= brw_vec1_grf(2, 0);
206 struct brw_reg g4
= brw_vec8_grf(4, 0);
208 brw_PLN(p
, m6
, interp
, g4
);
212 gen_f0_0_MOV_GRF_GRF(struct brw_compile
*p
)
214 struct brw_reg g0
= brw_vec8_grf(0, 0);
215 struct brw_reg g2
= brw_vec8_grf(2, 0);
217 brw_push_insn_state(p
);
218 brw_set_default_predicate_control(p
, true);
220 brw_pop_insn_state(p
);
223 /* The handling of f0.1 vs f0.0 changes between gen6 and gen7. Explicitly test
224 * it, so that we run the fuzzing can run over all the other bits that might
228 gen_f0_1_MOV_GRF_GRF(struct brw_compile
*p
)
230 struct brw_reg g0
= brw_vec8_grf(0, 0);
231 struct brw_reg g2
= brw_vec8_grf(2, 0);
233 brw_push_insn_state(p
);
234 brw_set_default_predicate_control(p
, true);
235 brw_inst
*mov
= brw_MOV(p
, g0
, g2
);
236 brw_inst_set_flag_subreg_nr(p
->brw
, mov
, 1);
237 brw_pop_insn_state(p
);
241 void (*func
)(struct brw_compile
*p
);
244 { gen_ADD_GRF_GRF_GRF
},
245 { gen_ADD_GRF_GRF_IMM
},
246 { gen_ADD_GRF_GRF_IMM_d
},
247 { gen_ADD_MRF_GRF_GRF
},
248 { gen_ADD_vec1_GRF_GRF_GRF
},
249 { gen_PLN_MRF_GRF_GRF
},
250 { gen_f0_0_MOV_GRF_GRF
},
251 { gen_f0_1_MOV_GRF_GRF
},
255 run_tests(struct brw_context
*brw
)
259 for (int i
= 0; i
< ARRAY_SIZE(tests
); i
++) {
260 for (int align_16
= 0; align_16
<= 1; align_16
++) {
261 struct brw_compile
*p
= rzalloc(NULL
, struct brw_compile
);
262 brw_init_compile(brw
, p
, p
);
264 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
266 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
268 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
271 assert(p
->nr_insn
== 1);
273 if (!test_compact_instruction(p
, p
->store
[0])) {
278 if (!test_fuzz_compact_instruction(p
, p
->store
[0])) {
291 main(int argc
, char **argv
)
293 struct brw_context
*brw
= calloc(1, sizeof(*brw
));
297 for (brw
->gen
= 6; brw
->gen
<= 7; brw
->gen
++) {
298 fail
|= run_tests(brw
);