2 * Copyright © 2015 Intel Corporation
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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23 * Based on test_fs_cmod_propagation.cpp
26 #include <gtest/gtest.h>
28 #include "brw_vec4_builder.h"
30 #include "program/program.h"
34 class cmod_propagation_test
: public ::testing::Test
{
38 struct brw_compiler
*compiler
;
39 struct brw_device_info
*devinfo
;
40 struct gl_context
*ctx
;
41 struct gl_shader_program
*shader_prog
;
42 struct brw_vertex_program
*vp
;
46 class cmod_propagation_vec4_visitor
: public vec4_visitor
49 cmod_propagation_vec4_visitor(struct brw_compiler
*compiler
,
51 : vec4_visitor(compiler
, NULL
, NULL
, NULL
, shader
, NULL
,
55 /* Dummy implementation for pure virtual methods */
56 virtual dst_reg
*make_reg_for_system_value(int location
,
57 const glsl_type
*type
)
59 unreachable("Not reached");
62 virtual void setup_payload()
64 unreachable("Not reached");
67 virtual void emit_prolog()
69 unreachable("Not reached");
72 virtual void emit_program_code()
74 unreachable("Not reached");
77 virtual void emit_thread_end()
79 unreachable("Not reached");
82 virtual void emit_urb_write_header(int mrf
)
84 unreachable("Not reached");
87 virtual vec4_instruction
*emit_urb_write_opcode(bool complete
)
89 unreachable("Not reached");
94 void cmod_propagation_test::SetUp()
96 ctx
= (struct gl_context
*)calloc(1, sizeof(*ctx
));
97 compiler
= (struct brw_compiler
*)calloc(1, sizeof(*compiler
));
98 devinfo
= (struct brw_device_info
*)calloc(1, sizeof(*devinfo
));
99 compiler
->devinfo
= devinfo
;
101 vp
= ralloc(NULL
, struct brw_vertex_program
);
103 nir_shader
*shader
= nir_shader_create(NULL
, MESA_SHADER_VERTEX
, NULL
);
105 v
= new cmod_propagation_vec4_visitor(compiler
, shader
);
107 _mesa_init_gl_program(&vp
->program
.Base
, GL_VERTEX_SHADER
, 0);
112 static vec4_instruction
*
113 instruction(bblock_t
*block
, int num
)
115 vec4_instruction
*inst
= (vec4_instruction
*)block
->start();
116 for (int i
= 0; i
< num
; i
++) {
117 inst
= (vec4_instruction
*)inst
->next
;
123 cmod_propagation(vec4_visitor
*v
)
125 const bool print
= getenv("TEST_DEBUG");
128 fprintf(stderr
, "= Before =\n");
129 v
->dump_instructions();
132 bool ret
= v
->opt_cmod_propagation();
135 fprintf(stderr
, "\n= After =\n");
136 v
->dump_instructions();
142 TEST_F(cmod_propagation_test
, basic
)
144 const vec4_builder bld
= vec4_builder(v
).at_end();
145 dst_reg dest
= dst_reg(v
, glsl_type::float_type
);
146 src_reg src0
= src_reg(v
, glsl_type::float_type
);
147 src_reg src1
= src_reg(v
, glsl_type::float_type
);
149 dst_reg dest_null
= bld
.null_reg_f();
150 dest_null
.writemask
= WRITEMASK_X
;
152 bld
.ADD(dest
, src0
, src1
);
153 bld
.CMP(dest_null
, src_reg(dest
), zero
, BRW_CONDITIONAL_GE
);
157 * 0: add dest.x src0.xxxx src1.xxxx
158 * 1: cmp.ge.f0 null.x dest.xxxx 0.0f
161 * 0: add.ge.f0 dest.x src0.xxxx src1.xxxx
165 bblock_t
*block0
= v
->cfg
->blocks
[0];
167 EXPECT_EQ(0, block0
->start_ip
);
168 EXPECT_EQ(1, block0
->end_ip
);
170 EXPECT_TRUE(cmod_propagation(v
));
172 ASSERT_EQ(0, block0
->start_ip
);
173 ASSERT_EQ(0, block0
->end_ip
);
174 EXPECT_EQ(BRW_OPCODE_ADD
, instruction(block0
, 0)->opcode
);
175 EXPECT_EQ(BRW_CONDITIONAL_GE
, instruction(block0
, 0)->conditional_mod
);
178 TEST_F(cmod_propagation_test
, basic_different_dst_writemask
)
180 const vec4_builder bld
= vec4_builder(v
).at_end();
181 dst_reg dest
= dst_reg(v
, glsl_type::float_type
);
182 src_reg src0
= src_reg(v
, glsl_type::float_type
);
183 src_reg src1
= src_reg(v
, glsl_type::float_type
);
185 dst_reg dest_null
= bld
.null_reg_f();
187 bld
.ADD(dest
, src0
, src1
);
188 bld
.CMP(dest_null
, src_reg(dest
), zero
, BRW_CONDITIONAL_GE
);
192 * 0: add dest.x src0 src1
193 * 1: cmp.ge.f0 null.xyzw dest 0.0f
200 bblock_t
*block0
= v
->cfg
->blocks
[0];
202 EXPECT_EQ(0, block0
->start_ip
);
203 EXPECT_EQ(1, block0
->end_ip
);
205 EXPECT_FALSE(cmod_propagation(v
));
207 ASSERT_EQ(0, block0
->start_ip
);
208 ASSERT_EQ(1, block0
->end_ip
);
209 EXPECT_EQ(BRW_OPCODE_ADD
, instruction(block0
, 0)->opcode
);
210 EXPECT_EQ(BRW_CONDITIONAL_NONE
, instruction(block0
, 0)->conditional_mod
);
211 EXPECT_EQ(BRW_OPCODE_CMP
, instruction(block0
, 1)->opcode
);
212 EXPECT_EQ(BRW_CONDITIONAL_GE
, instruction(block0
, 1)->conditional_mod
);
215 TEST_F(cmod_propagation_test
, andz_one
)
217 const vec4_builder bld
= vec4_builder(v
).at_end();
218 dst_reg dest
= dst_reg(v
, glsl_type::int_type
);
219 src_reg src0
= src_reg(v
, glsl_type::float_type
);
223 bld
.CMP(retype(dest
, BRW_REGISTER_TYPE_F
), src0
, zero
, BRW_CONDITIONAL_L
);
224 set_condmod(BRW_CONDITIONAL_Z
,
225 bld
.AND(bld
.null_reg_d(), src_reg(dest
), one
));
228 * 0: cmp.l.f0 dest:F src0:F 0F
229 * 1: and.z.f0 null:D dest:D 1D
236 bblock_t
*block0
= v
->cfg
->blocks
[0];
238 EXPECT_EQ(0, block0
->start_ip
);
239 EXPECT_EQ(1, block0
->end_ip
);
241 EXPECT_FALSE(cmod_propagation(v
));
243 ASSERT_EQ(0, block0
->start_ip
);
244 ASSERT_EQ(1, block0
->end_ip
);
245 EXPECT_EQ(BRW_OPCODE_CMP
, instruction(block0
, 0)->opcode
);
246 EXPECT_EQ(BRW_CONDITIONAL_L
, instruction(block0
, 0)->conditional_mod
);
247 EXPECT_EQ(BRW_OPCODE_AND
, instruction(block0
, 1)->opcode
);
248 EXPECT_EQ(BRW_CONDITIONAL_EQ
, instruction(block0
, 1)->conditional_mod
);
251 TEST_F(cmod_propagation_test
, non_cmod_instruction
)
253 const vec4_builder bld
= vec4_builder(v
).at_end();
254 dst_reg dest
= dst_reg(v
, glsl_type::uint_type
);
255 src_reg src0
= src_reg(v
, glsl_type::uint_type
);
258 bld
.CMP(bld
.null_reg_ud(), src_reg(dest
), zero
, BRW_CONDITIONAL_GE
);
263 * 1: cmp.ge.f0 null dest 0u
270 bblock_t
*block0
= v
->cfg
->blocks
[0];
272 EXPECT_EQ(0, block0
->start_ip
);
273 EXPECT_EQ(1, block0
->end_ip
);
275 EXPECT_FALSE(cmod_propagation(v
));
277 ASSERT_EQ(0, block0
->start_ip
);
278 ASSERT_EQ(1, block0
->end_ip
);
279 EXPECT_EQ(BRW_OPCODE_FBL
, instruction(block0
, 0)->opcode
);
280 EXPECT_EQ(BRW_OPCODE_CMP
, instruction(block0
, 1)->opcode
);
281 EXPECT_EQ(BRW_CONDITIONAL_GE
, instruction(block0
, 1)->conditional_mod
);
284 TEST_F(cmod_propagation_test
, intervening_flag_write
)
286 const vec4_builder bld
= vec4_builder(v
).at_end();
287 dst_reg dest
= dst_reg(v
, glsl_type::float_type
);
288 src_reg src0
= src_reg(v
, glsl_type::float_type
);
289 src_reg src1
= src_reg(v
, glsl_type::float_type
);
290 src_reg src2
= src_reg(v
, glsl_type::float_type
);
292 bld
.ADD(dest
, src0
, src1
);
293 bld
.CMP(bld
.null_reg_f(), src2
, zero
, BRW_CONDITIONAL_GE
);
294 bld
.CMP(bld
.null_reg_f(), src_reg(dest
), zero
, BRW_CONDITIONAL_GE
);
298 * 0: add dest src0 src1
299 * 1: cmp.ge.f0 null src2 0.0f
300 * 2: cmp.ge.f0 null dest 0.0f
307 bblock_t
*block0
= v
->cfg
->blocks
[0];
309 EXPECT_EQ(0, block0
->start_ip
);
310 EXPECT_EQ(2, block0
->end_ip
);
312 EXPECT_FALSE(cmod_propagation(v
));
314 ASSERT_EQ(0, block0
->start_ip
);
315 ASSERT_EQ(2, block0
->end_ip
);
316 EXPECT_EQ(BRW_OPCODE_ADD
, instruction(block0
, 0)->opcode
);
317 EXPECT_EQ(BRW_OPCODE_CMP
, instruction(block0
, 1)->opcode
);
318 EXPECT_EQ(BRW_CONDITIONAL_GE
, instruction(block0
, 1)->conditional_mod
);
319 EXPECT_EQ(BRW_OPCODE_CMP
, instruction(block0
, 2)->opcode
);
320 EXPECT_EQ(BRW_CONDITIONAL_GE
, instruction(block0
, 2)->conditional_mod
);
323 TEST_F(cmod_propagation_test
, intervening_flag_read
)
325 const vec4_builder bld
= vec4_builder(v
).at_end();
326 dst_reg dest0
= dst_reg(v
, glsl_type::float_type
);
327 dst_reg dest1
= dst_reg(v
, glsl_type::float_type
);
328 src_reg src0
= src_reg(v
, glsl_type::float_type
);
329 src_reg src1
= src_reg(v
, glsl_type::float_type
);
330 src_reg src2
= src_reg(v
, glsl_type::float_type
);
332 bld
.ADD(dest0
, src0
, src1
);
333 set_predicate(BRW_PREDICATE_NORMAL
, bld
.SEL(dest1
, src2
, zero
));
334 bld
.CMP(bld
.null_reg_f(), src_reg(dest0
), zero
, BRW_CONDITIONAL_GE
);
338 * 0: add dest0 src0 src1
339 * 1: (+f0) sel dest1 src2 0.0f
340 * 2: cmp.ge.f0 null dest0 0.0f
347 bblock_t
*block0
= v
->cfg
->blocks
[0];
349 EXPECT_EQ(0, block0
->start_ip
);
350 EXPECT_EQ(2, block0
->end_ip
);
352 EXPECT_FALSE(cmod_propagation(v
));
354 ASSERT_EQ(0, block0
->start_ip
);
355 ASSERT_EQ(2, block0
->end_ip
);
356 EXPECT_EQ(BRW_OPCODE_ADD
, instruction(block0
, 0)->opcode
);
357 EXPECT_EQ(BRW_OPCODE_SEL
, instruction(block0
, 1)->opcode
);
358 EXPECT_EQ(BRW_PREDICATE_NORMAL
, instruction(block0
, 1)->predicate
);
359 EXPECT_EQ(BRW_OPCODE_CMP
, instruction(block0
, 2)->opcode
);
360 EXPECT_EQ(BRW_CONDITIONAL_GE
, instruction(block0
, 2)->conditional_mod
);
363 TEST_F(cmod_propagation_test
, intervening_dest_write
)
365 const vec4_builder bld
= vec4_builder(v
).at_end();
366 dst_reg dest
= dst_reg(v
, glsl_type::vec4_type
);
367 src_reg src0
= src_reg(v
, glsl_type::float_type
);
368 src_reg src1
= src_reg(v
, glsl_type::float_type
);
369 src_reg src2
= src_reg(v
, glsl_type::vec2_type
);
371 bld
.ADD(offset(dest
, 2), src0
, src1
);
372 bld
.emit(SHADER_OPCODE_TEX
, dest
, src2
)
374 bld
.CMP(bld
.null_reg_f(), offset(src_reg(dest
), 2), zero
, BRW_CONDITIONAL_GE
);
378 * 0: add dest+2 src0 src1
379 * 1: tex rlen 4 dest+0 src2
380 * 2: cmp.ge.f0 null dest+2 0.0f
387 bblock_t
*block0
= v
->cfg
->blocks
[0];
389 EXPECT_EQ(0, block0
->start_ip
);
390 EXPECT_EQ(2, block0
->end_ip
);
392 EXPECT_FALSE(cmod_propagation(v
));
394 ASSERT_EQ(0, block0
->start_ip
);
395 ASSERT_EQ(2, block0
->end_ip
);
396 EXPECT_EQ(BRW_OPCODE_ADD
, instruction(block0
, 0)->opcode
);
397 EXPECT_EQ(BRW_CONDITIONAL_NONE
, instruction(block0
, 0)->conditional_mod
);
398 EXPECT_EQ(SHADER_OPCODE_TEX
, instruction(block0
, 1)->opcode
);
399 EXPECT_EQ(BRW_CONDITIONAL_NONE
, instruction(block0
, 0)->conditional_mod
);
400 EXPECT_EQ(BRW_OPCODE_CMP
, instruction(block0
, 2)->opcode
);
401 EXPECT_EQ(BRW_CONDITIONAL_GE
, instruction(block0
, 2)->conditional_mod
);
404 TEST_F(cmod_propagation_test
, intervening_flag_read_same_value
)
406 const vec4_builder bld
= vec4_builder(v
).at_end();
407 dst_reg dest0
= dst_reg(v
, glsl_type::float_type
);
408 dst_reg dest1
= dst_reg(v
, glsl_type::float_type
);
409 src_reg src0
= src_reg(v
, glsl_type::float_type
);
410 src_reg src1
= src_reg(v
, glsl_type::float_type
);
411 src_reg src2
= src_reg(v
, glsl_type::float_type
);
413 dst_reg dest_null
= bld
.null_reg_f();
414 dest_null
.writemask
= WRITEMASK_X
;
416 set_condmod(BRW_CONDITIONAL_GE
, bld
.ADD(dest0
, src0
, src1
));
417 set_predicate(BRW_PREDICATE_NORMAL
, bld
.SEL(dest1
, src2
, zero
));
418 bld
.CMP(dest_null
, src_reg(dest0
), zero
, BRW_CONDITIONAL_GE
);
422 * 0: add.ge.f0 dest0 src0 src1
423 * 1: (+f0) sel dest1 src2 0.0f
424 * 2: cmp.ge.f0 null.x dest0 0.0f
427 * 0: add.ge.f0 dest0 src0 src1
428 * 1: (+f0) sel dest1 src2 0.0f
432 bblock_t
*block0
= v
->cfg
->blocks
[0];
434 EXPECT_EQ(0, block0
->start_ip
);
435 EXPECT_EQ(2, block0
->end_ip
);
437 EXPECT_TRUE(cmod_propagation(v
));
438 ASSERT_EQ(0, block0
->start_ip
);
439 ASSERT_EQ(1, block0
->end_ip
);
440 EXPECT_EQ(BRW_OPCODE_ADD
, instruction(block0
, 0)->opcode
);
441 EXPECT_EQ(BRW_CONDITIONAL_GE
, instruction(block0
, 0)->conditional_mod
);
442 EXPECT_EQ(BRW_OPCODE_SEL
, instruction(block0
, 1)->opcode
);
443 EXPECT_EQ(BRW_PREDICATE_NORMAL
, instruction(block0
, 1)->predicate
);
446 TEST_F(cmod_propagation_test
, negate
)
448 const vec4_builder bld
= vec4_builder(v
).at_end();
449 dst_reg dest
= dst_reg(v
, glsl_type::float_type
);
450 src_reg src0
= src_reg(v
, glsl_type::float_type
);
451 src_reg src1
= src_reg(v
, glsl_type::float_type
);
453 bld
.ADD(dest
, src0
, src1
);
454 src_reg tmp_src
= src_reg(dest
);
455 tmp_src
.negate
= true;
456 dst_reg dest_null
= bld
.null_reg_f();
457 dest_null
.writemask
= WRITEMASK_X
;
458 bld
.CMP(dest_null
, tmp_src
, zero
, BRW_CONDITIONAL_GE
);
462 * 0: add dest src0 src1
463 * 1: cmp.ge.f0 null.x -dest 0.0f
466 * 0: add.le.f0 dest src0 src1
470 bblock_t
*block0
= v
->cfg
->blocks
[0];
472 EXPECT_EQ(0, block0
->start_ip
);
473 EXPECT_EQ(1, block0
->end_ip
);
475 EXPECT_TRUE(cmod_propagation(v
));
476 EXPECT_EQ(0, block0
->start_ip
);
477 EXPECT_EQ(0, block0
->end_ip
);
478 EXPECT_EQ(BRW_OPCODE_ADD
, instruction(block0
, 0)->opcode
);
479 EXPECT_EQ(BRW_CONDITIONAL_LE
, instruction(block0
, 0)->conditional_mod
);
482 TEST_F(cmod_propagation_test
, movnz
)
484 const vec4_builder bld
= vec4_builder(v
).at_end();
485 dst_reg dest
= dst_reg(v
, glsl_type::float_type
);
486 src_reg src0
= src_reg(v
, glsl_type::float_type
);
487 src_reg src1
= src_reg(v
, glsl_type::float_type
);
488 dst_reg dest_null
= bld
.null_reg_f();
489 dest_null
.writemask
= WRITEMASK_X
;
491 bld
.CMP(dest
, src0
, src1
, BRW_CONDITIONAL_L
);
492 set_condmod(BRW_CONDITIONAL_NZ
,
493 bld
.MOV(dest_null
, src_reg(dest
)));
497 * 0: cmp.l.f0 dest:F src0:F src1:F
498 * 1: mov.nz.f0 null.x dest:F
501 * 0: cmp.l.f0 dest src0:F src1:F
505 bblock_t
*block0
= v
->cfg
->blocks
[0];
507 EXPECT_EQ(0, block0
->start_ip
);
508 EXPECT_EQ(1, block0
->end_ip
);
510 EXPECT_TRUE(cmod_propagation(v
));
512 ASSERT_EQ(0, block0
->start_ip
);
513 ASSERT_EQ(0, block0
->end_ip
);
514 EXPECT_EQ(BRW_OPCODE_CMP
, instruction(block0
, 0)->opcode
);
515 EXPECT_EQ(BRW_CONDITIONAL_L
, instruction(block0
, 0)->conditional_mod
);
518 TEST_F(cmod_propagation_test
, different_types_cmod_with_zero
)
520 const vec4_builder bld
= vec4_builder(v
).at_end();
521 dst_reg dest
= dst_reg(v
, glsl_type::int_type
);
522 src_reg src0
= src_reg(v
, glsl_type::int_type
);
523 src_reg src1
= src_reg(v
, glsl_type::int_type
);
525 bld
.ADD(dest
, src0
, src1
);
526 bld
.CMP(bld
.null_reg_f(), retype(src_reg(dest
), BRW_REGISTER_TYPE_F
), zero
,
531 * 0: add dest:D src0:D src1:D
532 * 1: cmp.ge.f0 null:F dest:F 0.0f
539 bblock_t
*block0
= v
->cfg
->blocks
[0];
541 EXPECT_EQ(0, block0
->start_ip
);
542 EXPECT_EQ(1, block0
->end_ip
);
544 EXPECT_FALSE(cmod_propagation(v
));
546 ASSERT_EQ(0, block0
->start_ip
);
547 ASSERT_EQ(1, block0
->end_ip
);
548 EXPECT_EQ(BRW_OPCODE_ADD
, instruction(block0
, 0)->opcode
);
549 EXPECT_EQ(BRW_OPCODE_CMP
, instruction(block0
, 1)->opcode
);
550 EXPECT_EQ(BRW_CONDITIONAL_GE
, instruction(block0
, 1)->conditional_mod
);
553 TEST_F(cmod_propagation_test
, andnz_non_one
)
555 const vec4_builder bld
= vec4_builder(v
).at_end();
556 dst_reg dest
= dst_reg(v
, glsl_type::int_type
);
557 src_reg src0
= src_reg(v
, glsl_type::float_type
);
561 bld
.CMP(retype(dest
, BRW_REGISTER_TYPE_F
), src0
, zero
, BRW_CONDITIONAL_L
);
562 set_condmod(BRW_CONDITIONAL_NZ
,
563 bld
.AND(bld
.null_reg_d(), src_reg(dest
), nonone
));
566 * 0: cmp.l.f0 dest:F src0:F 0F
567 * 1: and.nz.f0 null:D dest:D 38D
574 bblock_t
*block0
= v
->cfg
->blocks
[0];
576 EXPECT_EQ(0, block0
->start_ip
);
577 EXPECT_EQ(1, block0
->end_ip
);
579 EXPECT_FALSE(cmod_propagation(v
));
581 ASSERT_EQ(0, block0
->start_ip
);
582 ASSERT_EQ(1, block0
->end_ip
);
583 EXPECT_EQ(BRW_OPCODE_CMP
, instruction(block0
, 0)->opcode
);
584 EXPECT_EQ(BRW_CONDITIONAL_L
, instruction(block0
, 0)->conditional_mod
);
585 EXPECT_EQ(BRW_OPCODE_AND
, instruction(block0
, 1)->opcode
);
586 EXPECT_EQ(BRW_CONDITIONAL_NZ
, instruction(block0
, 1)->conditional_mod
);
589 /* Note that basic is using glsl_type:float types, while this one is using
591 TEST_F(cmod_propagation_test
, basic_vec4
)
593 const vec4_builder bld
= vec4_builder(v
).at_end();
594 dst_reg dest
= dst_reg(v
, glsl_type::vec4_type
);
595 src_reg src0
= src_reg(v
, glsl_type::vec4_type
);
596 src_reg src1
= src_reg(v
, glsl_type::vec4_type
);
599 bld
.MUL(dest
, src0
, src1
);
600 bld
.CMP(bld
.null_reg_f(), src_reg(dest
), zero
, BRW_CONDITIONAL_NZ
);
603 * 0: mul dest.xyzw src0.xyzw src1.xyzw
604 * 1: cmp.nz.f0.0 null.xyzw dest.xyzw 0.0f
607 * 0: mul.nz.f0.0 dest.xyzw src0.xyzw src1.xyzw
611 bblock_t
*block0
= v
->cfg
->blocks
[0];
613 EXPECT_EQ(0, block0
->start_ip
);
614 EXPECT_EQ(1, block0
->end_ip
);
616 EXPECT_TRUE(cmod_propagation(v
));
618 ASSERT_EQ(0, block0
->start_ip
);
619 ASSERT_EQ(0, block0
->end_ip
);
620 EXPECT_EQ(BRW_OPCODE_MUL
, instruction(block0
, 0)->opcode
);
621 EXPECT_EQ(BRW_CONDITIONAL_NZ
, instruction(block0
, 0)->conditional_mod
);
624 TEST_F(cmod_propagation_test
, basic_vec4_different_dst_writemask
)
626 const vec4_builder bld
= vec4_builder(v
).at_end();
627 dst_reg dest
= dst_reg(v
, glsl_type::vec4_type
);
628 dest
.writemask
= WRITEMASK_X
;
629 src_reg src0
= src_reg(v
, glsl_type::vec4_type
);
630 src_reg src1
= src_reg(v
, glsl_type::vec4_type
);
632 dst_reg dest_null
= bld
.null_reg_f();
634 bld
.MUL(dest
, src0
, src1
);
635 bld
.CMP(dest_null
, src_reg(dest
), zero
, BRW_CONDITIONAL_NZ
);
638 * 0: mul dest.x src0 src1
639 * 1: cmp.nz.f0.0 null dest 0.0f
646 bblock_t
*block0
= v
->cfg
->blocks
[0];
648 EXPECT_EQ(0, block0
->start_ip
);
649 EXPECT_EQ(1, block0
->end_ip
);
651 EXPECT_FALSE(cmod_propagation(v
));
653 ASSERT_EQ(0, block0
->start_ip
);
654 ASSERT_EQ(1, block0
->end_ip
);
655 EXPECT_EQ(BRW_OPCODE_MUL
, instruction(block0
, 0)->opcode
);
656 EXPECT_EQ(BRW_CONDITIONAL_NONE
, instruction(block0
, 0)->conditional_mod
);
657 EXPECT_EQ(BRW_OPCODE_CMP
, instruction(block0
, 1)->opcode
);
658 EXPECT_EQ(BRW_CONDITIONAL_NZ
, instruction(block0
, 1)->conditional_mod
);
661 TEST_F(cmod_propagation_test
, mad_one_component_vec4
)
663 const vec4_builder bld
= vec4_builder(v
).at_end();
664 dst_reg dest
= dst_reg(v
, glsl_type::vec4_type
);
665 dest
.writemask
= WRITEMASK_X
;
666 src_reg src0
= src_reg(v
, glsl_type::vec4_type
);
667 src_reg src1
= src_reg(v
, glsl_type::vec4_type
);
668 src_reg src2
= src_reg(v
, glsl_type::vec4_type
);
669 src0
.swizzle
= src1
.swizzle
= src2
.swizzle
= BRW_SWIZZLE_XXXX
;
673 tmp
.swizzle
= BRW_SWIZZLE_XXXX
;
674 dst_reg dest_null
= bld
.null_reg_f();
675 dest_null
.writemask
= WRITEMASK_X
;
677 bld
.MAD(dest
, src0
, src1
, src2
);
678 bld
.CMP(dest_null
, tmp
, zero
, BRW_CONDITIONAL_L
);
682 * 0: mad dest.x:F src0.xxxx:F src10.xxxx:F -src2.xxxx:F
683 * 1: cmp.l.f0.0 null.x:F dest.xxxx:F 0.0f
686 * 0: mad.l.f0 dest.x:F src0.xxxx:F src10.xxxx:F -src2.xxxx:F
690 bblock_t
*block0
= v
->cfg
->blocks
[0];
692 EXPECT_EQ(0, block0
->start_ip
);
693 EXPECT_EQ(1, block0
->end_ip
);
695 EXPECT_TRUE(cmod_propagation(v
));
697 ASSERT_EQ(0, block0
->start_ip
);
698 ASSERT_EQ(0, block0
->end_ip
);
699 EXPECT_EQ(BRW_OPCODE_MAD
, instruction(block0
, 0)->opcode
);
700 EXPECT_EQ(BRW_CONDITIONAL_L
, instruction(block0
, 0)->conditional_mod
);
703 TEST_F(cmod_propagation_test
, mad_more_one_component_vec4
)
705 const vec4_builder bld
= vec4_builder(v
).at_end();
706 dst_reg dest
= dst_reg(v
, glsl_type::vec4_type
);
707 dest
.writemask
= WRITEMASK_XW
;
708 src_reg src0
= src_reg(v
, glsl_type::vec4_type
);
709 src_reg src1
= src_reg(v
, glsl_type::vec4_type
);
710 src_reg src2
= src_reg(v
, glsl_type::vec4_type
);
711 src0
.swizzle
= src1
.swizzle
= src2
.swizzle
= BRW_SWIZZLE_XXXX
;
715 tmp
.swizzle
= BRW_SWIZZLE_XXXX
;
716 dst_reg dest_null
= bld
.null_reg_f();
718 bld
.MAD(dest
, src0
, src1
, src2
);
719 bld
.CMP(dest_null
, tmp
, zero
, BRW_CONDITIONAL_L
);
723 * 0: mad dest.xw:F src0.xxxx:F src10.xxxx:F -src2.xxxx:F
724 * 1: cmp.l.f0.0 null:F dest.xxxx:F zeroF
731 bblock_t
*block0
= v
->cfg
->blocks
[0];
733 EXPECT_EQ(0, block0
->start_ip
);
734 EXPECT_EQ(1, block0
->end_ip
);
736 EXPECT_FALSE(cmod_propagation(v
));
738 ASSERT_EQ(0, block0
->start_ip
);
739 ASSERT_EQ(1, block0
->end_ip
);
740 EXPECT_EQ(BRW_OPCODE_MAD
, instruction(block0
, 0)->opcode
);
741 EXPECT_EQ(BRW_CONDITIONAL_NONE
, instruction(block0
, 0)->conditional_mod
);
742 EXPECT_EQ(BRW_OPCODE_CMP
, instruction(block0
, 1)->opcode
);
743 EXPECT_EQ(BRW_CONDITIONAL_L
, instruction(block0
, 1)->conditional_mod
);
746 TEST_F(cmod_propagation_test
, cmp_mov_vec4
)
748 const vec4_builder bld
= vec4_builder(v
).at_end();
749 dst_reg dest
= dst_reg(v
, glsl_type::ivec4_type
);
750 dest
.writemask
= WRITEMASK_X
;
751 src_reg src0
= src_reg(v
, glsl_type::ivec4_type
);
752 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
754 src_reg nonone
= retype(src_reg(16), BRW_REGISTER_TYPE_D
);
755 src_reg mov_src
= src_reg(dest
);
756 mov_src
.swizzle
= BRW_SWIZZLE_XXXX
;
757 dst_reg dest_null
= bld
.null_reg_d();
758 dest_null
.writemask
= WRITEMASK_X
;
760 bld
.CMP(dest
, src0
, nonone
, BRW_CONDITIONAL_GE
);
761 set_condmod(BRW_CONDITIONAL_NZ
,
762 bld
.MOV(dest_null
, mov_src
));
766 * 0: cmp.ge.f0 dest.x:D u.xxxx:D 16D
767 * 1: mov.nz.f0 null.x:D dest.xxxx:D
770 * 0: cmp.ge.f0 dest.x:D u.xxxx:D 16D
774 bblock_t
*block0
= v
->cfg
->blocks
[0];
776 EXPECT_EQ(0, block0
->start_ip
);
777 EXPECT_EQ(1, block0
->end_ip
);
779 EXPECT_TRUE(cmod_propagation(v
));
781 ASSERT_EQ(0, block0
->start_ip
);
782 ASSERT_EQ(0, block0
->end_ip
);
783 EXPECT_EQ(BRW_OPCODE_CMP
, instruction(block0
, 0)->opcode
);
784 EXPECT_EQ(BRW_CONDITIONAL_GE
, instruction(block0
, 0)->conditional_mod
);
787 TEST_F(cmod_propagation_test
, mul_cmp_different_channels_vec4
)
789 const vec4_builder bld
= vec4_builder(v
).at_end();
790 dst_reg dest
= dst_reg(v
, glsl_type::vec4_type
);
791 src_reg src0
= src_reg(v
, glsl_type::vec4_type
);
792 src_reg src1
= src_reg(v
, glsl_type::vec4_type
);
794 src_reg cmp_src
= src_reg(dest
);
795 cmp_src
.swizzle
= BRW_SWIZZLE4(0,1,3,2);
797 bld
.MUL(dest
, src0
, src1
);
798 bld
.CMP(bld
.null_reg_f(), cmp_src
, zero
, BRW_CONDITIONAL_NZ
);
801 * 0: mul dest src0 src1
802 * 1: cmp.nz.f0.0 null dest.xywz 0.0f
809 bblock_t
*block0
= v
->cfg
->blocks
[0];
811 EXPECT_EQ(0, block0
->start_ip
);
812 EXPECT_EQ(1, block0
->end_ip
);
814 EXPECT_FALSE(cmod_propagation(v
));
816 ASSERT_EQ(0, block0
->start_ip
);
817 ASSERT_EQ(1, block0
->end_ip
);
818 EXPECT_EQ(BRW_OPCODE_MUL
, instruction(block0
, 0)->opcode
);
819 EXPECT_EQ(BRW_CONDITIONAL_NONE
, instruction(block0
, 0)->conditional_mod
);
820 EXPECT_EQ(BRW_OPCODE_CMP
, instruction(block0
, 1)->opcode
);
821 EXPECT_EQ(BRW_CONDITIONAL_NZ
, instruction(block0
, 1)->conditional_mod
);