src/mesa/drivers/dri/i965/test_vec4_register_coalesce.cpp

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <gtest/gtest.h>
  25 #include "brw_vec4.h"
  26 #include "brw_vs.h"
  27 #include "program/program.h"
  28
  29 using namespace brw;
  30
  31 int ret = 0;
  32
  33 #define register_coalesce(v) _register_coalesce(v, __func__)
  34
  35 class register_coalesce_test : public ::testing::Test {
  36    virtual void SetUp();
  37
  38 public:
  39    struct brw_compiler *compiler;
  40    struct brw_device_info *devinfo;
  41    struct gl_context *ctx;
  42    struct gl_shader_program *shader_prog;
  43    struct brw_vue_prog_data *prog_data;
  44    vec4_visitor *v;
  45 };
  46
  47
  48 class register_coalesce_vec4_visitor : public vec4_visitor
  49 {
  50 public:
  51    register_coalesce_vec4_visitor(struct brw_compiler *compiler,
  52                                   nir_shader *shader,
  53                                   struct brw_vue_prog_data *prog_data)
  54       : vec4_visitor(compiler, NULL, NULL, prog_data, shader, NULL,
  55                      false /* no_spills */, -1)
  56    {
  57       prog_data->dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
  58    }
  59
  60 protected:
  61    virtual dst_reg *make_reg_for_system_value(int location)
  62    {
  63       unreachable("Not reached");
  64    }
  65
  66    virtual void setup_payload()
  67    {
  68       unreachable("Not reached");
  69    }
  70
  71    virtual void emit_prolog()
  72    {
  73       unreachable("Not reached");
  74    }
  75
  76    virtual void emit_thread_end()
  77    {
  78       unreachable("Not reached");
  79    }
  80
  81    virtual void emit_urb_write_header(int mrf)
  82    {
  83       unreachable("Not reached");
  84    }
  85
  86    virtual vec4_instruction *emit_urb_write_opcode(bool complete)
  87    {
  88       unreachable("Not reached");
  89    }
  90 };
  91
  92
  93 void register_coalesce_test::SetUp()
  94 {
  95    ctx = (struct gl_context *)calloc(1, sizeof(*ctx));
  96    compiler = (struct brw_compiler *)calloc(1, sizeof(*compiler));
  97    devinfo = (struct brw_device_info *)calloc(1, sizeof(*devinfo));
  98    prog_data = (struct brw_vue_prog_data *)calloc(1, sizeof(*prog_data));
  99    compiler->devinfo = devinfo;
 100
 101    nir_shader *shader = nir_shader_create(NULL, MESA_SHADER_VERTEX, NULL);
 102
 103    v = new register_coalesce_vec4_visitor(compiler, shader, prog_data);
 104
 105    devinfo->gen = 4;
 106 }
 107
 108 static void
 109 _register_coalesce(vec4_visitor *v, const char *func)
 110 {
 111    bool print = false;
 112
 113    if (print) {
 114       printf("%s: instructions before:\n", func);
 115       v->dump_instructions();
 116    }
 117
 118    v->calculate_cfg();
 119    v->opt_register_coalesce();
 120
 121    if (print) {
 122       printf("%s: instructions after:\n", func);
 123       v->dump_instructions();
 124    }
 125 }
 126
 127 TEST_F(register_coalesce_test, test_compute_to_mrf)
 128 {
 129    src_reg something = src_reg(v, glsl_type::float_type);
 130    dst_reg temp = dst_reg(v, glsl_type::float_type);
 131    dst_reg init;
 132
 133    dst_reg m0 = dst_reg(MRF, 0);
 134    m0.writemask = WRITEMASK_X;
 135    m0.type = BRW_REGISTER_TYPE_F;
 136
 137    vec4_instruction *mul = v->emit(v->MUL(temp, something, brw_imm_f(1.0f)));
 138    v->emit(v->MOV(m0, src_reg(temp)));
 139
 140    register_coalesce(v);
 141
 142    EXPECT_EQ(mul->dst.file, MRF);
 143 }
 144
 145
 146 TEST_F(register_coalesce_test, test_multiple_use)
 147 {
 148    src_reg something = src_reg(v, glsl_type::float_type);
 149    dst_reg temp = dst_reg(v, glsl_type::vec4_type);
 150    dst_reg init;
 151
 152    dst_reg m0 = dst_reg(MRF, 0);
 153    m0.writemask = WRITEMASK_X;
 154    m0.type = BRW_REGISTER_TYPE_F;
 155
 156    dst_reg m1 = dst_reg(MRF, 1);
 157    m1.writemask = WRITEMASK_XYZW;
 158    m1.type = BRW_REGISTER_TYPE_F;
 159
 160    src_reg src = src_reg(temp);
 161    vec4_instruction *mul = v->emit(v->MUL(temp, something, brw_imm_f(1.0f)));
 162    src.swizzle = BRW_SWIZZLE_XXXX;
 163    v->emit(v->MOV(m0, src));
 164    src.swizzle = BRW_SWIZZLE_XYZW;
 165    v->emit(v->MOV(m1, src));
 166
 167    register_coalesce(v);
 168
 169    EXPECT_NE(mul->dst.file, MRF);
 170 }
 171
 172 TEST_F(register_coalesce_test, test_dp4_mrf)
 173 {
 174    src_reg some_src_1 = src_reg(v, glsl_type::vec4_type);
 175    src_reg some_src_2 = src_reg(v, glsl_type::vec4_type);
 176    dst_reg init;
 177
 178    dst_reg m0 = dst_reg(MRF, 0);
 179    m0.writemask = WRITEMASK_Y;
 180    m0.type = BRW_REGISTER_TYPE_F;
 181
 182    dst_reg temp = dst_reg(v, glsl_type::float_type);
 183
 184    vec4_instruction *dp4 = v->emit(v->DP4(temp, some_src_1, some_src_2));
 185    v->emit(v->MOV(m0, src_reg(temp)));
 186
 187    register_coalesce(v);
 188
 189    EXPECT_EQ(dp4->dst.file, MRF);
 190    EXPECT_EQ(dp4->dst.writemask, WRITEMASK_Y);
 191 }
 192
 193 TEST_F(register_coalesce_test, test_dp4_grf)
 194 {
 195    src_reg some_src_1 = src_reg(v, glsl_type::vec4_type);
 196    src_reg some_src_2 = src_reg(v, glsl_type::vec4_type);
 197    dst_reg init;
 198
 199    dst_reg to = dst_reg(v, glsl_type::vec4_type);
 200    dst_reg temp = dst_reg(v, glsl_type::float_type);
 201
 202    vec4_instruction *dp4 = v->emit(v->DP4(temp, some_src_1, some_src_2));
 203    to.writemask = WRITEMASK_Y;
 204    v->emit(v->MOV(to, src_reg(temp)));
 205
 206    /* if we don't do something with the result, the automatic dead code
 207     * elimination will remove all our instructions.
 208     */
 209    src_reg src = src_reg(to);
 210    src.negate = true;
 211    v->emit(v->MOV(dst_reg(MRF, 0), src));
 212
 213    register_coalesce(v);
 214
 215    EXPECT_EQ(dp4->dst.nr, to.nr);
 216    EXPECT_EQ(dp4->dst.writemask, WRITEMASK_Y);
 217 }
 218
 219 TEST_F(register_coalesce_test, test_channel_mul_grf)
 220 {
 221    src_reg some_src_1 = src_reg(v, glsl_type::vec4_type);
 222    src_reg some_src_2 = src_reg(v, glsl_type::vec4_type);
 223    dst_reg init;
 224
 225    dst_reg to = dst_reg(v, glsl_type::vec4_type);
 226    dst_reg temp = dst_reg(v, glsl_type::float_type);
 227
 228    vec4_instruction *mul = v->emit(v->MUL(temp, some_src_1, some_src_2));
 229    to.writemask = WRITEMASK_Y;
 230    v->emit(v->MOV(to, src_reg(temp)));
 231
 232    /* if we don't do something with the result, the automatic dead code
 233     * elimination will remove all our instructions.
 234     */
 235    src_reg src = src_reg(to);
 236    src.negate = true;
 237    v->emit(v->MOV(dst_reg(MRF, 0), src));
 238
 239    register_coalesce(v);
 240
 241    EXPECT_EQ(mul->dst.nr, to.nr);
 242 }