i965/vs: Add a unit test for opt_compute_to_mrf().
[mesa.git] / src / mesa / drivers / dri / i965 / test_vec4_register_coalesce.cpp
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <gtest/gtest.h>
25 #include "brw_vec4.h"
26
27 using namespace brw;
28
29 int ret = 0;
30
31 #define register_coalesce(v) _register_coalesce(v, __FUNCTION__)
32
33 class register_coalesce_test : public ::testing::Test {
34 virtual void SetUp();
35
36 public:
37 struct brw_context *brw;
38 struct intel_context *intel;
39 struct gl_context *ctx;
40 struct gl_shader_program *shader_prog;
41 struct brw_vs_compile *c;
42 vec4_visitor *v;
43 };
44
45 void register_coalesce_test::SetUp()
46 {
47 brw = (struct brw_context *)calloc(1, sizeof(*brw));
48 intel = &brw->intel;
49 ctx = &intel->ctx;
50
51 c = ralloc(NULL, struct brw_vs_compile);
52 c->vp = ralloc(NULL, struct brw_vertex_program);
53
54 shader_prog = ralloc(NULL, struct gl_shader_program);
55
56 v = new vec4_visitor(brw, c, shader_prog, NULL, NULL);
57
58 _mesa_init_vertex_program(ctx, &c->vp->program, GL_VERTEX_SHADER, 0);
59
60 intel->gen = 4;
61 }
62
63 static void
64 _register_coalesce(vec4_visitor *v, const char *func)
65 {
66 bool print = false;
67
68 if (print) {
69 printf("%s: instructions before:\n", func);
70 v->dump_instructions();
71 }
72
73 v->opt_compute_to_mrf();
74
75 if (print) {
76 printf("%s: instructions after:\n", func);
77 v->dump_instructions();
78 }
79 }
80
81 TEST_F(register_coalesce_test, test_easy_success)
82 {
83 src_reg something = src_reg(v, glsl_type::float_type);
84 dst_reg temp = dst_reg(v, glsl_type::float_type);
85 dst_reg init;
86
87 dst_reg m0 = dst_reg(MRF, 0);
88 m0.writemask = WRITEMASK_X;
89 m0.type = BRW_REGISTER_TYPE_F;
90
91 vec4_instruction *mul = v->emit(v->MUL(temp, something, src_reg(1.0f)));
92 v->emit(v->MOV(m0, src_reg(temp)));
93
94 register_coalesce(v);
95
96 EXPECT_EQ(mul->dst.file, MRF);
97 }
98
99
100 TEST_F(register_coalesce_test, test_multiple_use)
101 {
102 src_reg something = src_reg(v, glsl_type::float_type);
103 dst_reg temp = dst_reg(v, glsl_type::vec4_type);
104 dst_reg init;
105
106 dst_reg m0 = dst_reg(MRF, 0);
107 m0.writemask = WRITEMASK_X;
108 m0.type = BRW_REGISTER_TYPE_F;
109
110 dst_reg m1 = dst_reg(MRF, 1);
111 m1.writemask = WRITEMASK_XYZW;
112 m1.type = BRW_REGISTER_TYPE_F;
113
114 src_reg src = src_reg(temp);
115 vec4_instruction *mul = v->emit(v->MUL(temp, something, src_reg(1.0f)));
116 src.swizzle = BRW_SWIZZLE_XXXX;
117 v->emit(v->MOV(m0, src));
118 src.swizzle = BRW_SWIZZLE_XYZW;
119 v->emit(v->MOV(m1, src));
120
121 register_coalesce(v);
122
123 EXPECT_NE(mul->dst.file, MRF);
124 }