src/mesa/drivers/dri/intel/intel_batchbuffer.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "intel_batchbuffer.h"
  29 #include "intel_ioctl.h"
  30 #include "intel_decode.h"
  31 #include "intel_reg.h"
  32
  33 /* Relocations in kernel space:
  34  *    - pass dma buffer seperately
  35  *    - memory manager knows how to patch
  36  *    - pass list of dependent buffers
  37  *    - pass relocation list
  38  *
  39  * Either:
  40  *    - get back an offset for buffer to fire
  41  *    - memory manager knows how to fire buffer
  42  *
  43  * Really want the buffer to be AGP and pinned.
  44  *
  45  */
  46
  47 /* Cliprect fence: The highest fence protecting a dma buffer
  48  * containing explicit cliprect information.  Like the old drawable
  49  * lock but irq-driven.  X server must wait for this fence to expire
  50  * before changing cliprects [and then doing sw rendering?].  For
  51  * other dma buffers, the scheduler will grab current cliprect info
  52  * and mix into buffer.  X server must hold the lock while changing
  53  * cliprects???  Make per-drawable.  Need cliprects in shared memory
  54  * -- beats storing them with every cmd buffer in the queue.
  55  *
  56  * ==> X server must wait for this fence to expire before touching the
  57  * framebuffer with new cliprects.
  58  *
  59  * ==> Cliprect-dependent buffers associated with a
  60  * cliprect-timestamp.  All of the buffers associated with a timestamp
  61  * must go to hardware before any buffer with a newer timestamp.
  62  *
  63  * ==> Dma should be queued per-drawable for correct X/GL
  64  * synchronization.  Or can fences be used for this?
  65  *
  66  * Applies to: Blit operations, metaops, X server operations -- X
  67  * server automatically waits on its own dma to complete before
  68  * modifying cliprects ???
  69  */
  70
  71 void
  72 intel_batchbuffer_reset(struct intel_batchbuffer *batch)
  73 {
  74    struct intel_context *intel = batch->intel;
  75
  76    if (batch->buf != NULL) {
  77       dri_bo_unreference(batch->buf);
  78       batch->buf = NULL;
  79    }
  80
  81    batch->buf = dri_bo_alloc(intel->intelScreen->bufmgr, "batchbuffer",
  82                              intel->intelScreen->maxBatchSize, 4096,
  83                              DRM_BO_FLAG_MEM_LOCAL | DRM_BO_FLAG_CACHED | DRM_BO_FLAG_CACHED_MAPPED);
  84    dri_bo_map(batch->buf, GL_TRUE);
  85    batch->map = batch->buf->virtual;
  86    batch->size = intel->intelScreen->maxBatchSize;
  87    batch->ptr = batch->map;
  88 }
  89
  90 struct intel_batchbuffer *
  91 intel_batchbuffer_alloc(struct intel_context *intel)
  92 {
  93    struct intel_batchbuffer *batch = calloc(sizeof(*batch), 1);
  94
  95    batch->intel = intel;
  96    batch->last_fence = NULL;
  97    intel_batchbuffer_reset(batch);
  98
  99    return batch;
 100 }
 101
 102 void
 103 intel_batchbuffer_free(struct intel_batchbuffer *batch)
 104 {
 105    if (batch->last_fence) {
 106       dri_fence_wait(batch->last_fence);
 107       dri_fence_unreference(batch->last_fence);
 108       batch->last_fence = NULL;
 109    }
 110    if (batch->map) {
 111       dri_bo_unmap(batch->buf);
 112       batch->map = NULL;
 113    }
 114    dri_bo_unreference(batch->buf);
 115    batch->buf = NULL;
 116    free(batch);
 117 }
 118
 119
 120
 121 /* TODO: Push this whole function into bufmgr.
 122  */
 123 static void
 124 do_flush_locked(struct intel_batchbuffer *batch,
 125                 GLuint used,
 126                 GLboolean ignore_cliprects, GLboolean allow_unlock)
 127 {
 128    struct intel_context *intel = batch->intel;
 129    void *start;
 130    GLuint count;
 131
 132    start = dri_process_relocs(batch->buf, &count);
 133
 134    batch->map = NULL;
 135    batch->ptr = NULL;
 136    batch->flags = 0;
 137
 138    /* Throw away non-effective packets.  Won't work once we have
 139     * hardware contexts which would preserve statechanges beyond a
 140     * single buffer.
 141     */
 142
 143    if (!(intel->numClipRects == 0 && !ignore_cliprects)) {
 144       if (intel->intelScreen->ttm == GL_TRUE) {
 145          intel_exec_ioctl(batch->intel,
 146                           used, ignore_cliprects, allow_unlock,
 147                           start, count, &batch->last_fence);
 148       } else {
 149          intel_batch_ioctl(batch->intel,
 150                            batch->buf->offset,
 151                            used, ignore_cliprects, allow_unlock);
 152       }
 153    }
 154
 155    dri_post_submit(batch->buf, &batch->last_fence);
 156
 157    if (intel->numClipRects == 0 && !ignore_cliprects) {
 158       if (allow_unlock) {
 159          /* If we are not doing any actual user-visible rendering,
 160           * do a sched_yield to keep the app from pegging the cpu while
 161           * achieving nothing.
 162           */
 163          UNLOCK_HARDWARE(intel);
 164          sched_yield();
 165          LOCK_HARDWARE(intel);
 166       }
 167       intel->vtbl.lost_hardware(intel);
 168    }
 169
 170    if (INTEL_DEBUG & DEBUG_BATCH) {
 171       dri_bo_map(batch->buf, GL_FALSE);
 172       intel_decode(batch->buf->virtual, used / 4, batch->buf->offset,
 173                    intel->intelScreen->deviceID);
 174       dri_bo_unmap(batch->buf);
 175    }
 176 }
 177
 178 void
 179 intel_batchbuffer_flush(struct intel_batchbuffer *batch)
 180 {
 181    struct intel_context *intel = batch->intel;
 182    GLuint used = batch->ptr - batch->map;
 183    GLboolean was_locked = intel->locked;
 184
 185    if (used == 0)
 186       return;
 187
 188    /* Add the MI_BATCH_BUFFER_END.  Always add an MI_FLUSH - this is a
 189     * performance drain that we would like to avoid.
 190     */
 191    if (used & 4) {
 192       ((int *) batch->ptr)[0] = intel->vtbl.flush_cmd();
 193       ((int *) batch->ptr)[1] = 0;
 194       ((int *) batch->ptr)[2] = MI_BATCH_BUFFER_END;
 195       used += 12;
 196    }
 197    else {
 198       ((int *) batch->ptr)[0] = intel->vtbl.flush_cmd();
 199       ((int *) batch->ptr)[1] = MI_BATCH_BUFFER_END;
 200       used += 8;
 201    }
 202
 203    /* TODO: Just pass the relocation list and dma buffer up to the
 204     * kernel.
 205     */
 206    if (!was_locked)
 207       LOCK_HARDWARE(intel);
 208
 209    do_flush_locked(batch, used, !(batch->flags & INTEL_BATCH_CLIPRECTS),
 210                    GL_FALSE);
 211
 212    if (!was_locked)
 213       UNLOCK_HARDWARE(intel);
 214
 215    if (INTEL_DEBUG & DEBUG_SYNC) {
 216       fprintf(stderr, "waiting for idle\n");
 217       if (batch->last_fence != NULL)
 218          dri_fence_wait(batch->last_fence);
 219    }
 220
 221    /* Reset the buffer:
 222     */
 223    intel_batchbuffer_reset(batch);
 224 }
 225
 226 void
 227 intel_batchbuffer_finish(struct intel_batchbuffer *batch)
 228 {
 229    intel_batchbuffer_flush(batch);
 230    if (batch->last_fence != NULL)
 231       dri_fence_wait(batch->last_fence);
 232 }
 233
 234
 235 /*  This is the only way buffers get added to the validate list.
 236  */
 237 GLboolean
 238 intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch,
 239                              dri_bo *buffer,
 240                              GLuint flags, GLuint delta)
 241 {
 242    dri_emit_reloc(batch->buf, flags, delta, batch->ptr - batch->map, buffer);
 243    batch->ptr += 4;
 244
 245    return GL_TRUE;
 246 }
 247
 248 void
 249 intel_batchbuffer_data(struct intel_batchbuffer *batch,
 250                        const void *data, GLuint bytes, GLuint flags)
 251 {
 252    assert((bytes & 3) == 0);
 253    intel_batchbuffer_require_space(batch, bytes, flags);
 254    __memcpy(batch->ptr, data, bytes);
 255    batch->ptr += bytes;
 256 }