src/mesa/drivers/dri/intel/intel_batchbuffer.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "intel_context.h"
  29 #include "intel_batchbuffer.h"
  30 #include "intel_buffer_objects.h"
  31 #include "intel_decode.h"
  32 #include "intel_reg.h"
  33 #include "intel_bufmgr.h"
  34 #include "intel_buffers.h"
  35
  36 struct cached_batch_item {
  37    struct cached_batch_item *next;
  38    uint16_t header;
  39    uint16_t size;
  40 };
  41
  42 static void clear_cache( struct intel_context *intel )
  43 {
  44    struct cached_batch_item *item = intel->batch.cached_items;
  45
  46    while (item) {
  47       struct cached_batch_item *next = item->next;
  48       free(item);
  49       item = next;
  50    }
  51
  52    intel->batch.cached_items = NULL;
  53 }
  54
  55 void
  56 intel_batchbuffer_reset(struct intel_context *intel)
  57 {
  58    if (intel->batch.last_bo != NULL) {
  59       drm_intel_bo_unreference(intel->batch.last_bo);
  60       intel->batch.last_bo = NULL;
  61    }
  62    intel->batch.last_bo = intel->batch.bo;
  63
  64    clear_cache(intel);
  65
  66    intel->batch.bo = drm_intel_bo_alloc(intel->bufmgr, "batchbuffer",
  67                                         intel->maxBatchSize, 4096);
  68
  69    intel->batch.reserved_space = BATCH_RESERVED;
  70    intel->batch.state_batch_offset = intel->batch.bo->size;
  71    intel->batch.used = 0;
  72 }
  73
  74 void
  75 intel_batchbuffer_free(struct intel_context *intel)
  76 {
  77    drm_intel_bo_unreference(intel->batch.last_bo);
  78    drm_intel_bo_unreference(intel->batch.bo);
  79    clear_cache(intel);
  80 }
  81
  82
  83 /* TODO: Push this whole function into bufmgr.
  84  */
  85 static void
  86 do_flush_locked(struct intel_context *intel)
  87 {
  88    struct intel_batchbuffer *batch = &intel->batch;
  89    int ret = 0;
  90
  91    if (!intel->intelScreen->no_hw) {
  92       int ring;
  93
  94       if (intel->gen < 6 || !batch->is_blit) {
  95          ring = I915_EXEC_RENDER;
  96       } else {
  97          ring = I915_EXEC_BLT;
  98       }
  99
 100       ret = drm_intel_bo_subdata(batch->bo, 0, 4*batch->used, batch->map);
 101       if (ret == 0 && batch->state_batch_offset != batch->bo->size) {
 102          ret = drm_intel_bo_subdata(batch->bo,
 103                                     batch->state_batch_offset,
 104                                     batch->bo->size - batch->state_batch_offset,
 105                                     (char *)batch->map + batch->state_batch_offset);
 106       }
 107
 108       if (ret == 0)
 109          ret = drm_intel_bo_mrb_exec(batch->bo, 4*batch->used, NULL, 0, 0, ring);
 110    }
 111
 112    if (unlikely(INTEL_DEBUG & DEBUG_BATCH)) {
 113       intel_decode(batch->map, batch->used,
 114                    batch->bo->offset,
 115                    intel->intelScreen->deviceID, GL_TRUE);
 116
 117       if (intel->vtbl.debug_batch != NULL)
 118          intel->vtbl.debug_batch(intel);
 119    }
 120
 121    if (ret != 0) {
 122       exit(1);
 123    }
 124    intel->vtbl.new_batch(intel);
 125 }
 126
 127 void
 128 _intel_batchbuffer_flush(struct intel_context *intel,
 129                          const char *file, int line)
 130 {
 131    if (intel->batch.used == 0)
 132       return;
 133
 134    if (intel->first_post_swapbuffers_batch == NULL) {
 135       intel->first_post_swapbuffers_batch = intel->batch.bo;
 136       drm_intel_bo_reference(intel->first_post_swapbuffers_batch);
 137    }
 138
 139    if (unlikely(INTEL_DEBUG & DEBUG_BATCH))
 140       fprintf(stderr, "%s:%d: Batchbuffer flush with %db used\n", file, line,
 141               4*intel->batch.used);
 142
 143    intel->batch.reserved_space = 0;
 144
 145    if (intel->always_flush_cache) {
 146       intel_batchbuffer_emit_mi_flush(intel);
 147    }
 148
 149    /* Mark the end of the buffer. */
 150    intel_batchbuffer_emit_dword(intel, MI_BATCH_BUFFER_END);
 151    if (intel->batch.used & 1) {
 152       /* Round batchbuffer usage to 2 DWORDs. */
 153       intel_batchbuffer_emit_dword(intel, MI_NOOP);
 154    }
 155
 156    if (intel->vtbl.finish_batch)
 157       intel->vtbl.finish_batch(intel);
 158
 159    intel_upload_finish(intel);
 160
 161    /* Check that we didn't just wrap our batchbuffer at a bad time. */
 162    assert(!intel->no_batch_wrap);
 163
 164    do_flush_locked(intel);
 165
 166    if (unlikely(INTEL_DEBUG & DEBUG_SYNC)) {
 167       fprintf(stderr, "waiting for idle\n");
 168       drm_intel_bo_wait_rendering(intel->batch.bo);
 169    }
 170
 171    /* Reset the buffer:
 172     */
 173    intel_batchbuffer_reset(intel);
 174 }
 175
 176
 177 /*  This is the only way buffers get added to the validate list.
 178  */
 179 GLboolean
 180 intel_batchbuffer_emit_reloc(struct intel_context *intel,
 181                              drm_intel_bo *buffer,
 182                              uint32_t read_domains, uint32_t write_domain,
 183                              uint32_t delta)
 184 {
 185    int ret;
 186
 187    ret = drm_intel_bo_emit_reloc(intel->batch.bo, 4*intel->batch.used,
 188                                  buffer, delta,
 189                                  read_domains, write_domain);
 190    assert(ret == 0);
 191    (void)ret;
 192
 193    /*
 194     * Using the old buffer offset, write in what the right data would be, in case
 195     * the buffer doesn't move and we can short-circuit the relocation processing
 196     * in the kernel
 197     */
 198    intel_batchbuffer_emit_dword(intel, buffer->offset + delta);
 199
 200    return GL_TRUE;
 201 }
 202
 203 GLboolean
 204 intel_batchbuffer_emit_reloc_fenced(struct intel_context *intel,
 205                                     drm_intel_bo *buffer,
 206                                     uint32_t read_domains,
 207                                     uint32_t write_domain,
 208                                     uint32_t delta)
 209 {
 210    int ret;
 211
 212    ret = drm_intel_bo_emit_reloc_fence(intel->batch.bo, 4*intel->batch.used,
 213                                        buffer, delta,
 214                                        read_domains, write_domain);
 215    assert(ret == 0);
 216    (void)ret;
 217
 218    /*
 219     * Using the old buffer offset, write in what the right data would
 220     * be, in case the buffer doesn't move and we can short-circuit the
 221     * relocation processing in the kernel
 222     */
 223    intel_batchbuffer_emit_dword(intel, buffer->offset + delta);
 224
 225    return GL_TRUE;
 226 }
 227
 228 void
 229 intel_batchbuffer_data(struct intel_context *intel,
 230                        const void *data, GLuint bytes, bool is_blit)
 231 {
 232    assert((bytes & 3) == 0);
 233    intel_batchbuffer_require_space(intel, bytes, is_blit);
 234    __memcpy(intel->batch.map + intel->batch.used, data, bytes);
 235    intel->batch.used += bytes >> 2;
 236 }
 237
 238 void
 239 intel_batchbuffer_cached_advance(struct intel_context *intel)
 240 {
 241    struct cached_batch_item **prev = &intel->batch.cached_items, *item;
 242    uint32_t sz = (intel->batch.used - intel->batch.emit) * sizeof(uint32_t);
 243    uint32_t *start = intel->batch.map + intel->batch.emit;
 244    uint16_t op = *start >> 16;
 245
 246    while (*prev) {
 247       uint32_t *old;
 248
 249       item = *prev;
 250       old = intel->batch.map + item->header;
 251       if (op == *old >> 16) {
 252          if (item->size == sz && memcmp(old, start, sz) == 0) {
 253             if (prev != &intel->batch.cached_items) {
 254                *prev = item->next;
 255                item->next = intel->batch.cached_items;
 256                intel->batch.cached_items = item;
 257             }
 258             intel->batch.used = intel->batch.emit;
 259             return;
 260          }
 261
 262          goto emit;
 263       }
 264       prev = &item->next;
 265    }
 266
 267    item = malloc(sizeof(struct cached_batch_item));
 268    if (item == NULL)
 269       return;
 270
 271    item->next = intel->batch.cached_items;
 272    intel->batch.cached_items = item;
 273
 274 emit:
 275    item->size = sz;
 276    item->header = intel->batch.emit;
 277 }
 278
 279 /* Emit a pipelined flush to either flush render and texture cache for
 280  * reading from a FBO-drawn texture, or flush so that frontbuffer
 281  * render appears on the screen in DRI1.
 282  *
 283  * This is also used for the always_flush_cache driconf debug option.
 284  */
 285 void
 286 intel_batchbuffer_emit_mi_flush(struct intel_context *intel)
 287 {
 288    if (intel->gen >= 6) {
 289       if (intel->batch.is_blit) {
 290          BEGIN_BATCH_BLT(4);
 291          OUT_BATCH(MI_FLUSH_DW);
 292          OUT_BATCH(0);
 293          OUT_BATCH(0);
 294          OUT_BATCH(0);
 295          ADVANCE_BATCH();
 296       } else {
 297          BEGIN_BATCH(8);
 298          /* XXX workaround: issue any post sync != 0 before write
 299           * cache flush = 1
 300           */
 301          OUT_BATCH(_3DSTATE_PIPE_CONTROL);
 302          OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
 303          OUT_BATCH(0); /* write address */
 304          OUT_BATCH(0); /* write data */
 305
 306          OUT_BATCH(_3DSTATE_PIPE_CONTROL);
 307          OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH |
 308                    PIPE_CONTROL_WRITE_FLUSH |
 309                    PIPE_CONTROL_DEPTH_CACHE_FLUSH |
 310                    PIPE_CONTROL_NO_WRITE);
 311          OUT_BATCH(0); /* write address */
 312          OUT_BATCH(0); /* write data */
 313          ADVANCE_BATCH();
 314       }
 315    } else if (intel->gen >= 4) {
 316       BEGIN_BATCH(4);
 317       OUT_BATCH(_3DSTATE_PIPE_CONTROL |
 318                 PIPE_CONTROL_WRITE_FLUSH |
 319                 PIPE_CONTROL_NO_WRITE);
 320       OUT_BATCH(0); /* write address */
 321       OUT_BATCH(0); /* write data */
 322       OUT_BATCH(0); /* write data */
 323       ADVANCE_BATCH();
 324    } else {
 325       BEGIN_BATCH(1);
 326       OUT_BATCH(MI_FLUSH);
 327       ADVANCE_BATCH();
 328    }
 329 }