src/mesa/drivers/dri/intel/intel_batchbuffer.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "intel_context.h"
  29 #include "intel_batchbuffer.h"
  30 #include "intel_buffer_objects.h"
  31 #include "intel_decode.h"
  32 #include "intel_reg.h"
  33 #include "intel_bufmgr.h"
  34 #include "intel_buffers.h"
  35
  36 struct cached_batch_item {
  37    struct cached_batch_item *next;
  38    uint16_t header;
  39    uint16_t size;
  40 };
  41
  42 static void clear_cache( struct intel_context *intel )
  43 {
  44    struct cached_batch_item *item = intel->batch.cached_items;
  45
  46    while (item) {
  47       struct cached_batch_item *next = item->next;
  48       free(item);
  49       item = next;
  50    }
  51
  52    intel->batch.cached_items = NULL;
  53 }
  54
  55 void
  56 intel_batchbuffer_reset(struct intel_context *intel)
  57 {
  58    if (intel->batch.bo != NULL) {
  59       drm_intel_bo_unreference(intel->batch.bo);
  60       intel->batch.bo = NULL;
  61    }
  62    clear_cache(intel);
  63
  64    intel->batch.bo = drm_intel_bo_alloc(intel->bufmgr, "batchbuffer",
  65                                         intel->maxBatchSize, 4096);
  66
  67    intel->batch.reserved_space = BATCH_RESERVED;
  68    intel->batch.state_batch_offset = intel->batch.bo->size;
  69    intel->batch.used = 0;
  70 }
  71
  72 void
  73 intel_batchbuffer_free(struct intel_context *intel)
  74 {
  75    drm_intel_bo_unreference(intel->batch.bo);
  76    clear_cache(intel);
  77 }
  78
  79
  80 /* TODO: Push this whole function into bufmgr.
  81  */
  82 static void
  83 do_flush_locked(struct intel_context *intel)
  84 {
  85    struct intel_batchbuffer *batch = &intel->batch;
  86    int ret = 0;
  87
  88    if (!intel->intelScreen->no_hw) {
  89       int ring;
  90
  91       if (intel->gen < 6 || !batch->is_blit) {
  92          ring = I915_EXEC_RENDER;
  93       } else {
  94          ring = I915_EXEC_BLT;
  95       }
  96
  97       ret = drm_intel_bo_subdata(batch->bo, 0, 4*batch->used, batch->map);
  98       if (ret == 0 && batch->state_batch_offset != batch->bo->size) {
  99          ret = drm_intel_bo_subdata(batch->bo,
 100                                     batch->state_batch_offset,
 101                                     batch->bo->size - batch->state_batch_offset,
 102                                     (char *)batch->map + batch->state_batch_offset);
 103       }
 104
 105       if (ret == 0)
 106          ret = drm_intel_bo_mrb_exec(batch->bo, 4*batch->used, NULL, 0, 0, ring);
 107    }
 108
 109    if (unlikely(INTEL_DEBUG & DEBUG_BATCH)) {
 110       intel_decode(batch->map, batch->used,
 111                    batch->bo->offset,
 112                    intel->intelScreen->deviceID, GL_TRUE);
 113
 114       if (intel->vtbl.debug_batch != NULL)
 115          intel->vtbl.debug_batch(intel);
 116    }
 117
 118    if (ret != 0) {
 119       exit(1);
 120    }
 121    intel->vtbl.new_batch(intel);
 122 }
 123
 124 void
 125 _intel_batchbuffer_flush(struct intel_context *intel,
 126                          const char *file, int line)
 127 {
 128    if (intel->batch.used == 0)
 129       return;
 130
 131    if (unlikely(INTEL_DEBUG & DEBUG_BATCH))
 132       fprintf(stderr, "%s:%d: Batchbuffer flush with %db used\n", file, line,
 133               4*intel->batch.used);
 134
 135    intel->batch.reserved_space = 0;
 136
 137    if (intel->always_flush_cache) {
 138       intel_batchbuffer_emit_mi_flush(intel);
 139    }
 140
 141    /* Mark the end of the buffer. */
 142    intel_batchbuffer_emit_dword(intel, MI_BATCH_BUFFER_END);
 143    if (intel->batch.used & 1) {
 144       /* Round batchbuffer usage to 2 DWORDs. */
 145       intel_batchbuffer_emit_dword(intel, MI_NOOP);
 146    }
 147
 148    if (intel->vtbl.finish_batch)
 149       intel->vtbl.finish_batch(intel);
 150
 151    intel_upload_finish(intel);
 152
 153    /* Check that we didn't just wrap our batchbuffer at a bad time. */
 154    assert(!intel->no_batch_wrap);
 155
 156    do_flush_locked(intel);
 157
 158    if (unlikely(INTEL_DEBUG & DEBUG_SYNC)) {
 159       fprintf(stderr, "waiting for idle\n");
 160       drm_intel_bo_wait_rendering(intel->batch.bo);
 161    }
 162
 163    /* Reset the buffer:
 164     */
 165    intel_batchbuffer_reset(intel);
 166 }
 167
 168
 169 /*  This is the only way buffers get added to the validate list.
 170  */
 171 GLboolean
 172 intel_batchbuffer_emit_reloc(struct intel_context *intel,
 173                              drm_intel_bo *buffer,
 174                              uint32_t read_domains, uint32_t write_domain,
 175                              uint32_t delta)
 176 {
 177    int ret;
 178
 179    assert(delta < buffer->size);
 180
 181    ret = drm_intel_bo_emit_reloc(intel->batch.bo, 4*intel->batch.used,
 182                                  buffer, delta,
 183                                  read_domains, write_domain);
 184    assert(ret == 0);
 185    (void)ret;
 186
 187    /*
 188     * Using the old buffer offset, write in what the right data would be, in case
 189     * the buffer doesn't move and we can short-circuit the relocation processing
 190     * in the kernel
 191     */
 192    intel_batchbuffer_emit_dword(intel, buffer->offset + delta);
 193
 194    return GL_TRUE;
 195 }
 196
 197 GLboolean
 198 intel_batchbuffer_emit_reloc_fenced(struct intel_context *intel,
 199                                     drm_intel_bo *buffer,
 200                                     uint32_t read_domains,
 201                                     uint32_t write_domain,
 202                                     uint32_t delta)
 203 {
 204    int ret;
 205
 206    assert(delta < buffer->size);
 207
 208    ret = drm_intel_bo_emit_reloc_fence(intel->batch.bo, 4*intel->batch.used,
 209                                        buffer, delta,
 210                                        read_domains, write_domain);
 211    assert(ret == 0);
 212    (void)ret;
 213
 214    /*
 215     * Using the old buffer offset, write in what the right data would
 216     * be, in case the buffer doesn't move and we can short-circuit the
 217     * relocation processing in the kernel
 218     */
 219    intel_batchbuffer_emit_dword(intel, buffer->offset + delta);
 220
 221    return GL_TRUE;
 222 }
 223
 224 void
 225 intel_batchbuffer_data(struct intel_context *intel,
 226                        const void *data, GLuint bytes, bool is_blit)
 227 {
 228    assert((bytes & 3) == 0);
 229    intel_batchbuffer_require_space(intel, bytes, is_blit);
 230    __memcpy(intel->batch.map + intel->batch.used, data, bytes);
 231    intel->batch.used += bytes >> 2;
 232 }
 233
 234 void
 235 intel_batchbuffer_cached_advance(struct intel_context *intel)
 236 {
 237    struct cached_batch_item **prev = &intel->batch.cached_items, *item;
 238    uint32_t sz = (intel->batch.used - intel->batch.emit) * sizeof(uint32_t);
 239    uint32_t *start = intel->batch.map + intel->batch.emit;
 240    uint16_t op = *start >> 16;
 241
 242    while (*prev) {
 243       uint32_t *old;
 244
 245       item = *prev;
 246       old = intel->batch.map + item->header;
 247       if (op == *old >> 16) {
 248          if (item->size == sz && memcmp(old, start, sz) == 0) {
 249             if (prev != &intel->batch.cached_items) {
 250                *prev = item->next;
 251                item->next = intel->batch.cached_items;
 252                intel->batch.cached_items = item;
 253             }
 254             intel->batch.used = intel->batch.emit;
 255             return;
 256          }
 257
 258          goto emit;
 259       }
 260       prev = &item->next;
 261    }
 262
 263    item = malloc(sizeof(struct cached_batch_item));
 264    if (item == NULL)
 265       return;
 266
 267    item->next = intel->batch.cached_items;
 268    intel->batch.cached_items = item;
 269
 270 emit:
 271    item->size = sz;
 272    item->header = intel->batch.emit;
 273 }
 274
 275 /* Emit a pipelined flush to either flush render and texture cache for
 276  * reading from a FBO-drawn texture, or flush so that frontbuffer
 277  * render appears on the screen in DRI1.
 278  *
 279  * This is also used for the always_flush_cache driconf debug option.
 280  */
 281 void
 282 intel_batchbuffer_emit_mi_flush(struct intel_context *intel)
 283 {
 284    if (intel->gen >= 6) {
 285       if (intel->batch.is_blit) {
 286          BEGIN_BATCH_BLT(4);
 287          OUT_BATCH(MI_FLUSH_DW);
 288          OUT_BATCH(0);
 289          OUT_BATCH(0);
 290          OUT_BATCH(0);
 291          ADVANCE_BATCH();
 292       } else {
 293          BEGIN_BATCH(8);
 294          /* XXX workaround: issue any post sync != 0 before write
 295           * cache flush = 1
 296           */
 297          OUT_BATCH(_3DSTATE_PIPE_CONTROL);
 298          OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
 299          OUT_BATCH(0); /* write address */
 300          OUT_BATCH(0); /* write data */
 301
 302          OUT_BATCH(_3DSTATE_PIPE_CONTROL);
 303          OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH |
 304                    PIPE_CONTROL_WRITE_FLUSH |
 305                    PIPE_CONTROL_DEPTH_CACHE_FLUSH |
 306                    PIPE_CONTROL_NO_WRITE);
 307          OUT_BATCH(0); /* write address */
 308          OUT_BATCH(0); /* write data */
 309          ADVANCE_BATCH();
 310       }
 311    } else if (intel->gen >= 4) {
 312       BEGIN_BATCH(4);
 313       OUT_BATCH(_3DSTATE_PIPE_CONTROL |
 314                 PIPE_CONTROL_WRITE_FLUSH |
 315                 PIPE_CONTROL_NO_WRITE);
 316       OUT_BATCH(0); /* write address */
 317       OUT_BATCH(0); /* write data */
 318       OUT_BATCH(0); /* write data */
 319       ADVANCE_BATCH();
 320    } else {
 321       BEGIN_BATCH(1);
 322       OUT_BATCH(MI_FLUSH);
 323       ADVANCE_BATCH();
 324    }
 325 }