src/mesa/drivers/dri/intel/intel_batchbuffer.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "intel_context.h"
  29 #include "intel_batchbuffer.h"
  30 #include "intel_buffer_objects.h"
  31 #include "intel_decode.h"
  32 #include "intel_reg.h"
  33 #include "intel_bufmgr.h"
  34 #include "intel_buffers.h"
  35
  36 void
  37 intel_batchbuffer_reset(struct intel_context *intel)
  38 {
  39    if (intel->batch.bo != NULL) {
  40       drm_intel_bo_unreference(intel->batch.bo);
  41       intel->batch.bo = NULL;
  42    }
  43
  44    intel->batch.bo = drm_intel_bo_alloc(intel->bufmgr, "batchbuffer",
  45                                         intel->maxBatchSize, 4096);
  46
  47    intel->batch.reserved_space = BATCH_RESERVED;
  48    intel->batch.state_batch_offset = intel->batch.bo->size;
  49    intel->batch.used = 0;
  50 }
  51
  52 void
  53 intel_batchbuffer_free(struct intel_context *intel)
  54 {
  55    drm_intel_bo_unreference(intel->batch.bo);
  56 }
  57
  58
  59 /* TODO: Push this whole function into bufmgr.
  60  */
  61 static void
  62 do_flush_locked(struct intel_context *intel)
  63 {
  64    struct intel_batchbuffer *batch = &intel->batch;
  65    int ret = 0;
  66
  67    if (!intel->intelScreen->no_hw) {
  68       int ring;
  69
  70       if (intel->gen < 6 || !batch->is_blit) {
  71          ring = I915_EXEC_RENDER;
  72       } else {
  73          ring = I915_EXEC_BLT;
  74       }
  75
  76       ret = drm_intel_bo_subdata(batch->bo, 0, 4*batch->used, batch->map);
  77       if (ret == 0 && batch->state_batch_offset != batch->bo->size) {
  78          ret = drm_intel_bo_subdata(batch->bo,
  79                                     batch->state_batch_offset,
  80                                     batch->bo->size - batch->state_batch_offset,
  81                                     (char *)batch->map + batch->state_batch_offset);
  82       }
  83
  84       if (ret == 0)
  85          ret = drm_intel_bo_mrb_exec(batch->bo, 4*batch->used, NULL, 0, 0, ring);
  86    }
  87
  88    if (unlikely(INTEL_DEBUG & DEBUG_BATCH)) {
  89       intel_decode(batch->map, batch->used,
  90                    batch->bo->offset,
  91                    intel->intelScreen->deviceID, GL_TRUE);
  92
  93       if (intel->vtbl.debug_batch != NULL)
  94          intel->vtbl.debug_batch(intel);
  95    }
  96
  97    if (ret != 0) {
  98       exit(1);
  99    }
 100    intel->vtbl.new_batch(intel);
 101 }
 102
 103 void
 104 _intel_batchbuffer_flush(struct intel_context *intel,
 105                          const char *file, int line)
 106 {
 107    if (intel->batch.used == 0)
 108       return;
 109
 110    if (intel->first_post_swapbuffers_batch == NULL) {
 111       intel->first_post_swapbuffers_batch = intel->batch.bo;
 112       drm_intel_bo_reference(intel->first_post_swapbuffers_batch);
 113    }
 114
 115    if (unlikely(INTEL_DEBUG & DEBUG_BATCH))
 116       fprintf(stderr, "%s:%d: Batchbuffer flush with %db used\n", file, line,
 117               4*intel->batch.used);
 118
 119    intel->batch.reserved_space = 0;
 120
 121    if (intel->always_flush_cache) {
 122       intel_batchbuffer_emit_mi_flush(intel);
 123    }
 124
 125    /* Mark the end of the buffer. */
 126    intel_batchbuffer_emit_dword(intel, MI_BATCH_BUFFER_END);
 127    if (intel->batch.used & 1) {
 128       /* Round batchbuffer usage to 2 DWORDs. */
 129       intel_batchbuffer_emit_dword(intel, MI_NOOP);
 130    }
 131
 132    if (intel->vtbl.finish_batch)
 133       intel->vtbl.finish_batch(intel);
 134
 135    intel_upload_finish(intel);
 136
 137    /* Check that we didn't just wrap our batchbuffer at a bad time. */
 138    assert(!intel->no_batch_wrap);
 139
 140    do_flush_locked(intel);
 141
 142    if (unlikely(INTEL_DEBUG & DEBUG_SYNC)) {
 143       fprintf(stderr, "waiting for idle\n");
 144       drm_intel_bo_wait_rendering(intel->batch.bo);
 145    }
 146
 147    /* Reset the buffer:
 148     */
 149    intel_batchbuffer_reset(intel);
 150 }
 151
 152
 153 /*  This is the only way buffers get added to the validate list.
 154  */
 155 GLboolean
 156 intel_batchbuffer_emit_reloc(struct intel_context *intel,
 157                              drm_intel_bo *buffer,
 158                              uint32_t read_domains, uint32_t write_domain,
 159                              uint32_t delta)
 160 {
 161    int ret;
 162
 163    assert(delta < buffer->size);
 164
 165    ret = drm_intel_bo_emit_reloc(intel->batch.bo, 4*intel->batch.used,
 166                                  buffer, delta,
 167                                  read_domains, write_domain);
 168    assert (ret == 0);
 169
 170    /*
 171     * Using the old buffer offset, write in what the right data would be, in case
 172     * the buffer doesn't move and we can short-circuit the relocation processing
 173     * in the kernel
 174     */
 175    intel_batchbuffer_emit_dword(intel, buffer->offset + delta);
 176
 177    return GL_TRUE;
 178 }
 179
 180 GLboolean
 181 intel_batchbuffer_emit_reloc_fenced(struct intel_context *intel,
 182                                     drm_intel_bo *buffer,
 183                                     uint32_t read_domains,
 184                                     uint32_t write_domain,
 185                                     uint32_t delta)
 186 {
 187    int ret;
 188
 189    assert(delta < buffer->size);
 190
 191    ret = drm_intel_bo_emit_reloc_fence(intel->batch.bo, 4*intel->batch.used,
 192                                        buffer, delta,
 193                                        read_domains, write_domain);
 194    assert (ret == 0);
 195
 196    /*
 197     * Using the old buffer offset, write in what the right data would
 198     * be, in case the buffer doesn't move and we can short-circuit the
 199     * relocation processing in the kernel
 200     */
 201    intel_batchbuffer_emit_dword(intel, buffer->offset + delta);
 202
 203    return GL_TRUE;
 204 }
 205
 206 void
 207 intel_batchbuffer_data(struct intel_context *intel,
 208                        const void *data, GLuint bytes, bool is_blit)
 209 {
 210    assert((bytes & 3) == 0);
 211    intel_batchbuffer_require_space(intel, bytes, is_blit);
 212    __memcpy(intel->batch.map + intel->batch.used, data, bytes);
 213    intel->batch.used += bytes >> 2;
 214 }
 215
 216 /* Emit a pipelined flush to either flush render and texture cache for
 217  * reading from a FBO-drawn texture, or flush so that frontbuffer
 218  * render appears on the screen in DRI1.
 219  *
 220  * This is also used for the always_flush_cache driconf debug option.
 221  */
 222 void
 223 intel_batchbuffer_emit_mi_flush(struct intel_context *intel)
 224 {
 225    if (intel->gen >= 6) {
 226       if (intel->batch.is_blit) {
 227          BEGIN_BATCH_BLT(4);
 228          OUT_BATCH(MI_FLUSH_DW);
 229          OUT_BATCH(0);
 230          OUT_BATCH(0);
 231          OUT_BATCH(0);
 232          ADVANCE_BATCH();
 233       } else {
 234          BEGIN_BATCH(8);
 235          /* XXX workaround: issue any post sync != 0 before write
 236           * cache flush = 1
 237           */
 238          OUT_BATCH(_3DSTATE_PIPE_CONTROL);
 239          OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
 240          OUT_BATCH(0); /* write address */
 241          OUT_BATCH(0); /* write data */
 242
 243          OUT_BATCH(_3DSTATE_PIPE_CONTROL);
 244          OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH |
 245                    PIPE_CONTROL_WRITE_FLUSH |
 246                    PIPE_CONTROL_DEPTH_CACHE_FLUSH |
 247                    PIPE_CONTROL_NO_WRITE);
 248          OUT_BATCH(0); /* write address */
 249          OUT_BATCH(0); /* write data */
 250          ADVANCE_BATCH();
 251       }
 252    } else if (intel->gen >= 4) {
 253       BEGIN_BATCH(4);
 254       OUT_BATCH(_3DSTATE_PIPE_CONTROL |
 255                 PIPE_CONTROL_WRITE_FLUSH |
 256                 PIPE_CONTROL_NO_WRITE);
 257       OUT_BATCH(0); /* write address */
 258       OUT_BATCH(0); /* write data */
 259       OUT_BATCH(0); /* write data */
 260       ADVANCE_BATCH();
 261    } else {
 262       BEGIN_BATCH(1);
 263       OUT_BATCH(MI_FLUSH);
 264       ADVANCE_BATCH();
 265    }
 266 }