1 /**************************************************************************
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include "intel_context.h"
29 #include "intel_batchbuffer.h"
30 #include "intel_buffer_objects.h"
31 #include "intel_decode.h"
32 #include "intel_reg.h"
33 #include "intel_bufmgr.h"
34 #include "intel_buffers.h"
36 struct cached_batch_item
{
37 struct cached_batch_item
*next
;
42 static void clear_cache( struct intel_context
*intel
)
44 struct cached_batch_item
*item
= intel
->batch
.cached_items
;
47 struct cached_batch_item
*next
= item
->next
;
52 intel
->batch
.cached_items
= NULL
;
56 intel_batchbuffer_reset(struct intel_context
*intel
)
58 if (intel
->batch
.last_bo
!= NULL
) {
59 drm_intel_bo_unreference(intel
->batch
.last_bo
);
60 intel
->batch
.last_bo
= NULL
;
62 intel
->batch
.last_bo
= intel
->batch
.bo
;
66 intel
->batch
.bo
= drm_intel_bo_alloc(intel
->bufmgr
, "batchbuffer",
67 intel
->maxBatchSize
, 4096);
69 intel
->batch
.reserved_space
= BATCH_RESERVED
;
70 intel
->batch
.state_batch_offset
= intel
->batch
.bo
->size
;
71 intel
->batch
.used
= 0;
75 intel_batchbuffer_free(struct intel_context
*intel
)
77 drm_intel_bo_unreference(intel
->batch
.last_bo
);
78 drm_intel_bo_unreference(intel
->batch
.bo
);
83 /* TODO: Push this whole function into bufmgr.
86 do_flush_locked(struct intel_context
*intel
)
88 struct intel_batchbuffer
*batch
= &intel
->batch
;
91 if (!intel
->intelScreen
->no_hw
) {
94 if (intel
->gen
< 6 || !batch
->is_blit
) {
95 ring
= I915_EXEC_RENDER
;
100 ret
= drm_intel_bo_subdata(batch
->bo
, 0, 4*batch
->used
, batch
->map
);
101 if (ret
== 0 && batch
->state_batch_offset
!= batch
->bo
->size
) {
102 ret
= drm_intel_bo_subdata(batch
->bo
,
103 batch
->state_batch_offset
,
104 batch
->bo
->size
- batch
->state_batch_offset
,
105 (char *)batch
->map
+ batch
->state_batch_offset
);
109 ret
= drm_intel_bo_mrb_exec(batch
->bo
, 4*batch
->used
, NULL
, 0, 0, ring
);
112 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
113 intel_decode(batch
->map
, batch
->used
,
115 intel
->intelScreen
->deviceID
, GL_TRUE
);
117 if (intel
->vtbl
.debug_batch
!= NULL
)
118 intel
->vtbl
.debug_batch(intel
);
124 intel
->vtbl
.new_batch(intel
);
128 _intel_batchbuffer_flush(struct intel_context
*intel
,
129 const char *file
, int line
)
131 if (intel
->batch
.used
== 0)
134 if (intel
->first_post_swapbuffers_batch
== NULL
) {
135 intel
->first_post_swapbuffers_batch
= intel
->batch
.bo
;
136 drm_intel_bo_reference(intel
->first_post_swapbuffers_batch
);
139 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
))
140 fprintf(stderr
, "%s:%d: Batchbuffer flush with %db used\n", file
, line
,
141 4*intel
->batch
.used
);
143 intel
->batch
.reserved_space
= 0;
145 if (intel
->always_flush_cache
) {
146 intel_batchbuffer_emit_mi_flush(intel
);
149 /* Mark the end of the buffer. */
150 intel_batchbuffer_emit_dword(intel
, MI_BATCH_BUFFER_END
);
151 if (intel
->batch
.used
& 1) {
152 /* Round batchbuffer usage to 2 DWORDs. */
153 intel_batchbuffer_emit_dword(intel
, MI_NOOP
);
156 if (intel
->vtbl
.finish_batch
)
157 intel
->vtbl
.finish_batch(intel
);
159 intel_upload_finish(intel
);
161 /* Check that we didn't just wrap our batchbuffer at a bad time. */
162 assert(!intel
->no_batch_wrap
);
164 do_flush_locked(intel
);
166 if (unlikely(INTEL_DEBUG
& DEBUG_SYNC
)) {
167 fprintf(stderr
, "waiting for idle\n");
168 drm_intel_bo_wait_rendering(intel
->batch
.bo
);
173 intel_batchbuffer_reset(intel
);
177 /* This is the only way buffers get added to the validate list.
180 intel_batchbuffer_emit_reloc(struct intel_context
*intel
,
181 drm_intel_bo
*buffer
,
182 uint32_t read_domains
, uint32_t write_domain
,
187 ret
= drm_intel_bo_emit_reloc(intel
->batch
.bo
, 4*intel
->batch
.used
,
189 read_domains
, write_domain
);
194 * Using the old buffer offset, write in what the right data would be, in case
195 * the buffer doesn't move and we can short-circuit the relocation processing
198 intel_batchbuffer_emit_dword(intel
, buffer
->offset
+ delta
);
204 intel_batchbuffer_emit_reloc_fenced(struct intel_context
*intel
,
205 drm_intel_bo
*buffer
,
206 uint32_t read_domains
,
207 uint32_t write_domain
,
212 ret
= drm_intel_bo_emit_reloc_fence(intel
->batch
.bo
, 4*intel
->batch
.used
,
214 read_domains
, write_domain
);
219 * Using the old buffer offset, write in what the right data would
220 * be, in case the buffer doesn't move and we can short-circuit the
221 * relocation processing in the kernel
223 intel_batchbuffer_emit_dword(intel
, buffer
->offset
+ delta
);
229 intel_batchbuffer_data(struct intel_context
*intel
,
230 const void *data
, GLuint bytes
, bool is_blit
)
232 assert((bytes
& 3) == 0);
233 intel_batchbuffer_require_space(intel
, bytes
, is_blit
);
234 __memcpy(intel
->batch
.map
+ intel
->batch
.used
, data
, bytes
);
235 intel
->batch
.used
+= bytes
>> 2;
239 intel_batchbuffer_cached_advance(struct intel_context
*intel
)
241 struct cached_batch_item
**prev
= &intel
->batch
.cached_items
, *item
;
242 uint32_t sz
= (intel
->batch
.used
- intel
->batch
.emit
) * sizeof(uint32_t);
243 uint32_t *start
= intel
->batch
.map
+ intel
->batch
.emit
;
244 uint16_t op
= *start
>> 16;
250 old
= intel
->batch
.map
+ item
->header
;
251 if (op
== *old
>> 16) {
252 if (item
->size
== sz
&& memcmp(old
, start
, sz
) == 0) {
253 if (prev
!= &intel
->batch
.cached_items
) {
255 item
->next
= intel
->batch
.cached_items
;
256 intel
->batch
.cached_items
= item
;
258 intel
->batch
.used
= intel
->batch
.emit
;
267 item
= malloc(sizeof(struct cached_batch_item
));
271 item
->next
= intel
->batch
.cached_items
;
272 intel
->batch
.cached_items
= item
;
276 item
->header
= intel
->batch
.emit
;
280 intel_emit_post_sync_nonzero_flush(struct intel_context
*intel
)
283 OUT_BATCH(_3DSTATE_PIPE_CONTROL
);
284 OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE
);
285 OUT_BATCH(0); /* write address */
286 OUT_BATCH(0); /* write data */
290 /* Emit a pipelined flush to either flush render and texture cache for
291 * reading from a FBO-drawn texture, or flush so that frontbuffer
292 * render appears on the screen in DRI1.
294 * This is also used for the always_flush_cache driconf debug option.
297 intel_batchbuffer_emit_mi_flush(struct intel_context
*intel
)
299 if (intel
->gen
>= 6) {
300 if (intel
->batch
.is_blit
) {
302 OUT_BATCH(MI_FLUSH_DW
);
308 if (intel
->gen
== 6) {
309 /* Hardware workaround: SNB B-Spec says:
311 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache
312 * Flush Enable =1, a PIPE_CONTROL with any non-zero
313 * post-sync-op is required.
315 intel_emit_post_sync_nonzero_flush(intel
);
319 OUT_BATCH(_3DSTATE_PIPE_CONTROL
);
320 OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH
|
321 PIPE_CONTROL_WRITE_FLUSH
|
322 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
323 PIPE_CONTROL_NO_WRITE
);
324 OUT_BATCH(0); /* write address */
325 OUT_BATCH(0); /* write data */
328 } else if (intel
->gen
>= 4) {
330 OUT_BATCH(_3DSTATE_PIPE_CONTROL
|
331 PIPE_CONTROL_WRITE_FLUSH
|
332 PIPE_CONTROL_NO_WRITE
);
333 OUT_BATCH(0); /* write address */
334 OUT_BATCH(0); /* write data */
335 OUT_BATCH(0); /* write data */