src/mesa/drivers/dri/intel/intel_batchbuffer.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "intel_context.h"
  29 #include "intel_batchbuffer.h"
  30 #include "intel_decode.h"
  31 #include "intel_reg.h"
  32 #include "intel_bufmgr.h"
  33 #include "intel_buffers.h"
  34
  35 void
  36 intel_batchbuffer_reset(struct intel_batchbuffer *batch)
  37 {
  38    struct intel_context *intel = batch->intel;
  39
  40    if (batch->buf != NULL) {
  41       dri_bo_unreference(batch->buf);
  42       batch->buf = NULL;
  43    }
  44
  45    if (!batch->buffer)
  46       batch->buffer = malloc (intel->maxBatchSize);
  47
  48    batch->buf = dri_bo_alloc(intel->bufmgr, "batchbuffer",
  49                              intel->maxBatchSize, 4096);
  50    if (batch->buffer)
  51       batch->map = batch->buffer;
  52    else {
  53       dri_bo_map(batch->buf, GL_TRUE);
  54       batch->map = batch->buf->virtual;
  55    }
  56    batch->size = intel->maxBatchSize;
  57    batch->ptr = batch->map;
  58    batch->reserved_space = BATCH_RESERVED;
  59    batch->dirty_state = ~0;
  60 }
  61
  62 struct intel_batchbuffer *
  63 intel_batchbuffer_alloc(struct intel_context *intel)
  64 {
  65    struct intel_batchbuffer *batch = calloc(sizeof(*batch), 1);
  66
  67    batch->intel = intel;
  68    intel_batchbuffer_reset(batch);
  69
  70    return batch;
  71 }
  72
  73 void
  74 intel_batchbuffer_free(struct intel_batchbuffer *batch)
  75 {
  76    if (batch->buffer)
  77       free (batch->buffer);
  78    else {
  79       if (batch->map) {
  80          dri_bo_unmap(batch->buf);
  81          batch->map = NULL;
  82       }
  83    }
  84    dri_bo_unreference(batch->buf);
  85    batch->buf = NULL;
  86    free(batch);
  87 }
  88
  89
  90
  91 /* TODO: Push this whole function into bufmgr.
  92  */
  93 static void
  94 do_flush_locked(struct intel_batchbuffer *batch, GLuint used)
  95 {
  96    struct intel_context *intel = batch->intel;
  97    int ret = 0;
  98    int x_off = 0, y_off = 0;
  99
 100    if (batch->buffer)
 101       dri_bo_subdata (batch->buf, 0, used, batch->buffer);
 102    else
 103       dri_bo_unmap(batch->buf);
 104
 105    batch->map = NULL;
 106    batch->ptr = NULL;
 107
 108    if (!intel->no_hw)
 109       dri_bo_exec(batch->buf, used, NULL, 0, (x_off & 0xffff) | (y_off << 16));
 110
 111    if (INTEL_DEBUG & DEBUG_BATCH) {
 112       dri_bo_map(batch->buf, GL_FALSE);
 113       intel_decode(batch->buf->virtual, used / 4, batch->buf->offset,
 114                    intel->intelScreen->deviceID);
 115       dri_bo_unmap(batch->buf);
 116
 117       if (intel->vtbl.debug_batch != NULL)
 118          intel->vtbl.debug_batch(intel);
 119    }
 120
 121    if (ret != 0) {
 122       exit(1);
 123    }
 124    intel->vtbl.new_batch(intel);
 125 }
 126
 127 void
 128 _intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file,
 129                          int line)
 130 {
 131    struct intel_context *intel = batch->intel;
 132    GLuint used = batch->ptr - batch->map;
 133
 134    if (intel->first_post_swapbuffers_batch == NULL) {
 135       intel->first_post_swapbuffers_batch = intel->batch->buf;
 136       drm_intel_bo_reference(intel->first_post_swapbuffers_batch);
 137    }
 138
 139    if (used == 0)
 140       return;
 141
 142    if (INTEL_DEBUG & DEBUG_BATCH)
 143       fprintf(stderr, "%s:%d: Batchbuffer flush with %db used\n", file, line,
 144               used);
 145
 146    batch->reserved_space = 0;
 147    /* Emit a flush if the bufmgr doesn't do it for us. */
 148    if (intel->always_flush_cache) {
 149       intel_batchbuffer_emit_mi_flush(batch);
 150       used = batch->ptr - batch->map;
 151    }
 152
 153    /* Round batchbuffer usage to 2 DWORDs. */
 154
 155    if ((used & 4) == 0) {
 156       *(GLuint *) (batch->ptr) = 0; /* noop */
 157       batch->ptr += 4;
 158       used = batch->ptr - batch->map;
 159    }
 160
 161    /* Mark the end of the buffer. */
 162    *(GLuint *) (batch->ptr) = MI_BATCH_BUFFER_END;
 163    batch->ptr += 4;
 164    used = batch->ptr - batch->map;
 165    assert (used <= batch->buf->size);
 166
 167    /* Workaround for recursive batchbuffer flushing: If the window is
 168     * moved, we can get into a case where we try to flush during a
 169     * flush.  What happens is that when we try to grab the lock for
 170     * the first flush, we detect that the window moved which then
 171     * causes another flush (from the intel_draw_buffer() call in
 172     * intelUpdatePageFlipping()).  To work around this we reset the
 173     * batchbuffer tail pointer before trying to get the lock.  This
 174     * prevent the nested buffer flush, but a better fix would be to
 175     * avoid that in the first place. */
 176    batch->ptr = batch->map;
 177
 178    if (intel->vtbl.finish_batch)
 179       intel->vtbl.finish_batch(intel);
 180
 181    /* Check that we didn't just wrap our batchbuffer at a bad time. */
 182    assert(!intel->no_batch_wrap);
 183
 184    /* TODO: Just pass the relocation list and dma buffer up to the
 185     * kernel.
 186     */
 187    do_flush_locked(batch, used);
 188
 189    if (INTEL_DEBUG & DEBUG_SYNC) {
 190       fprintf(stderr, "waiting for idle\n");
 191       dri_bo_map(batch->buf, GL_TRUE);
 192       dri_bo_unmap(batch->buf);
 193    }
 194
 195    /* Reset the buffer:
 196     */
 197    intel_batchbuffer_reset(batch);
 198 }
 199
 200
 201 /*  This is the only way buffers get added to the validate list.
 202  */
 203 GLboolean
 204 intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch,
 205                              dri_bo *buffer,
 206                              uint32_t read_domains, uint32_t write_domain,
 207                              uint32_t delta)
 208 {
 209    int ret;
 210
 211    assert(delta < buffer->size);
 212
 213    if (batch->ptr - batch->map > batch->buf->size)
 214     printf ("bad relocation ptr %p map %p offset %d size %lu\n",
 215             batch->ptr, batch->map, batch->ptr - batch->map, batch->buf->size);
 216    ret = dri_bo_emit_reloc(batch->buf, read_domains, write_domain,
 217                            delta, batch->ptr - batch->map, buffer);
 218
 219    /*
 220     * Using the old buffer offset, write in what the right data would be, in case
 221     * the buffer doesn't move and we can short-circuit the relocation processing
 222     * in the kernel
 223     */
 224    intel_batchbuffer_emit_dword (batch, buffer->offset + delta);
 225
 226    return GL_TRUE;
 227 }
 228
 229 GLboolean
 230 intel_batchbuffer_emit_reloc_fenced(struct intel_batchbuffer *batch,
 231                                     drm_intel_bo *buffer,
 232                                     uint32_t read_domains, uint32_t write_domain,
 233                                     uint32_t delta)
 234 {
 235    int ret;
 236
 237    assert(delta < buffer->size);
 238
 239    if (batch->ptr - batch->map > batch->buf->size)
 240     printf ("bad relocation ptr %p map %p offset %d size %lu\n",
 241             batch->ptr, batch->map, batch->ptr - batch->map, batch->buf->size);
 242    ret = drm_intel_bo_emit_reloc_fence(batch->buf, batch->ptr - batch->map,
 243                                        buffer, delta,
 244                                        read_domains, write_domain);
 245
 246    /*
 247     * Using the old buffer offset, write in what the right data would
 248     * be, in case the buffer doesn't move and we can short-circuit the
 249     * relocation processing in the kernel
 250     */
 251    intel_batchbuffer_emit_dword (batch, buffer->offset + delta);
 252
 253    return GL_TRUE;
 254 }
 255
 256 void
 257 intel_batchbuffer_data(struct intel_batchbuffer *batch,
 258                        const void *data, GLuint bytes)
 259 {
 260    assert((bytes & 3) == 0);
 261    intel_batchbuffer_require_space(batch, bytes);
 262    __memcpy(batch->ptr, data, bytes);
 263    batch->ptr += bytes;
 264 }
 265
 266 /* Emit a pipelined flush to either flush render and texture cache for
 267  * reading from a FBO-drawn texture, or flush so that frontbuffer
 268  * render appears on the screen in DRI1.
 269  *
 270  * This is also used for the always_flush_cache driconf debug option.
 271  */
 272 void
 273 intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch)
 274 {
 275    struct intel_context *intel = batch->intel;
 276
 277    if (intel->gen >= 6) {
 278       BEGIN_BATCH(4);
 279       OUT_BATCH(_3DSTATE_PIPE_CONTROL);
 280       OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH |
 281                 PIPE_CONTROL_WRITE_FLUSH |
 282                 PIPE_CONTROL_NO_WRITE);
 283       OUT_BATCH(0); /* write address */
 284       OUT_BATCH(0); /* write data */
 285       ADVANCE_BATCH();
 286    } else if (intel->gen >= 4) {
 287       BEGIN_BATCH(4);
 288       OUT_BATCH(_3DSTATE_PIPE_CONTROL |
 289                 PIPE_CONTROL_WRITE_FLUSH |
 290                 PIPE_CONTROL_NO_WRITE);
 291       OUT_BATCH(0); /* write address */
 292       OUT_BATCH(0); /* write data */
 293       OUT_BATCH(0); /* write data */
 294       ADVANCE_BATCH();
 295    } else {
 296       BEGIN_BATCH(1);
 297       OUT_BATCH(MI_FLUSH);
 298       ADVANCE_BATCH();
 299    }
 300 }