src/mesa/drivers/dri/intel/intel_batchbuffer.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "intel_context.h"
  29 #include "intel_batchbuffer.h"
  30 #include "intel_decode.h"
  31 #include "intel_reg.h"
  32 #include "intel_bufmgr.h"
  33 #include "intel_buffers.h"
  34
  35 void
  36 intel_batchbuffer_reset(struct intel_batchbuffer *batch)
  37 {
  38    struct intel_context *intel = batch->intel;
  39
  40    if (batch->buf != NULL) {
  41       drm_intel_bo_unreference(batch->buf);
  42       batch->buf = NULL;
  43    }
  44
  45    batch->buf = drm_intel_bo_alloc(intel->bufmgr, "batchbuffer",
  46                                    intel->maxBatchSize, 4096);
  47    drm_intel_gem_bo_map_gtt(batch->buf);
  48    batch->map = batch->buf->virtual;
  49
  50    batch->size = intel->maxBatchSize;
  51    batch->ptr = batch->map;
  52    batch->reserved_space = BATCH_RESERVED;
  53    batch->dirty_state = ~0;
  54    batch->state_batch_offset = batch->size;
  55 }
  56
  57 struct intel_batchbuffer *
  58 intel_batchbuffer_alloc(struct intel_context *intel)
  59 {
  60    struct intel_batchbuffer *batch = calloc(sizeof(*batch), 1);
  61
  62    batch->intel = intel;
  63    intel_batchbuffer_reset(batch);
  64
  65    return batch;
  66 }
  67
  68 void
  69 intel_batchbuffer_free(struct intel_batchbuffer *batch)
  70 {
  71    if (batch->map) {
  72       drm_intel_gem_bo_unmap_gtt(batch->buf);
  73       batch->map = NULL;
  74    }
  75    dri_bo_unreference(batch->buf);
  76    batch->buf = NULL;
  77    free(batch);
  78 }
  79
  80
  81
  82 /* TODO: Push this whole function into bufmgr.
  83  */
  84 static void
  85 do_flush_locked(struct intel_batchbuffer *batch, GLuint used)
  86 {
  87    struct intel_context *intel = batch->intel;
  88    int ret = 0;
  89    int x_off = 0, y_off = 0;
  90
  91    drm_intel_gem_bo_unmap_gtt(batch->buf);
  92
  93    batch->ptr = NULL;
  94
  95    if (!intel->intelScreen->no_hw) {
  96       int ring;
  97
  98       if (intel->gen < 6 || !intel->batch->is_blit) {
  99          ring = I915_EXEC_RENDER;
 100       } else {
 101          ring = I915_EXEC_BLT;
 102       }
 103
 104       drm_intel_bo_mrb_exec(batch->buf, used, NULL, 0,
 105                             (x_off & 0xffff) | (y_off << 16), ring);
 106    }
 107
 108    if (unlikely(INTEL_DEBUG & DEBUG_BATCH)) {
 109       drm_intel_bo_map(batch->buf, GL_FALSE);
 110       intel_decode(batch->buf->virtual, used / 4, batch->buf->offset,
 111                    intel->intelScreen->deviceID, GL_TRUE);
 112       drm_intel_bo_unmap(batch->buf);
 113
 114       if (intel->vtbl.debug_batch != NULL)
 115          intel->vtbl.debug_batch(intel);
 116    }
 117
 118    if (ret != 0) {
 119       exit(1);
 120    }
 121    intel->vtbl.new_batch(intel);
 122 }
 123
 124 void
 125 _intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file,
 126                          int line)
 127 {
 128    struct intel_context *intel = batch->intel;
 129    GLuint used = batch->ptr - batch->map;
 130
 131    if (intel->first_post_swapbuffers_batch == NULL) {
 132       intel->first_post_swapbuffers_batch = intel->batch->buf;
 133       drm_intel_bo_reference(intel->first_post_swapbuffers_batch);
 134    }
 135
 136    if (used == 0)
 137       return;
 138
 139    if (unlikely(INTEL_DEBUG & DEBUG_BATCH))
 140       fprintf(stderr, "%s:%d: Batchbuffer flush with %db used\n", file, line,
 141               used);
 142
 143    batch->reserved_space = 0;
 144
 145    if (intel->always_flush_cache) {
 146       intel_batchbuffer_emit_mi_flush(batch);
 147       used = batch->ptr - batch->map;
 148    }
 149
 150    /* Round batchbuffer usage to 2 DWORDs. */
 151
 152    if ((used & 4) == 0) {
 153       *(GLuint *) (batch->ptr) = 0; /* noop */
 154       batch->ptr += 4;
 155       used = batch->ptr - batch->map;
 156    }
 157
 158    /* Mark the end of the buffer. */
 159    *(GLuint *) (batch->ptr) = MI_BATCH_BUFFER_END;
 160    batch->ptr += 4;
 161    used = batch->ptr - batch->map;
 162    assert (used <= batch->buf->size);
 163
 164    /* Workaround for recursive batchbuffer flushing: If the window is
 165     * moved, we can get into a case where we try to flush during a
 166     * flush.  What happens is that when we try to grab the lock for
 167     * the first flush, we detect that the window moved which then
 168     * causes another flush (from the intel_draw_buffer() call in
 169     * intelUpdatePageFlipping()).  To work around this we reset the
 170     * batchbuffer tail pointer before trying to get the lock.  This
 171     * prevent the nested buffer flush, but a better fix would be to
 172     * avoid that in the first place. */
 173    batch->ptr = batch->map;
 174
 175    if (intel->vtbl.finish_batch)
 176       intel->vtbl.finish_batch(intel);
 177
 178    if (intel->upload.bo) {
 179       drm_intel_bo_unreference(intel->upload.bo);
 180       intel->upload.bo = NULL;
 181       intel->upload.offset = 0;
 182    }
 183
 184    /* Check that we didn't just wrap our batchbuffer at a bad time. */
 185    assert(!intel->no_batch_wrap);
 186
 187    do_flush_locked(batch, used);
 188
 189    if (unlikely(INTEL_DEBUG & DEBUG_SYNC)) {
 190       fprintf(stderr, "waiting for idle\n");
 191       drm_intel_bo_map(batch->buf, GL_TRUE);
 192       drm_intel_bo_unmap(batch->buf);
 193    }
 194
 195    /* Reset the buffer:
 196     */
 197    intel_batchbuffer_reset(batch);
 198 }
 199
 200
 201 /*  This is the only way buffers get added to the validate list.
 202  */
 203 GLboolean
 204 intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch,
 205                              drm_intel_bo *buffer,
 206                              uint32_t read_domains, uint32_t write_domain,
 207                              uint32_t delta)
 208 {
 209    int ret;
 210
 211    assert(delta < buffer->size);
 212
 213    if (batch->ptr - batch->map > batch->buf->size)
 214     printf ("bad relocation ptr %p map %p offset %d size %lu\n",
 215             batch->ptr, batch->map, batch->ptr - batch->map, batch->buf->size);
 216    ret = drm_intel_bo_emit_reloc(batch->buf, batch->ptr - batch->map,
 217                                  buffer, delta,
 218                                  read_domains, write_domain);
 219
 220    /*
 221     * Using the old buffer offset, write in what the right data would be, in case
 222     * the buffer doesn't move and we can short-circuit the relocation processing
 223     * in the kernel
 224     */
 225    intel_batchbuffer_emit_dword (batch, buffer->offset + delta);
 226
 227    return GL_TRUE;
 228 }
 229
 230 GLboolean
 231 intel_batchbuffer_emit_reloc_fenced(struct intel_batchbuffer *batch,
 232                                     drm_intel_bo *buffer,
 233                                     uint32_t read_domains, uint32_t write_domain,
 234                                     uint32_t delta)
 235 {
 236    int ret;
 237
 238    assert(delta < buffer->size);
 239
 240    if (batch->ptr - batch->map > batch->buf->size)
 241     printf ("bad relocation ptr %p map %p offset %d size %lu\n",
 242             batch->ptr, batch->map, batch->ptr - batch->map, batch->buf->size);
 243    ret = drm_intel_bo_emit_reloc_fence(batch->buf, batch->ptr - batch->map,
 244                                        buffer, delta,
 245                                        read_domains, write_domain);
 246
 247    /*
 248     * Using the old buffer offset, write in what the right data would
 249     * be, in case the buffer doesn't move and we can short-circuit the
 250     * relocation processing in the kernel
 251     */
 252    intel_batchbuffer_emit_dword (batch, buffer->offset + delta);
 253
 254    return GL_TRUE;
 255 }
 256
 257 void
 258 intel_batchbuffer_data(struct intel_batchbuffer *batch,
 259                        const void *data, GLuint bytes, bool is_blit)
 260 {
 261    assert((bytes & 3) == 0);
 262    intel_batchbuffer_require_space(batch, bytes, is_blit);
 263    __memcpy(batch->ptr, data, bytes);
 264    batch->ptr += bytes;
 265 }
 266
 267 /* Emit a pipelined flush to either flush render and texture cache for
 268  * reading from a FBO-drawn texture, or flush so that frontbuffer
 269  * render appears on the screen in DRI1.
 270  *
 271  * This is also used for the always_flush_cache driconf debug option.
 272  */
 273 void
 274 intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch)
 275 {
 276    struct intel_context *intel = batch->intel;
 277
 278    if (intel->gen >= 6) {
 279       if (intel->batch->is_blit) {
 280          BEGIN_BATCH_BLT(4);
 281          OUT_BATCH(MI_FLUSH_DW);
 282          OUT_BATCH(0);
 283          OUT_BATCH(0);
 284          OUT_BATCH(0);
 285          ADVANCE_BATCH();
 286       } else {
 287          BEGIN_BATCH(8);
 288          /* XXX workaround: issue any post sync != 0 before write
 289           * cache flush = 1
 290           */
 291          OUT_BATCH(_3DSTATE_PIPE_CONTROL);
 292          OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
 293          OUT_BATCH(0); /* write address */
 294          OUT_BATCH(0); /* write data */
 295
 296          OUT_BATCH(_3DSTATE_PIPE_CONTROL);
 297          OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH |
 298                    PIPE_CONTROL_WRITE_FLUSH |
 299                    PIPE_CONTROL_DEPTH_CACHE_FLUSH |
 300                    PIPE_CONTROL_NO_WRITE);
 301          OUT_BATCH(0); /* write address */
 302          OUT_BATCH(0); /* write data */
 303          ADVANCE_BATCH();
 304       }
 305    } else if (intel->gen >= 4) {
 306       BEGIN_BATCH(4);
 307       OUT_BATCH(_3DSTATE_PIPE_CONTROL |
 308                 PIPE_CONTROL_WRITE_FLUSH |
 309                 PIPE_CONTROL_NO_WRITE);
 310       OUT_BATCH(0); /* write address */
 311       OUT_BATCH(0); /* write data */
 312       OUT_BATCH(0); /* write data */
 313       ADVANCE_BATCH();
 314    } else {
 315       BEGIN_BATCH(1);
 316       OUT_BATCH(MI_FLUSH);
 317       ADVANCE_BATCH();
 318    }
 319 }