src/mesa/drivers/dri/intel/intel_batchbuffer.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "intel_context.h"
  29 #include "intel_batchbuffer.h"
  30 #include "intel_buffer_objects.h"
  31 #include "intel_decode.h"
  32 #include "intel_reg.h"
  33 #include "intel_bufmgr.h"
  34 #include "intel_buffers.h"
  35
  36 struct cached_batch_item {
  37    struct cached_batch_item *next;
  38    uint16_t header;
  39    uint16_t size;
  40 };
  41
  42 static void clear_cache( struct intel_context *intel )
  43 {
  44    struct cached_batch_item *item = intel->batch.cached_items;
  45
  46    while (item) {
  47       struct cached_batch_item *next = item->next;
  48       free(item);
  49       item = next;
  50    }
  51
  52    intel->batch.cached_items = NULL;
  53 }
  54
  55 void
  56 intel_batchbuffer_reset(struct intel_context *intel)
  57 {
  58    if (intel->batch.bo != NULL) {
  59       drm_intel_bo_unreference(intel->batch.bo);
  60       intel->batch.bo = NULL;
  61    }
  62    clear_cache(intel);
  63
  64    intel->batch.bo = drm_intel_bo_alloc(intel->bufmgr, "batchbuffer",
  65                                         intel->maxBatchSize, 4096);
  66
  67    intel->batch.reserved_space = BATCH_RESERVED;
  68    intel->batch.state_batch_offset = intel->batch.bo->size;
  69    intel->batch.used = 0;
  70 }
  71
  72 void
  73 intel_batchbuffer_free(struct intel_context *intel)
  74 {
  75    drm_intel_bo_unreference(intel->batch.bo);
  76    clear_cache(intel);
  77 }
  78
  79
  80 /* TODO: Push this whole function into bufmgr.
  81  */
  82 static void
  83 do_flush_locked(struct intel_context *intel)
  84 {
  85    struct intel_batchbuffer *batch = &intel->batch;
  86    int ret = 0;
  87
  88    if (!intel->intelScreen->no_hw) {
  89       int ring;
  90
  91       if (intel->gen < 6 || !batch->is_blit) {
  92          ring = I915_EXEC_RENDER;
  93       } else {
  94          ring = I915_EXEC_BLT;
  95       }
  96
  97       ret = drm_intel_bo_subdata(batch->bo, 0, 4*batch->used, batch->map);
  98       if (ret == 0 && batch->state_batch_offset != batch->bo->size) {
  99          ret = drm_intel_bo_subdata(batch->bo,
 100                                     batch->state_batch_offset,
 101                                     batch->bo->size - batch->state_batch_offset,
 102                                     (char *)batch->map + batch->state_batch_offset);
 103       }
 104
 105       if (ret == 0)
 106          ret = drm_intel_bo_mrb_exec(batch->bo, 4*batch->used, NULL, 0, 0, ring);
 107    }
 108
 109    if (unlikely(INTEL_DEBUG & DEBUG_BATCH)) {
 110       intel_decode(batch->map, batch->used,
 111                    batch->bo->offset,
 112                    intel->intelScreen->deviceID, GL_TRUE);
 113
 114       if (intel->vtbl.debug_batch != NULL)
 115          intel->vtbl.debug_batch(intel);
 116    }
 117
 118    if (ret != 0) {
 119       exit(1);
 120    }
 121    intel->vtbl.new_batch(intel);
 122 }
 123
 124 void
 125 _intel_batchbuffer_flush(struct intel_context *intel,
 126                          const char *file, int line)
 127 {
 128    if (intel->batch.used == 0)
 129       return;
 130
 131    if (unlikely(INTEL_DEBUG & DEBUG_BATCH))
 132       fprintf(stderr, "%s:%d: Batchbuffer flush with %db used\n", file, line,
 133               4*intel->batch.used);
 134
 135    intel->batch.reserved_space = 0;
 136
 137    if (intel->always_flush_cache) {
 138       intel_batchbuffer_emit_mi_flush(intel);
 139    }
 140
 141    /* Mark the end of the buffer. */
 142    intel_batchbuffer_emit_dword(intel, MI_BATCH_BUFFER_END);
 143    if (intel->batch.used & 1) {
 144       /* Round batchbuffer usage to 2 DWORDs. */
 145       intel_batchbuffer_emit_dword(intel, MI_NOOP);
 146    }
 147
 148    if (intel->vtbl.finish_batch)
 149       intel->vtbl.finish_batch(intel);
 150
 151    intel_upload_finish(intel);
 152
 153    /* Check that we didn't just wrap our batchbuffer at a bad time. */
 154    assert(!intel->no_batch_wrap);
 155
 156    do_flush_locked(intel);
 157
 158    if (unlikely(INTEL_DEBUG & DEBUG_SYNC)) {
 159       fprintf(stderr, "waiting for idle\n");
 160       drm_intel_bo_wait_rendering(intel->batch.bo);
 161    }
 162
 163    /* Reset the buffer:
 164     */
 165    intel_batchbuffer_reset(intel);
 166 }
 167
 168
 169 /*  This is the only way buffers get added to the validate list.
 170  */
 171 GLboolean
 172 intel_batchbuffer_emit_reloc(struct intel_context *intel,
 173                              drm_intel_bo *buffer,
 174                              uint32_t read_domains, uint32_t write_domain,
 175                              uint32_t delta)
 176 {
 177    int ret;
 178
 179    ret = drm_intel_bo_emit_reloc(intel->batch.bo, 4*intel->batch.used,
 180                                  buffer, delta,
 181                                  read_domains, write_domain);
 182    assert(ret == 0);
 183    (void)ret;
 184
 185    /*
 186     * Using the old buffer offset, write in what the right data would be, in case
 187     * the buffer doesn't move and we can short-circuit the relocation processing
 188     * in the kernel
 189     */
 190    intel_batchbuffer_emit_dword(intel, buffer->offset + delta);
 191
 192    return GL_TRUE;
 193 }
 194
 195 GLboolean
 196 intel_batchbuffer_emit_reloc_fenced(struct intel_context *intel,
 197                                     drm_intel_bo *buffer,
 198                                     uint32_t read_domains,
 199                                     uint32_t write_domain,
 200                                     uint32_t delta)
 201 {
 202    int ret;
 203
 204    ret = drm_intel_bo_emit_reloc_fence(intel->batch.bo, 4*intel->batch.used,
 205                                        buffer, delta,
 206                                        read_domains, write_domain);
 207    assert(ret == 0);
 208    (void)ret;
 209
 210    /*
 211     * Using the old buffer offset, write in what the right data would
 212     * be, in case the buffer doesn't move and we can short-circuit the
 213     * relocation processing in the kernel
 214     */
 215    intel_batchbuffer_emit_dword(intel, buffer->offset + delta);
 216
 217    return GL_TRUE;
 218 }
 219
 220 void
 221 intel_batchbuffer_data(struct intel_context *intel,
 222                        const void *data, GLuint bytes, bool is_blit)
 223 {
 224    assert((bytes & 3) == 0);
 225    intel_batchbuffer_require_space(intel, bytes, is_blit);
 226    __memcpy(intel->batch.map + intel->batch.used, data, bytes);
 227    intel->batch.used += bytes >> 2;
 228 }
 229
 230 void
 231 intel_batchbuffer_cached_advance(struct intel_context *intel)
 232 {
 233    struct cached_batch_item **prev = &intel->batch.cached_items, *item;
 234    uint32_t sz = (intel->batch.used - intel->batch.emit) * sizeof(uint32_t);
 235    uint32_t *start = intel->batch.map + intel->batch.emit;
 236    uint16_t op = *start >> 16;
 237
 238    while (*prev) {
 239       uint32_t *old;
 240
 241       item = *prev;
 242       old = intel->batch.map + item->header;
 243       if (op == *old >> 16) {
 244          if (item->size == sz && memcmp(old, start, sz) == 0) {
 245             if (prev != &intel->batch.cached_items) {
 246                *prev = item->next;
 247                item->next = intel->batch.cached_items;
 248                intel->batch.cached_items = item;
 249             }
 250             intel->batch.used = intel->batch.emit;
 251             return;
 252          }
 253
 254          goto emit;
 255       }
 256       prev = &item->next;
 257    }
 258
 259    item = malloc(sizeof(struct cached_batch_item));
 260    if (item == NULL)
 261       return;
 262
 263    item->next = intel->batch.cached_items;
 264    intel->batch.cached_items = item;
 265
 266 emit:
 267    item->size = sz;
 268    item->header = intel->batch.emit;
 269 }
 270
 271 /* Emit a pipelined flush to either flush render and texture cache for
 272  * reading from a FBO-drawn texture, or flush so that frontbuffer
 273  * render appears on the screen in DRI1.
 274  *
 275  * This is also used for the always_flush_cache driconf debug option.
 276  */
 277 void
 278 intel_batchbuffer_emit_mi_flush(struct intel_context *intel)
 279 {
 280    if (intel->gen >= 6) {
 281       if (intel->batch.is_blit) {
 282          BEGIN_BATCH_BLT(4);
 283          OUT_BATCH(MI_FLUSH_DW);
 284          OUT_BATCH(0);
 285          OUT_BATCH(0);
 286          OUT_BATCH(0);
 287          ADVANCE_BATCH();
 288       } else {
 289          BEGIN_BATCH(8);
 290          /* XXX workaround: issue any post sync != 0 before write
 291           * cache flush = 1
 292           */
 293          OUT_BATCH(_3DSTATE_PIPE_CONTROL);
 294          OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
 295          OUT_BATCH(0); /* write address */
 296          OUT_BATCH(0); /* write data */
 297
 298          OUT_BATCH(_3DSTATE_PIPE_CONTROL);
 299          OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH |
 300                    PIPE_CONTROL_WRITE_FLUSH |
 301                    PIPE_CONTROL_DEPTH_CACHE_FLUSH |
 302                    PIPE_CONTROL_NO_WRITE);
 303          OUT_BATCH(0); /* write address */
 304          OUT_BATCH(0); /* write data */
 305          ADVANCE_BATCH();
 306       }
 307    } else if (intel->gen >= 4) {
 308       BEGIN_BATCH(4);
 309       OUT_BATCH(_3DSTATE_PIPE_CONTROL |
 310                 PIPE_CONTROL_WRITE_FLUSH |
 311                 PIPE_CONTROL_NO_WRITE);
 312       OUT_BATCH(0); /* write address */
 313       OUT_BATCH(0); /* write data */
 314       OUT_BATCH(0); /* write data */
 315       ADVANCE_BATCH();
 316    } else {
 317       BEGIN_BATCH(1);
 318       OUT_BATCH(MI_FLUSH);
 319       ADVANCE_BATCH();
 320    }
 321 }