src/mesa/drivers/dri/intel/intel_blit.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29 #include "main/mtypes.h"
  30 #include "main/context.h"
  31 #include "main/enums.h"
  32 #include "main/colormac.h"
  33
  34 #include "intel_blit.h"
  35 #include "intel_buffers.h"
  36 #include "intel_context.h"
  37 #include "intel_fbo.h"
  38 #include "intel_reg.h"
  39 #include "intel_regions.h"
  40 #include "intel_batchbuffer.h"
  41 #include "intel_mipmap_tree.h"
  42
  43 #define FILE_DEBUG_FLAG DEBUG_BLIT
  44
  45 static GLuint translate_raster_op(GLenum logicop)
  46 {
  47    switch(logicop) {
  48    case GL_CLEAR: return 0x00;
  49    case GL_AND: return 0x88;
  50    case GL_AND_REVERSE: return 0x44;
  51    case GL_COPY: return 0xCC;
  52    case GL_AND_INVERTED: return 0x22;
  53    case GL_NOOP: return 0xAA;
  54    case GL_XOR: return 0x66;
  55    case GL_OR: return 0xEE;
  56    case GL_NOR: return 0x11;
  57    case GL_EQUIV: return 0x99;
  58    case GL_INVERT: return 0x55;
  59    case GL_OR_REVERSE: return 0xDD;
  60    case GL_COPY_INVERTED: return 0x33;
  61    case GL_OR_INVERTED: return 0xBB;
  62    case GL_NAND: return 0x77;
  63    case GL_SET: return 0xFF;
  64    default: return 0;
  65    }
  66 }
  67
  68 static uint32_t
  69 br13_for_cpp(int cpp)
  70 {
  71    switch (cpp) {
  72    case 4:
  73       return BR13_8888;
  74       break;
  75    case 2:
  76       return BR13_565;
  77       break;
  78    case 1:
  79       return BR13_8;
  80       break;
  81    default:
  82       assert(0);
  83       return 0;
  84    }
  85 }
  86
  87 /* Copy BitBlt
  88  */
  89 GLboolean
  90 intelEmitCopyBlit(struct intel_context *intel,
  91                   GLuint cpp,
  92                   GLshort src_pitch,
  93                   drm_intel_bo *src_buffer,
  94                   GLuint src_offset,
  95                   uint32_t src_tiling,
  96                   GLshort dst_pitch,
  97                   drm_intel_bo *dst_buffer,
  98                   GLuint dst_offset,
  99                   uint32_t dst_tiling,
 100                   GLshort src_x, GLshort src_y,
 101                   GLshort dst_x, GLshort dst_y,
 102                   GLshort w, GLshort h,
 103                   GLenum logic_op)
 104 {
 105    GLuint CMD, BR13, pass = 0;
 106    int dst_y2 = dst_y + h;
 107    int dst_x2 = dst_x + w;
 108    drm_intel_bo *aper_array[3];
 109    BATCH_LOCALS;
 110
 111    if (dst_tiling != I915_TILING_NONE) {
 112       if (dst_offset & 4095)
 113          return GL_FALSE;
 114       if (dst_tiling == I915_TILING_Y)
 115          return GL_FALSE;
 116    }
 117    if (src_tiling != I915_TILING_NONE) {
 118       if (src_offset & 4095)
 119          return GL_FALSE;
 120       if (src_tiling == I915_TILING_Y)
 121          return GL_FALSE;
 122    }
 123
 124    /* do space check before going any further */
 125    do {
 126        aper_array[0] = intel->batch->buf;
 127        aper_array[1] = dst_buffer;
 128        aper_array[2] = src_buffer;
 129
 130        if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
 131            intel_batchbuffer_flush(intel->batch);
 132            pass++;
 133        } else
 134            break;
 135    } while (pass < 2);
 136
 137    if (pass >= 2)
 138       return GL_FALSE;
 139
 140    intel_batchbuffer_require_space(intel->batch, 8 * 4, true);
 141    DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
 142        __FUNCTION__,
 143        src_buffer, src_pitch, src_offset, src_x, src_y,
 144        dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
 145
 146    src_pitch *= cpp;
 147    dst_pitch *= cpp;
 148
 149    BR13 = br13_for_cpp(cpp) | translate_raster_op(logic_op) << 16;
 150
 151    switch (cpp) {
 152    case 1:
 153    case 2:
 154       CMD = XY_SRC_COPY_BLT_CMD;
 155       break;
 156    case 4:
 157       CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 158       break;
 159    default:
 160       return GL_FALSE;
 161    }
 162
 163 #ifndef I915
 164    if (dst_tiling != I915_TILING_NONE) {
 165       CMD |= XY_DST_TILED;
 166       dst_pitch /= 4;
 167    }
 168    if (src_tiling != I915_TILING_NONE) {
 169       CMD |= XY_SRC_TILED;
 170       src_pitch /= 4;
 171    }
 172 #endif
 173
 174    if (dst_y2 <= dst_y || dst_x2 <= dst_x) {
 175       return GL_TRUE;
 176    }
 177
 178    assert(dst_x < dst_x2);
 179    assert(dst_y < dst_y2);
 180
 181    BEGIN_BATCH_BLT(8);
 182    OUT_BATCH(CMD);
 183    OUT_BATCH(BR13 | (uint16_t)dst_pitch);
 184    OUT_BATCH((dst_y << 16) | dst_x);
 185    OUT_BATCH((dst_y2 << 16) | dst_x2);
 186    OUT_RELOC_FENCED(dst_buffer,
 187                     I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 188                     dst_offset);
 189    OUT_BATCH((src_y << 16) | src_x);
 190    OUT_BATCH((uint16_t)src_pitch);
 191    OUT_RELOC_FENCED(src_buffer,
 192                     I915_GEM_DOMAIN_RENDER, 0,
 193                     src_offset);
 194    ADVANCE_BATCH();
 195
 196    intel_batchbuffer_emit_mi_flush(intel->batch);
 197
 198    return GL_TRUE;
 199 }
 200
 201
 202 /**
 203  * Use blitting to clear the renderbuffers named by 'flags'.
 204  * Note: we can't use the ctx->DrawBuffer->_ColorDrawBufferIndexes field
 205  * since that might include software renderbuffers or renderbuffers
 206  * which we're clearing with triangles.
 207  * \param mask  bitmask of BUFFER_BIT_* values indicating buffers to clear
 208  */
 209 void
 210 intelClearWithBlit(struct gl_context *ctx, GLbitfield mask)
 211 {
 212    struct intel_context *intel = intel_context(ctx);
 213    struct gl_framebuffer *fb = ctx->DrawBuffer;
 214    GLuint clear_depth;
 215    GLboolean all;
 216    GLint cx, cy, cw, ch;
 217    BATCH_LOCALS;
 218
 219    /*
 220     * Compute values for clearing the buffers.
 221     */
 222    clear_depth = 0;
 223    if (mask & BUFFER_BIT_DEPTH) {
 224       clear_depth = (GLuint) (fb->_DepthMax * ctx->Depth.Clear);
 225    }
 226    if (mask & BUFFER_BIT_STENCIL) {
 227       clear_depth |= (ctx->Stencil.Clear & 0xff) << 24;
 228    }
 229
 230    cx = fb->_Xmin;
 231    if (fb->Name == 0)
 232       cy = ctx->DrawBuffer->Height - fb->_Ymax;
 233    else
 234       cy = fb->_Ymin;
 235    cw = fb->_Xmax - fb->_Xmin;
 236    ch = fb->_Ymax - fb->_Ymin;
 237
 238    if (cw == 0 || ch == 0)
 239       return;
 240
 241    GLuint buf;
 242    all = (cw == fb->Width && ch == fb->Height);
 243
 244    /* Loop over all renderbuffers */
 245    for (buf = 0; buf < BUFFER_COUNT && mask; buf++) {
 246       const GLbitfield bufBit = 1 << buf;
 247       struct intel_renderbuffer *irb;
 248       drm_intel_bo *write_buffer;
 249       int x1, y1, x2, y2;
 250       uint32_t clear_val;
 251       uint32_t BR13, CMD;
 252       int pitch, cpp;
 253       drm_intel_bo *aper_array[2];
 254
 255       if (!(mask & bufBit))
 256          continue;
 257
 258       /* OK, clear this renderbuffer */
 259       irb = intel_get_renderbuffer(fb, buf);
 260       write_buffer = intel_region_buffer(intel, irb->region,
 261                                          all ? INTEL_WRITE_FULL :
 262                                          INTEL_WRITE_PART);
 263       x1 = cx + irb->region->draw_x;
 264       y1 = cy + irb->region->draw_y;
 265       x2 = cx + cw + irb->region->draw_x;
 266       y2 = cy + ch + irb->region->draw_y;
 267
 268       pitch = irb->region->pitch;
 269       cpp = irb->region->cpp;
 270
 271       DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
 272           __FUNCTION__,
 273           irb->region->buffer, (pitch * cpp),
 274           x1, y1, x2 - x1, y2 - y1);
 275
 276       BR13 = br13_for_cpp(cpp) | 0xf0 << 16;
 277       CMD = XY_COLOR_BLT_CMD;
 278
 279       /* Setup the blit command */
 280       if (cpp == 4) {
 281          if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) {
 282             if (mask & BUFFER_BIT_DEPTH)
 283                CMD |= XY_BLT_WRITE_RGB;
 284             if (mask & BUFFER_BIT_STENCIL)
 285                CMD |= XY_BLT_WRITE_ALPHA;
 286          } else {
 287             /* clearing RGBA */
 288             CMD |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 289          }
 290       }
 291
 292       assert(irb->region->tiling != I915_TILING_Y);
 293
 294 #ifndef I915
 295       if (irb->region->tiling != I915_TILING_NONE) {
 296          CMD |= XY_DST_TILED;
 297          pitch /= 4;
 298       }
 299 #endif
 300       BR13 |= (pitch * cpp);
 301
 302       if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) {
 303          clear_val = clear_depth;
 304       } else {
 305          uint8_t clear[4];
 306          GLclampf *color = ctx->Color.ClearColor;
 307
 308          CLAMPED_FLOAT_TO_UBYTE(clear[0], color[0]);
 309          CLAMPED_FLOAT_TO_UBYTE(clear[1], color[1]);
 310          CLAMPED_FLOAT_TO_UBYTE(clear[2], color[2]);
 311          CLAMPED_FLOAT_TO_UBYTE(clear[3], color[3]);
 312
 313          switch (irb->Base.Format) {
 314          case MESA_FORMAT_ARGB8888:
 315          case MESA_FORMAT_XRGB8888:
 316             clear_val = PACK_COLOR_8888(clear[3], clear[0],
 317                                         clear[1], clear[2]);
 318             break;
 319          case MESA_FORMAT_RGB565:
 320             clear_val = PACK_COLOR_565(clear[0], clear[1], clear[2]);
 321             break;
 322          case MESA_FORMAT_ARGB4444:
 323             clear_val = PACK_COLOR_4444(clear[3], clear[0],
 324                                         clear[1], clear[2]);
 325             break;
 326          case MESA_FORMAT_ARGB1555:
 327             clear_val = PACK_COLOR_1555(clear[3], clear[0],
 328                                         clear[1], clear[2]);
 329             break;
 330          case MESA_FORMAT_A8:
 331             clear_val = PACK_COLOR_8888(clear[3], clear[3],
 332                                         clear[3], clear[3]);
 333             break;
 334          default:
 335             _mesa_problem(ctx, "Unexpected renderbuffer format: %d\n",
 336                           irb->Base.Format);
 337             clear_val = 0;
 338          }
 339       }
 340
 341       assert(x1 < x2);
 342       assert(y1 < y2);
 343
 344       /* do space check before going any further */
 345       aper_array[0] = intel->batch->buf;
 346       aper_array[1] = write_buffer;
 347
 348       if (drm_intel_bufmgr_check_aperture_space(aper_array,
 349                                                 ARRAY_SIZE(aper_array)) != 0) {
 350          intel_batchbuffer_flush(intel->batch);
 351       }
 352
 353       BEGIN_BATCH_BLT(6);
 354       OUT_BATCH(CMD);
 355       OUT_BATCH(BR13);
 356       OUT_BATCH((y1 << 16) | x1);
 357       OUT_BATCH((y2 << 16) | x2);
 358       OUT_RELOC_FENCED(write_buffer,
 359                        I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 360                        0);
 361       OUT_BATCH(clear_val);
 362       ADVANCE_BATCH();
 363
 364       if (intel->always_flush_cache)
 365          intel_batchbuffer_emit_mi_flush(intel->batch);
 366
 367       if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL)
 368          mask &= ~(BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL);
 369       else
 370          mask &= ~bufBit;    /* turn off bit, for faster loop exit */
 371    }
 372 }
 373
 374 GLboolean
 375 intelEmitImmediateColorExpandBlit(struct intel_context *intel,
 376                                   GLuint cpp,
 377                                   GLubyte *src_bits, GLuint src_size,
 378                                   GLuint fg_color,
 379                                   GLshort dst_pitch,
 380                                   drm_intel_bo *dst_buffer,
 381                                   GLuint dst_offset,
 382                                   uint32_t dst_tiling,
 383                                   GLshort x, GLshort y,
 384                                   GLshort w, GLshort h,
 385                                   GLenum logic_op)
 386 {
 387    int dwords = ALIGN(src_size, 8) / 4;
 388    uint32_t opcode, br13, blit_cmd;
 389
 390    if (dst_tiling != I915_TILING_NONE) {
 391       if (dst_offset & 4095)
 392          return GL_FALSE;
 393       if (dst_tiling == I915_TILING_Y)
 394          return GL_FALSE;
 395    }
 396
 397    assert( logic_op - GL_CLEAR >= 0 );
 398    assert( logic_op - GL_CLEAR < 0x10 );
 399    assert(dst_pitch > 0);
 400
 401    if (w < 0 || h < 0)
 402       return GL_TRUE;
 403
 404    dst_pitch *= cpp;
 405
 406    DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
 407        __FUNCTION__,
 408        dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords);
 409
 410    intel_batchbuffer_require_space( intel->batch,
 411                                     (8 * 4) +
 412                                     (3 * 4) +
 413                                     dwords * 4, true);
 414
 415    opcode = XY_SETUP_BLT_CMD;
 416    if (cpp == 4)
 417       opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 418 #ifndef I915
 419    if (dst_tiling != I915_TILING_NONE) {
 420       opcode |= XY_DST_TILED;
 421       dst_pitch /= 4;
 422    }
 423 #endif
 424
 425    br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29);
 426    br13 |= br13_for_cpp(cpp);
 427
 428    blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */
 429    if (dst_tiling != I915_TILING_NONE)
 430       blit_cmd |= XY_DST_TILED;
 431
 432    BEGIN_BATCH_BLT(8 + 3);
 433    OUT_BATCH(opcode);
 434    OUT_BATCH(br13);
 435    OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
 436    OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
 437    OUT_RELOC_FENCED(dst_buffer,
 438                     I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 439                     dst_offset);
 440    OUT_BATCH(0); /* bg */
 441    OUT_BATCH(fg_color); /* fg */
 442    OUT_BATCH(0); /* pattern base addr */
 443
 444    OUT_BATCH(blit_cmd | ((3 - 2) + dwords));
 445    OUT_BATCH((y << 16) | x);
 446    OUT_BATCH(((y + h) << 16) | (x + w));
 447    ADVANCE_BATCH();
 448
 449    intel_batchbuffer_data(intel->batch,
 450                           src_bits,
 451                           dwords * 4, true);
 452
 453    intel_batchbuffer_emit_mi_flush(intel->batch);
 454
 455    return GL_TRUE;
 456 }
 457
 458 /* We don't have a memmove-type blit like some other hardware, so we'll do a
 459  * rectangular blit covering a large space, then emit 1-scanline blit at the
 460  * end to cover the last if we need.
 461  */
 462 void
 463 intel_emit_linear_blit(struct intel_context *intel,
 464                        drm_intel_bo *dst_bo,
 465                        unsigned int dst_offset,
 466                        drm_intel_bo *src_bo,
 467                        unsigned int src_offset,
 468                        unsigned int size)
 469 {
 470    GLuint pitch, height;
 471    GLboolean ok;
 472
 473    /* The pitch given to the GPU must be DWORD aligned, and
 474     * we want width to match pitch. Max width is (1 << 15 - 1),
 475     * rounding that down to the nearest DWORD is 1 << 15 - 4
 476     */
 477    pitch = MIN2(size, (1 << 15) - 4);
 478    height = size / pitch;
 479    ok = intelEmitCopyBlit(intel, 1,
 480                           pitch, src_bo, src_offset, I915_TILING_NONE,
 481                           pitch, dst_bo, dst_offset, I915_TILING_NONE,
 482                           0, 0, /* src x/y */
 483                           0, 0, /* dst x/y */
 484                           pitch, height, /* w, h */
 485                           GL_COPY);
 486    assert(ok);
 487
 488    src_offset += pitch * height;
 489    dst_offset += pitch * height;
 490    size -= pitch * height;
 491    assert (size < (1 << 15));
 492    assert ((size & 3) == 0); /* Pitch must be DWORD aligned */
 493    if (size != 0) {
 494       ok = intelEmitCopyBlit(intel, 1,
 495                              size, src_bo, src_offset, I915_TILING_NONE,
 496                              size, dst_bo, dst_offset, I915_TILING_NONE,
 497                              0, 0, /* src x/y */
 498                              0, 0, /* dst x/y */
 499                              size, 1, /* w, h */
 500                              GL_COPY);
 501       assert(ok);
 502    }
 503 }
 504
 505 /**
 506  * Used to initialize the alpha value of an ARGB8888 teximage after
 507  * loading it from an XRGB8888 source.
 508  *
 509  * This is very common with glCopyTexImage2D().
 510  */
 511 void
 512 intel_set_teximage_alpha_to_one(struct gl_context *ctx,
 513                                 struct intel_texture_image *intel_image)
 514 {
 515    struct intel_context *intel = intel_context(ctx);
 516    unsigned int image_x, image_y;
 517    uint32_t x1, y1, x2, y2;
 518    uint32_t BR13, CMD;
 519    int pitch, cpp;
 520    drm_intel_bo *aper_array[2];
 521    struct intel_region *region = intel_image->mt->region;
 522    BATCH_LOCALS;
 523
 524    assert(intel_image->base.TexFormat == MESA_FORMAT_ARGB8888);
 525
 526    /* get dest x/y in destination texture */
 527    intel_miptree_get_image_offset(intel_image->mt,
 528                                   intel_image->level,
 529                                   intel_image->face,
 530                                   0,
 531                                   &image_x, &image_y);
 532
 533    x1 = image_x;
 534    y1 = image_y;
 535    x2 = image_x + intel_image->base.Width;
 536    y2 = image_y + intel_image->base.Height;
 537
 538    pitch = region->pitch;
 539    cpp = region->cpp;
 540
 541    DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
 542        __FUNCTION__,
 543        intel_image->mt->region->buffer, (pitch * region->cpp),
 544        x1, y1, x2 - x1, y2 - y1);
 545
 546    BR13 = br13_for_cpp(region->cpp) | 0xf0 << 16;
 547    CMD = XY_COLOR_BLT_CMD;
 548    CMD |= XY_BLT_WRITE_ALPHA;
 549
 550    assert(region->tiling != I915_TILING_Y);
 551
 552 #ifndef I915
 553    if (region->tiling != I915_TILING_NONE) {
 554       CMD |= XY_DST_TILED;
 555       pitch /= 4;
 556    }
 557 #endif
 558    BR13 |= (pitch * region->cpp);
 559
 560    /* do space check before going any further */
 561    aper_array[0] = intel->batch->buf;
 562    aper_array[1] = region->buffer;
 563
 564    if (drm_intel_bufmgr_check_aperture_space(aper_array,
 565                                              ARRAY_SIZE(aper_array)) != 0) {
 566       intel_batchbuffer_flush(intel->batch);
 567    }
 568
 569    BEGIN_BATCH_BLT(6);
 570    OUT_BATCH(CMD);
 571    OUT_BATCH(BR13);
 572    OUT_BATCH((y1 << 16) | x1);
 573    OUT_BATCH((y2 << 16) | x2);
 574    OUT_RELOC_FENCED(region->buffer,
 575                     I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 576                     0);
 577    OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
 578    ADVANCE_BATCH();
 579
 580    intel_batchbuffer_emit_mi_flush(intel->batch);
 581 }