src/mesa/drivers/dri/intel/intel_blit.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29 #include <stdio.h>
  30 #include <errno.h>
  31
  32 #include "main/mtypes.h"
  33 #include "main/context.h"
  34 #include "main/enums.h"
  35 #include "main/texformat.h"
  36 #include "main/colormac.h"
  37
  38 #include "intel_blit.h"
  39 #include "intel_buffers.h"
  40 #include "intel_context.h"
  41 #include "intel_fbo.h"
  42 #include "intel_reg.h"
  43 #include "intel_regions.h"
  44 #include "intel_batchbuffer.h"
  45 #include "intel_chipset.h"
  46
  47 #define FILE_DEBUG_FLAG DEBUG_BLIT
  48
  49 /**
  50  * Copy the back color buffer to the front color buffer.
  51  * Used for SwapBuffers().
  52  */
  53 void
  54 intelCopyBuffer(const __DRIdrawablePrivate * dPriv,
  55                 const drm_clip_rect_t * rect)
  56 {
  57
  58    struct intel_context *intel;
  59    const intelScreenPrivate *intelScreen;
  60
  61    DBG("%s\n", __FUNCTION__);
  62
  63    assert(dPriv);
  64
  65    intel = intelScreenContext(dPriv->driScreenPriv->private);
  66    if (!intel)
  67       return;
  68
  69    intelScreen = intel->intelScreen;
  70
  71    /* The LOCK_HARDWARE is required for the cliprects.  Buffer offsets
  72     * should work regardless.
  73     */
  74    LOCK_HARDWARE(intel);
  75
  76    if (dPriv && dPriv->numClipRects) {
  77       struct intel_framebuffer *intel_fb = dPriv->driverPrivate;
  78       struct intel_region *src, *dst;
  79       int nbox = dPriv->numClipRects;
  80       drm_clip_rect_t *pbox = dPriv->pClipRects;
  81       int cpp;
  82       int src_pitch, dst_pitch;
  83       unsigned short src_x, src_y;
  84       int BR13, CMD;
  85       int i;
  86       dri_bo *aper_array[3];
  87
  88       src = intel_get_rb_region(&intel_fb->Base, BUFFER_BACK_LEFT);
  89       dst = intel_get_rb_region(&intel_fb->Base, BUFFER_FRONT_LEFT);
  90
  91       src_pitch = src->pitch * src->cpp;
  92       dst_pitch = dst->pitch * dst->cpp;
  93
  94       cpp = src->cpp;
  95
  96       ASSERT(intel_fb);
  97       ASSERT(intel_fb->Base.Name == 0);    /* Not a user-created FBO */
  98       ASSERT(src);
  99       ASSERT(dst);
 100       ASSERT(src->cpp == dst->cpp);
 101
 102       if (cpp == 2) {
 103          BR13 = (0xCC << 16) | BR13_565;
 104          CMD = XY_SRC_COPY_BLT_CMD;
 105       }
 106       else {
 107          BR13 = (0xCC << 16) | BR13_8888;
 108          CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 109       }
 110
 111 #ifndef I915
 112       if (src->tiling != I915_TILING_NONE) {
 113          CMD |= XY_SRC_TILED;
 114          src_pitch /= 4;
 115       }
 116       if (dst->tiling != I915_TILING_NONE) {
 117          CMD |= XY_DST_TILED;
 118          dst_pitch /= 4;
 119       }
 120 #endif
 121       /* do space/cliprects check before going any further */
 122       intel_batchbuffer_require_space(intel->batch, 8 * 4,
 123                                       REFERENCES_CLIPRECTS);
 124    again:
 125       aper_array[0] = intel->batch->buf;
 126       aper_array[1] = dst->buffer;
 127       aper_array[2] = src->buffer;
 128
 129       if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
 130         intel_batchbuffer_flush(intel->batch);
 131         goto again;
 132       }
 133
 134       for (i = 0; i < nbox; i++, pbox++) {
 135          drm_clip_rect_t box = *pbox;
 136
 137          if (rect) {
 138             if (!intel_intersect_cliprects(&box, &box, rect))
 139                continue;
 140          }
 141
 142          if (box.x1 >= box.x2 ||
 143              box.y1 >= box.y2)
 144             continue;
 145
 146          assert(box.x1 < box.x2);
 147          assert(box.y1 < box.y2);
 148          src_x = box.x1 - dPriv->x + dPriv->backX;
 149          src_y = box.y1 - dPriv->y + dPriv->backY;
 150
 151          BEGIN_BATCH(8, REFERENCES_CLIPRECTS);
 152          OUT_BATCH(CMD);
 153          OUT_BATCH(BR13 | dst_pitch);
 154          OUT_BATCH((box.y1 << 16) | box.x1);
 155          OUT_BATCH((box.y2 << 16) | box.x2);
 156
 157          OUT_RELOC(dst->buffer,
 158                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 159                    0);
 160          OUT_BATCH((src_y << 16) | src_x);
 161          OUT_BATCH(src_pitch);
 162          OUT_RELOC(src->buffer,
 163                    I915_GEM_DOMAIN_RENDER, 0,
 164                    0);
 165          ADVANCE_BATCH();
 166       }
 167
 168       /* Flush the rendering and the batch so that the results all land on the
 169        * screen in a timely fashion.
 170        */
 171       intel_batchbuffer_emit_mi_flush(intel->batch);
 172       intel_batchbuffer_flush(intel->batch);
 173    }
 174
 175    UNLOCK_HARDWARE(intel);
 176 }
 177
 178
 179
 180
 181 void
 182 intelEmitFillBlit(struct intel_context *intel,
 183                   GLuint cpp,
 184                   GLshort dst_pitch,
 185                   dri_bo *dst_buffer,
 186                   GLuint dst_offset,
 187                   uint32_t dst_tiling,
 188                   GLshort x, GLshort y,
 189                   GLshort w, GLshort h,
 190                   GLuint color)
 191 {
 192    GLuint BR13, CMD;
 193    BATCH_LOCALS;
 194
 195    dst_pitch *= cpp;
 196
 197    switch (cpp) {
 198    case 1:
 199       BR13 = (0xF0 << 16);
 200       CMD = XY_COLOR_BLT_CMD;
 201       break;
 202    case 2:
 203       BR13 = (0xF0 << 16) | BR13_565;
 204       CMD = XY_COLOR_BLT_CMD;
 205       break;
 206    case 4:
 207       BR13 = (0xF0 << 16) | BR13_8888;
 208       CMD = XY_COLOR_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 209       break;
 210    default:
 211       return;
 212    }
 213 #ifndef I915
 214    if (dst_tiling != I915_TILING_NONE) {
 215       CMD |= XY_DST_TILED;
 216       dst_pitch /= 4;
 217    }
 218 #endif
 219
 220    DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
 221        __FUNCTION__, dst_buffer, dst_pitch, dst_offset, x, y, w, h);
 222
 223    assert(w > 0);
 224    assert(h > 0);
 225
 226    BEGIN_BATCH(6, NO_LOOP_CLIPRECTS);
 227    OUT_BATCH(CMD);
 228    OUT_BATCH(BR13 | dst_pitch);
 229    OUT_BATCH((y << 16) | x);
 230    OUT_BATCH(((y + h) << 16) | (x + w));
 231    OUT_RELOC(dst_buffer,
 232              I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 233              dst_offset);
 234    OUT_BATCH(color);
 235    ADVANCE_BATCH();
 236 }
 237
 238 static GLuint translate_raster_op(GLenum logicop)
 239 {
 240    switch(logicop) {
 241    case GL_CLEAR: return 0x00;
 242    case GL_AND: return 0x88;
 243    case GL_AND_REVERSE: return 0x44;
 244    case GL_COPY: return 0xCC;
 245    case GL_AND_INVERTED: return 0x22;
 246    case GL_NOOP: return 0xAA;
 247    case GL_XOR: return 0x66;
 248    case GL_OR: return 0xEE;
 249    case GL_NOR: return 0x11;
 250    case GL_EQUIV: return 0x99;
 251    case GL_INVERT: return 0x55;
 252    case GL_OR_REVERSE: return 0xDD;
 253    case GL_COPY_INVERTED: return 0x33;
 254    case GL_OR_INVERTED: return 0xBB;
 255    case GL_NAND: return 0x77;
 256    case GL_SET: return 0xFF;
 257    default: return 0;
 258    }
 259 }
 260
 261
 262 /* Copy BitBlt
 263  */
 264 void
 265 intelEmitCopyBlit(struct intel_context *intel,
 266                   GLuint cpp,
 267                   GLshort src_pitch,
 268                   dri_bo *src_buffer,
 269                   GLuint src_offset,
 270                   uint32_t src_tiling,
 271                   GLshort dst_pitch,
 272                   dri_bo *dst_buffer,
 273                   GLuint dst_offset,
 274                   uint32_t dst_tiling,
 275                   GLshort src_x, GLshort src_y,
 276                   GLshort dst_x, GLshort dst_y,
 277                   GLshort w, GLshort h,
 278                   GLenum logic_op)
 279 {
 280    GLuint CMD, BR13, pass = 0;
 281    int dst_y2 = dst_y + h;
 282    int dst_x2 = dst_x + w;
 283    dri_bo *aper_array[3];
 284    BATCH_LOCALS;
 285
 286    /* do space/cliprects check before going any further */
 287    do {
 288        aper_array[0] = intel->batch->buf;
 289        aper_array[1] = dst_buffer;
 290        aper_array[2] = src_buffer;
 291
 292        if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
 293            intel_batchbuffer_flush(intel->batch);
 294            pass++;
 295        } else
 296            break;
 297    } while (pass < 2);
 298
 299    if (pass >= 2) {
 300        GLboolean locked = GL_FALSE;
 301        if (!intel->locked) {
 302            LOCK_HARDWARE(intel);
 303            locked = GL_TRUE;
 304        }
 305
 306        dri_bo_map(dst_buffer, GL_TRUE);
 307        dri_bo_map(src_buffer, GL_FALSE);
 308        _mesa_copy_rect((GLubyte *)dst_buffer->virtual + dst_offset,
 309                        cpp,
 310                        dst_pitch,
 311                        dst_x, dst_y,
 312                        w, h,
 313                        (GLubyte *)src_buffer->virtual + src_offset,
 314                        src_pitch,
 315                        src_x, src_y);
 316
 317        dri_bo_unmap(src_buffer);
 318        dri_bo_unmap(dst_buffer);
 319
 320        if (locked)
 321            UNLOCK_HARDWARE(intel);
 322
 323        return;
 324    }
 325
 326    intel_batchbuffer_require_space(intel->batch, 8 * 4, NO_LOOP_CLIPRECTS);
 327    DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
 328        __FUNCTION__,
 329        src_buffer, src_pitch, src_offset, src_x, src_y,
 330        dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
 331
 332    src_pitch *= cpp;
 333    dst_pitch *= cpp;
 334
 335    BR13 = translate_raster_op(logic_op) << 16;
 336
 337    switch (cpp) {
 338    case 1:
 339       CMD = XY_SRC_COPY_BLT_CMD;
 340       break;
 341    case 2:
 342       BR13 |= BR13_565;
 343       CMD = XY_SRC_COPY_BLT_CMD;
 344       break;
 345    case 4:
 346       BR13 |= BR13_8888;
 347       CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 348       break;
 349    default:
 350       return;
 351    }
 352
 353 #ifndef I915
 354    if (dst_tiling != I915_TILING_NONE) {
 355       CMD |= XY_DST_TILED;
 356       dst_pitch /= 4;
 357    }
 358    if (src_tiling != I915_TILING_NONE) {
 359       CMD |= XY_SRC_TILED;
 360       src_pitch /= 4;
 361    }
 362 #endif
 363
 364    if (dst_y2 <= dst_y || dst_x2 <= dst_x) {
 365       return;
 366    }
 367
 368    assert(dst_x < dst_x2);
 369    assert(dst_y < dst_y2);
 370
 371    BEGIN_BATCH(8, NO_LOOP_CLIPRECTS);
 372    OUT_BATCH(CMD);
 373    OUT_BATCH(BR13 | (uint16_t)dst_pitch);
 374    OUT_BATCH((dst_y << 16) | dst_x);
 375    OUT_BATCH((dst_y2 << 16) | dst_x2);
 376    OUT_RELOC(dst_buffer,
 377              I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 378              dst_offset);
 379    OUT_BATCH((src_y << 16) | src_x);
 380    OUT_BATCH((uint16_t)src_pitch);
 381    OUT_RELOC(src_buffer,
 382              I915_GEM_DOMAIN_RENDER, 0,
 383              src_offset);
 384    ADVANCE_BATCH();
 385
 386    intel_batchbuffer_emit_mi_flush(intel->batch);
 387 }
 388
 389
 390 /**
 391  * Use blitting to clear the renderbuffers named by 'flags'.
 392  * Note: we can't use the ctx->DrawBuffer->_ColorDrawBufferIndexes field
 393  * since that might include software renderbuffers or renderbuffers
 394  * which we're clearing with triangles.
 395  * \param mask  bitmask of BUFFER_BIT_* values indicating buffers to clear
 396  */
 397 void
 398 intelClearWithBlit(GLcontext *ctx, GLbitfield mask)
 399 {
 400    struct intel_context *intel = intel_context(ctx);
 401    struct gl_framebuffer *fb = ctx->DrawBuffer;
 402    GLuint clear_depth;
 403    GLbitfield skipBuffers = 0;
 404    unsigned int num_cliprects;
 405    struct drm_clip_rect *cliprects;
 406    int x_off, y_off;
 407    BATCH_LOCALS;
 408
 409    /*
 410     * Compute values for clearing the buffers.
 411     */
 412    clear_depth = 0;
 413    if (mask & BUFFER_BIT_DEPTH) {
 414       clear_depth = (GLuint) (fb->_DepthMax * ctx->Depth.Clear);
 415    }
 416    if (mask & BUFFER_BIT_STENCIL) {
 417       clear_depth |= (ctx->Stencil.Clear & 0xff) << 24;
 418    }
 419
 420    /* If clearing both depth and stencil, skip BUFFER_BIT_STENCIL in
 421     * the loop below.
 422     */
 423    if ((mask & BUFFER_BIT_DEPTH) && (mask & BUFFER_BIT_STENCIL)) {
 424       skipBuffers = BUFFER_BIT_STENCIL;
 425    }
 426
 427    /* XXX Move this flush/lock into the following conditional? */
 428    intelFlush(&intel->ctx);
 429    LOCK_HARDWARE(intel);
 430
 431    intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off);
 432    if (num_cliprects) {
 433       GLint cx, cy, cw, ch;
 434       drm_clip_rect_t clear;
 435       int i;
 436
 437       /* Get clear bounds after locking */
 438       cx = fb->_Xmin;
 439       cy = fb->_Ymin;
 440       cw = fb->_Xmax - cx;
 441       ch = fb->_Ymax - cy;
 442
 443       if (fb->Name == 0) {
 444          /* clearing a window */
 445
 446          /* flip top to bottom */
 447          clear.x1 = cx + x_off;
 448          clear.y1 = intel->driDrawable->y + intel->driDrawable->h - cy - ch;
 449          clear.x2 = clear.x1 + cw;
 450          clear.y2 = clear.y1 + ch;
 451       }
 452       else {
 453          /* clearing FBO */
 454          assert(num_cliprects == 1);
 455          assert(cliprects == &intel->fboRect);
 456          clear.x1 = cx;
 457          clear.y1 = cy;
 458          clear.x2 = clear.x1 + cw;
 459          clear.y2 = clear.y1 + ch;
 460          /* no change to mask */
 461       }
 462
 463       for (i = 0; i < num_cliprects; i++) {
 464          const drm_clip_rect_t *box = &cliprects[i];
 465          drm_clip_rect_t b;
 466          GLuint buf;
 467          GLuint clearMask = mask;      /* use copy, since we modify it below */
 468          GLboolean all = (cw == fb->Width && ch == fb->Height);
 469
 470          if (!all) {
 471             intel_intersect_cliprects(&b, &clear, box);
 472          }
 473          else {
 474             b = *box;
 475          }
 476
 477          if (b.x1 >= b.x2 || b.y1 >= b.y2)
 478             continue;
 479
 480          if (0)
 481             _mesa_printf("clear %d,%d..%d,%d, mask %x\n",
 482                          b.x1, b.y1, b.x2, b.y2, mask);
 483
 484          /* Loop over all renderbuffers */
 485          for (buf = 0; buf < BUFFER_COUNT && clearMask; buf++) {
 486             const GLbitfield bufBit = 1 << buf;
 487             if ((clearMask & bufBit) && !(bufBit & skipBuffers)) {
 488                /* OK, clear this renderbuffer */
 489                struct intel_renderbuffer *irb = intel_get_renderbuffer(fb, buf);
 490                dri_bo *write_buffer =
 491                   intel_region_buffer(intel, irb->region,
 492                                       all ? INTEL_WRITE_FULL :
 493                                       INTEL_WRITE_PART);
 494
 495                GLuint clearVal;
 496                GLint pitch, cpp;
 497                GLuint BR13, CMD;
 498
 499                pitch = irb->region->pitch;
 500                cpp = irb->region->cpp;
 501
 502                DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
 503                    __FUNCTION__,
 504                    irb->region->buffer, (pitch * cpp),
 505                    irb->region->draw_offset,
 506                    b.x1, b.y1, b.x2 - b.x1, b.y2 - b.y1);
 507
 508                BR13 = 0xf0 << 16;
 509                CMD = XY_COLOR_BLT_CMD;
 510
 511                /* Setup the blit command */
 512                if (cpp == 4) {
 513                   BR13 |= BR13_8888;
 514                   if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) {
 515                      if (clearMask & BUFFER_BIT_DEPTH)
 516                         CMD |= XY_BLT_WRITE_RGB;
 517                      if (clearMask & BUFFER_BIT_STENCIL)
 518                         CMD |= XY_BLT_WRITE_ALPHA;
 519                   }
 520                   else {
 521                      /* clearing RGBA */
 522                      CMD |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 523                   }
 524                }
 525                else {
 526                   ASSERT(cpp == 2);
 527                   BR13 |= BR13_565;
 528                }
 529
 530 #ifndef I915
 531                if (irb->region->tiling != I915_TILING_NONE) {
 532                   CMD |= XY_DST_TILED;
 533                   pitch /= 4;
 534                }
 535 #endif
 536                BR13 |= (pitch * cpp);
 537
 538                if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) {
 539                   clearVal = clear_depth;
 540                }
 541                else {
 542                   uint8_t clear[4];
 543                   GLclampf *color = ctx->Color.ClearColor;
 544
 545                   CLAMPED_FLOAT_TO_UBYTE(clear[0], color[0]);
 546                   CLAMPED_FLOAT_TO_UBYTE(clear[1], color[1]);
 547                   CLAMPED_FLOAT_TO_UBYTE(clear[2], color[2]);
 548                   CLAMPED_FLOAT_TO_UBYTE(clear[3], color[3]);
 549
 550                   switch (irb->texformat->MesaFormat) {
 551                   case MESA_FORMAT_ARGB8888:
 552                      clearVal = intel->ClearColor8888;
 553                      break;
 554                   case MESA_FORMAT_RGB565:
 555                      clearVal = intel->ClearColor565;
 556                      break;
 557                   case MESA_FORMAT_ARGB4444:
 558                      clearVal = PACK_COLOR_4444(clear[3], clear[0],
 559                                                 clear[1], clear[2]);
 560                      break;
 561                   case MESA_FORMAT_ARGB1555:
 562                      clearVal = PACK_COLOR_1555(clear[3], clear[0],
 563                                                 clear[1], clear[2]);
 564                      break;
 565                   default:
 566                      _mesa_problem(ctx, "Unexpected renderbuffer format: %d\n",
 567                                    irb->texformat->MesaFormat);
 568                      clearVal = 0;
 569                   }
 570                }
 571
 572                /*
 573                   _mesa_debug(ctx, "hardware blit clear buf %d rb id %d\n",
 574                   buf, irb->Base.Name);
 575                 */
 576
 577                assert(b.x1 < b.x2);
 578                assert(b.y1 < b.y2);
 579
 580                BEGIN_BATCH(6, REFERENCES_CLIPRECTS);
 581                OUT_BATCH(CMD);
 582                OUT_BATCH(BR13);
 583                OUT_BATCH((b.y1 << 16) | b.x1);
 584                OUT_BATCH((b.y2 << 16) | b.x2);
 585                OUT_RELOC(write_buffer,
 586                          I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 587                          irb->region->draw_offset);
 588                OUT_BATCH(clearVal);
 589                ADVANCE_BATCH();
 590                clearMask &= ~bufBit;    /* turn off bit, for faster loop exit */
 591             }
 592          }
 593       }
 594    }
 595
 596    UNLOCK_HARDWARE(intel);
 597 }
 598
 599 void
 600 intelEmitImmediateColorExpandBlit(struct intel_context *intel,
 601                                   GLuint cpp,
 602                                   GLubyte *src_bits, GLuint src_size,
 603                                   GLuint fg_color,
 604                                   GLshort dst_pitch,
 605                                   dri_bo *dst_buffer,
 606                                   GLuint dst_offset,
 607                                   uint32_t dst_tiling,
 608                                   GLshort x, GLshort y,
 609                                   GLshort w, GLshort h,
 610                                   GLenum logic_op)
 611 {
 612    int dwords = ALIGN(src_size, 8) / 4;
 613    uint32_t opcode, br13, blit_cmd;
 614
 615    assert( logic_op - GL_CLEAR >= 0 );
 616    assert( logic_op - GL_CLEAR < 0x10 );
 617
 618    if (w < 0 || h < 0)
 619       return;
 620
 621    dst_pitch *= cpp;
 622
 623    DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
 624        __FUNCTION__,
 625        dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords);
 626
 627    intel_batchbuffer_require_space( intel->batch,
 628                                     (8 * 4) +
 629                                     (3 * 4) +
 630                                     dwords * 4,
 631                                     REFERENCES_CLIPRECTS );
 632
 633    opcode = XY_SETUP_BLT_CMD;
 634    if (cpp == 4)
 635       opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 636 #ifndef I915
 637    if (dst_tiling != I915_TILING_NONE) {
 638       opcode |= XY_DST_TILED;
 639       dst_pitch /= 4;
 640    }
 641 #endif
 642
 643    br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29);
 644    if (cpp == 2)
 645       br13 |= BR13_565;
 646    else
 647       br13 |= BR13_8888;
 648
 649    blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */
 650    if (dst_tiling != I915_TILING_NONE)
 651       blit_cmd |= XY_DST_TILED;
 652
 653    BEGIN_BATCH(8 + 3, REFERENCES_CLIPRECTS);
 654    OUT_BATCH(opcode);
 655    OUT_BATCH(br13);
 656    OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
 657    OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
 658    OUT_RELOC(dst_buffer,
 659              I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 660              dst_offset);
 661    OUT_BATCH(0); /* bg */
 662    OUT_BATCH(fg_color); /* fg */
 663    OUT_BATCH(0); /* pattern base addr */
 664
 665    OUT_BATCH(blit_cmd | ((3 - 2) + dwords));
 666    OUT_BATCH((y << 16) | x);
 667    OUT_BATCH(((y + h) << 16) | (x + w));
 668    ADVANCE_BATCH();
 669
 670    intel_batchbuffer_data( intel->batch,
 671                            src_bits,
 672                            dwords * 4,
 673                            REFERENCES_CLIPRECTS );
 674
 675    intel_batchbuffer_emit_mi_flush(intel->batch);
 676 }