src/mesa/drivers/dri/intel/intel_blit.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29 #include "main/mtypes.h"
  30 #include "main/context.h"
  31 #include "main/enums.h"
  32 #include "main/colormac.h"
  33
  34 #include "intel_blit.h"
  35 #include "intel_buffers.h"
  36 #include "intel_context.h"
  37 #include "intel_fbo.h"
  38 #include "intel_reg.h"
  39 #include "intel_regions.h"
  40 #include "intel_batchbuffer.h"
  41 #include "intel_mipmap_tree.h"
  42
  43 #define FILE_DEBUG_FLAG DEBUG_BLIT
  44
  45 static GLuint translate_raster_op(GLenum logicop)
  46 {
  47    switch(logicop) {
  48    case GL_CLEAR: return 0x00;
  49    case GL_AND: return 0x88;
  50    case GL_AND_REVERSE: return 0x44;
  51    case GL_COPY: return 0xCC;
  52    case GL_AND_INVERTED: return 0x22;
  53    case GL_NOOP: return 0xAA;
  54    case GL_XOR: return 0x66;
  55    case GL_OR: return 0xEE;
  56    case GL_NOR: return 0x11;
  57    case GL_EQUIV: return 0x99;
  58    case GL_INVERT: return 0x55;
  59    case GL_OR_REVERSE: return 0xDD;
  60    case GL_COPY_INVERTED: return 0x33;
  61    case GL_OR_INVERTED: return 0xBB;
  62    case GL_NAND: return 0x77;
  63    case GL_SET: return 0xFF;
  64    default: return 0;
  65    }
  66 }
  67
  68 static uint32_t
  69 br13_for_cpp(int cpp)
  70 {
  71    switch (cpp) {
  72    case 4:
  73       return BR13_8888;
  74       break;
  75    case 2:
  76       return BR13_565;
  77       break;
  78    case 1:
  79       return BR13_8;
  80       break;
  81    default:
  82       assert(0);
  83       return 0;
  84    }
  85 }
  86
  87 /* Copy BitBlt
  88  */
  89 GLboolean
  90 intelEmitCopyBlit(struct intel_context *intel,
  91                   GLuint cpp,
  92                   GLshort src_pitch,
  93                   drm_intel_bo *src_buffer,
  94                   GLuint src_offset,
  95                   uint32_t src_tiling,
  96                   GLshort dst_pitch,
  97                   drm_intel_bo *dst_buffer,
  98                   GLuint dst_offset,
  99                   uint32_t dst_tiling,
 100                   GLshort src_x, GLshort src_y,
 101                   GLshort dst_x, GLshort dst_y,
 102                   GLshort w, GLshort h,
 103                   GLenum logic_op)
 104 {
 105    GLuint CMD, BR13, pass = 0;
 106    int dst_y2 = dst_y + h;
 107    int dst_x2 = dst_x + w;
 108    drm_intel_bo *aper_array[3];
 109    BATCH_LOCALS;
 110
 111    if (dst_tiling != I915_TILING_NONE) {
 112       if (dst_offset & 4095)
 113          return GL_FALSE;
 114       if (dst_tiling == I915_TILING_Y)
 115          return GL_FALSE;
 116    }
 117    if (src_tiling != I915_TILING_NONE) {
 118       if (src_offset & 4095)
 119          return GL_FALSE;
 120       if (src_tiling == I915_TILING_Y)
 121          return GL_FALSE;
 122    }
 123
 124    /* do space check before going any further */
 125    do {
 126        aper_array[0] = intel->batch.bo;
 127        aper_array[1] = dst_buffer;
 128        aper_array[2] = src_buffer;
 129
 130        if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
 131            intel_batchbuffer_flush(intel);
 132            pass++;
 133        } else
 134            break;
 135    } while (pass < 2);
 136
 137    if (pass >= 2)
 138       return GL_FALSE;
 139
 140    intel_batchbuffer_require_space(intel, 8 * 4, true);
 141    DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
 142        __FUNCTION__,
 143        src_buffer, src_pitch, src_offset, src_x, src_y,
 144        dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
 145
 146    src_pitch *= cpp;
 147    dst_pitch *= cpp;
 148
 149    /* For big formats (such as floating point), do the copy using 32bpp and
 150     * multiply the coordinates.
 151     */
 152    if (cpp > 4) {
 153       assert(cpp % 4 == 0);
 154       dst_x *= cpp / 4;
 155       dst_x2 *= cpp / 4;
 156       src_x *= cpp / 4;
 157       cpp = 4;
 158    }
 159
 160    BR13 = br13_for_cpp(cpp) | translate_raster_op(logic_op) << 16;
 161
 162    switch (cpp) {
 163    case 1:
 164    case 2:
 165       CMD = XY_SRC_COPY_BLT_CMD;
 166       break;
 167    case 4:
 168       CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 169       break;
 170    default:
 171       return GL_FALSE;
 172    }
 173
 174 #ifndef I915
 175    if (dst_tiling != I915_TILING_NONE) {
 176       CMD |= XY_DST_TILED;
 177       dst_pitch /= 4;
 178    }
 179    if (src_tiling != I915_TILING_NONE) {
 180       CMD |= XY_SRC_TILED;
 181       src_pitch /= 4;
 182    }
 183 #endif
 184
 185    if (dst_y2 <= dst_y || dst_x2 <= dst_x) {
 186       return GL_TRUE;
 187    }
 188
 189    assert(dst_x < dst_x2);
 190    assert(dst_y < dst_y2);
 191
 192    BEGIN_BATCH_BLT(8);
 193    OUT_BATCH(CMD);
 194    OUT_BATCH(BR13 | (uint16_t)dst_pitch);
 195    OUT_BATCH((dst_y << 16) | dst_x);
 196    OUT_BATCH((dst_y2 << 16) | dst_x2);
 197    OUT_RELOC_FENCED(dst_buffer,
 198                     I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 199                     dst_offset);
 200    OUT_BATCH((src_y << 16) | src_x);
 201    OUT_BATCH((uint16_t)src_pitch);
 202    OUT_RELOC_FENCED(src_buffer,
 203                     I915_GEM_DOMAIN_RENDER, 0,
 204                     src_offset);
 205    ADVANCE_BATCH();
 206
 207    intel_batchbuffer_emit_mi_flush(intel);
 208
 209    return GL_TRUE;
 210 }
 211
 212
 213 /**
 214  * Use blitting to clear the renderbuffers named by 'flags'.
 215  * Note: we can't use the ctx->DrawBuffer->_ColorDrawBufferIndexes field
 216  * since that might include software renderbuffers or renderbuffers
 217  * which we're clearing with triangles.
 218  * \param mask  bitmask of BUFFER_BIT_* values indicating buffers to clear
 219  */
 220 GLbitfield
 221 intelClearWithBlit(struct gl_context *ctx, GLbitfield mask)
 222 {
 223    struct intel_context *intel = intel_context(ctx);
 224    struct gl_framebuffer *fb = ctx->DrawBuffer;
 225    GLuint clear_depth_value, clear_depth_mask;
 226    GLboolean all;
 227    GLint cx, cy, cw, ch;
 228    GLbitfield fail_mask = 0;
 229    BATCH_LOCALS;
 230
 231    /*
 232     * Compute values for clearing the buffers.
 233     */
 234    clear_depth_value = 0;
 235    clear_depth_mask = 0;
 236    if (mask & BUFFER_BIT_DEPTH) {
 237       clear_depth_value = (GLuint) (fb->_DepthMax * ctx->Depth.Clear);
 238       clear_depth_mask = XY_BLT_WRITE_RGB;
 239    }
 240    if (mask & BUFFER_BIT_STENCIL) {
 241       clear_depth_value |= (ctx->Stencil.Clear & 0xff) << 24;
 242       clear_depth_mask |= XY_BLT_WRITE_ALPHA;
 243    }
 244
 245    cx = fb->_Xmin;
 246    if (fb->Name == 0)
 247       cy = ctx->DrawBuffer->Height - fb->_Ymax;
 248    else
 249       cy = fb->_Ymin;
 250    cw = fb->_Xmax - fb->_Xmin;
 251    ch = fb->_Ymax - fb->_Ymin;
 252
 253    if (cw == 0 || ch == 0)
 254       return 0;
 255
 256    all = (cw == fb->Width && ch == fb->Height);
 257
 258    /* Loop over all renderbuffers */
 259    mask &= (1 << BUFFER_COUNT) - 1;
 260    while (mask) {
 261       GLuint buf = _mesa_ffs(mask) - 1;
 262       GLboolean is_depth_stencil = buf == BUFFER_DEPTH || buf == BUFFER_STENCIL;
 263       struct intel_renderbuffer *irb;
 264       drm_intel_bo *write_buffer;
 265       int x1, y1, x2, y2;
 266       uint32_t clear_val;
 267       uint32_t BR13, CMD;
 268       int pitch, cpp;
 269       drm_intel_bo *aper_array[2];
 270
 271       mask &= ~(1 << buf);
 272
 273       irb = intel_get_renderbuffer(fb, buf);
 274       if (irb == NULL || irb->region == NULL || irb->region->buffer == NULL) {
 275          fail_mask |= 1 << buf;
 276          continue;
 277       }
 278
 279       /* OK, clear this renderbuffer */
 280       write_buffer = intel_region_buffer(intel, irb->region,
 281                                          all ? INTEL_WRITE_FULL :
 282                                          INTEL_WRITE_PART);
 283       x1 = cx + irb->draw_x;
 284       y1 = cy + irb->draw_y;
 285       x2 = cx + cw + irb->draw_x;
 286       y2 = cy + ch + irb->draw_y;
 287
 288       pitch = irb->region->pitch;
 289       cpp = irb->region->cpp;
 290
 291       DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
 292           __FUNCTION__,
 293           irb->region->buffer, (pitch * cpp),
 294           x1, y1, x2 - x1, y2 - y1);
 295
 296       BR13 = 0xf0 << 16;
 297       CMD = XY_COLOR_BLT_CMD;
 298
 299       /* Setup the blit command */
 300       if (cpp == 4) {
 301          if (is_depth_stencil) {
 302             CMD |= clear_depth_mask;
 303          } else {
 304             /* clearing RGBA */
 305             CMD |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 306          }
 307       }
 308
 309       assert(irb->region->tiling != I915_TILING_Y);
 310
 311 #ifndef I915
 312       if (irb->region->tiling != I915_TILING_NONE) {
 313          CMD |= XY_DST_TILED;
 314          pitch /= 4;
 315       }
 316 #endif
 317       BR13 |= (pitch * cpp);
 318
 319       if (is_depth_stencil) {
 320          clear_val = clear_depth_value;
 321       } else {
 322          uint8_t clear[4];
 323          GLfloat *color = ctx->Color.ClearColor.f;
 324
 325          _mesa_unclamped_float_rgba_to_ubyte(clear, color);
 326
 327          switch (irb->Base.Format) {
 328          case MESA_FORMAT_ARGB8888:
 329          case MESA_FORMAT_XRGB8888:
 330             clear_val = PACK_COLOR_8888(clear[3], clear[0],
 331                                         clear[1], clear[2]);
 332             break;
 333          case MESA_FORMAT_RGB565:
 334             clear_val = PACK_COLOR_565(clear[0], clear[1], clear[2]);
 335             break;
 336          case MESA_FORMAT_ARGB4444:
 337             clear_val = PACK_COLOR_4444(clear[3], clear[0],
 338                                         clear[1], clear[2]);
 339             break;
 340          case MESA_FORMAT_ARGB1555:
 341             clear_val = PACK_COLOR_1555(clear[3], clear[0],
 342                                         clear[1], clear[2]);
 343             break;
 344          case MESA_FORMAT_A8:
 345             clear_val = PACK_COLOR_8888(clear[3], clear[3],
 346                                         clear[3], clear[3]);
 347             break;
 348          default:
 349             fail_mask |= 1 << buf;
 350             continue;
 351          }
 352       }
 353
 354       BR13 |= br13_for_cpp(cpp);
 355
 356       assert(x1 < x2);
 357       assert(y1 < y2);
 358
 359       /* do space check before going any further */
 360       aper_array[0] = intel->batch.bo;
 361       aper_array[1] = write_buffer;
 362
 363       if (drm_intel_bufmgr_check_aperture_space(aper_array,
 364                                                 ARRAY_SIZE(aper_array)) != 0) {
 365          intel_batchbuffer_flush(intel);
 366       }
 367
 368       BEGIN_BATCH_BLT(6);
 369       OUT_BATCH(CMD);
 370       OUT_BATCH(BR13);
 371       OUT_BATCH((y1 << 16) | x1);
 372       OUT_BATCH((y2 << 16) | x2);
 373       OUT_RELOC_FENCED(write_buffer,
 374                        I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 375                        0);
 376       OUT_BATCH(clear_val);
 377       ADVANCE_BATCH();
 378
 379       if (intel->always_flush_cache)
 380          intel_batchbuffer_emit_mi_flush(intel);
 381
 382       if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL)
 383          mask &= ~(BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL);
 384    }
 385
 386    return fail_mask;
 387 }
 388
 389 GLboolean
 390 intelEmitImmediateColorExpandBlit(struct intel_context *intel,
 391                                   GLuint cpp,
 392                                   GLubyte *src_bits, GLuint src_size,
 393                                   GLuint fg_color,
 394                                   GLshort dst_pitch,
 395                                   drm_intel_bo *dst_buffer,
 396                                   GLuint dst_offset,
 397                                   uint32_t dst_tiling,
 398                                   GLshort x, GLshort y,
 399                                   GLshort w, GLshort h,
 400                                   GLenum logic_op)
 401 {
 402    int dwords = ALIGN(src_size, 8) / 4;
 403    uint32_t opcode, br13, blit_cmd;
 404
 405    if (dst_tiling != I915_TILING_NONE) {
 406       if (dst_offset & 4095)
 407          return GL_FALSE;
 408       if (dst_tiling == I915_TILING_Y)
 409          return GL_FALSE;
 410    }
 411
 412    assert( logic_op - GL_CLEAR >= 0 );
 413    assert( logic_op - GL_CLEAR < 0x10 );
 414    assert(dst_pitch > 0);
 415
 416    if (w < 0 || h < 0)
 417       return GL_TRUE;
 418
 419    dst_pitch *= cpp;
 420
 421    DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
 422        __FUNCTION__,
 423        dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords);
 424
 425    intel_batchbuffer_require_space(intel,
 426                                    (8 * 4) +
 427                                    (3 * 4) +
 428                                    dwords * 4, true);
 429
 430    opcode = XY_SETUP_BLT_CMD;
 431    if (cpp == 4)
 432       opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 433 #ifndef I915
 434    if (dst_tiling != I915_TILING_NONE) {
 435       opcode |= XY_DST_TILED;
 436       dst_pitch /= 4;
 437    }
 438 #endif
 439
 440    br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29);
 441    br13 |= br13_for_cpp(cpp);
 442
 443    blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */
 444    if (dst_tiling != I915_TILING_NONE)
 445       blit_cmd |= XY_DST_TILED;
 446
 447    BEGIN_BATCH_BLT(8 + 3);
 448    OUT_BATCH(opcode);
 449    OUT_BATCH(br13);
 450    OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
 451    OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
 452    OUT_RELOC_FENCED(dst_buffer,
 453                     I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 454                     dst_offset);
 455    OUT_BATCH(0); /* bg */
 456    OUT_BATCH(fg_color); /* fg */
 457    OUT_BATCH(0); /* pattern base addr */
 458
 459    OUT_BATCH(blit_cmd | ((3 - 2) + dwords));
 460    OUT_BATCH((y << 16) | x);
 461    OUT_BATCH(((y + h) << 16) | (x + w));
 462    ADVANCE_BATCH();
 463
 464    intel_batchbuffer_data(intel, src_bits, dwords * 4, true);
 465
 466    intel_batchbuffer_emit_mi_flush(intel);
 467
 468    return GL_TRUE;
 469 }
 470
 471 /* We don't have a memmove-type blit like some other hardware, so we'll do a
 472  * rectangular blit covering a large space, then emit 1-scanline blit at the
 473  * end to cover the last if we need.
 474  */
 475 void
 476 intel_emit_linear_blit(struct intel_context *intel,
 477                        drm_intel_bo *dst_bo,
 478                        unsigned int dst_offset,
 479                        drm_intel_bo *src_bo,
 480                        unsigned int src_offset,
 481                        unsigned int size)
 482 {
 483    GLuint pitch, height;
 484    GLboolean ok;
 485
 486    /* The pitch given to the GPU must be DWORD aligned, and
 487     * we want width to match pitch. Max width is (1 << 15 - 1),
 488     * rounding that down to the nearest DWORD is 1 << 15 - 4
 489     */
 490    pitch = MIN2(size, (1 << 15) - 4);
 491    height = size / pitch;
 492    ok = intelEmitCopyBlit(intel, 1,
 493                           pitch, src_bo, src_offset, I915_TILING_NONE,
 494                           pitch, dst_bo, dst_offset, I915_TILING_NONE,
 495                           0, 0, /* src x/y */
 496                           0, 0, /* dst x/y */
 497                           pitch, height, /* w, h */
 498                           GL_COPY);
 499    assert(ok);
 500
 501    src_offset += pitch * height;
 502    dst_offset += pitch * height;
 503    size -= pitch * height;
 504    assert (size < (1 << 15));
 505    assert ((size & 3) == 0); /* Pitch must be DWORD aligned */
 506    if (size != 0) {
 507       ok = intelEmitCopyBlit(intel, 1,
 508                              size, src_bo, src_offset, I915_TILING_NONE,
 509                              size, dst_bo, dst_offset, I915_TILING_NONE,
 510                              0, 0, /* src x/y */
 511                              0, 0, /* dst x/y */
 512                              size, 1, /* w, h */
 513                              GL_COPY);
 514       assert(ok);
 515    }
 516 }
 517
 518 /**
 519  * Used to initialize the alpha value of an ARGB8888 teximage after
 520  * loading it from an XRGB8888 source.
 521  *
 522  * This is very common with glCopyTexImage2D().
 523  */
 524 void
 525 intel_set_teximage_alpha_to_one(struct gl_context *ctx,
 526                                 struct intel_texture_image *intel_image)
 527 {
 528    struct intel_context *intel = intel_context(ctx);
 529    unsigned int image_x, image_y;
 530    uint32_t x1, y1, x2, y2;
 531    uint32_t BR13, CMD;
 532    int pitch, cpp;
 533    drm_intel_bo *aper_array[2];
 534    struct intel_region *region = intel_image->mt->region;
 535    BATCH_LOCALS;
 536
 537    assert(intel_image->base.Base.TexFormat == MESA_FORMAT_ARGB8888);
 538
 539    /* get dest x/y in destination texture */
 540    intel_miptree_get_image_offset(intel_image->mt,
 541                                   intel_image->base.Base.Level,
 542                                   intel_image->base.Base.Face,
 543                                   0,
 544                                   &image_x, &image_y);
 545
 546    x1 = image_x;
 547    y1 = image_y;
 548    x2 = image_x + intel_image->base.Base.Width;
 549    y2 = image_y + intel_image->base.Base.Height;
 550
 551    pitch = region->pitch;
 552    cpp = region->cpp;
 553
 554    DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
 555        __FUNCTION__,
 556        intel_image->mt->region->buffer, (pitch * cpp),
 557        x1, y1, x2 - x1, y2 - y1);
 558
 559    BR13 = br13_for_cpp(cpp) | 0xf0 << 16;
 560    CMD = XY_COLOR_BLT_CMD;
 561    CMD |= XY_BLT_WRITE_ALPHA;
 562
 563    assert(region->tiling != I915_TILING_Y);
 564
 565 #ifndef I915
 566    if (region->tiling != I915_TILING_NONE) {
 567       CMD |= XY_DST_TILED;
 568       pitch /= 4;
 569    }
 570 #endif
 571    BR13 |= (pitch * cpp);
 572
 573    /* do space check before going any further */
 574    aper_array[0] = intel->batch.bo;
 575    aper_array[1] = region->buffer;
 576
 577    if (drm_intel_bufmgr_check_aperture_space(aper_array,
 578                                              ARRAY_SIZE(aper_array)) != 0) {
 579       intel_batchbuffer_flush(intel);
 580    }
 581
 582    BEGIN_BATCH_BLT(6);
 583    OUT_BATCH(CMD);
 584    OUT_BATCH(BR13);
 585    OUT_BATCH((y1 << 16) | x1);
 586    OUT_BATCH((y2 << 16) | x2);
 587    OUT_RELOC_FENCED(region->buffer,
 588                     I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 589                     0);
 590    OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
 591    ADVANCE_BATCH();
 592
 593    intel_batchbuffer_emit_mi_flush(intel);
 594 }