1 /**************************************************************************
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
36 #include "intel_batchbuffer.h"
37 #include "intel_blit.h"
38 #include "intel_buffers.h"
39 #include "intel_context.h"
40 #include "intel_fbo.h"
41 #include "intel_reg.h"
42 #include "intel_regions.h"
44 #define FILE_DEBUG_FLAG DEBUG_BLIT
47 * Copy the back color buffer to the front color buffer.
48 * Used for SwapBuffers().
51 intelCopyBuffer(const __DRIdrawablePrivate
* dPriv
,
52 const drm_clip_rect_t
* rect
)
55 struct intel_context
*intel
;
56 const intelScreenPrivate
*intelScreen
;
58 DBG("%s\n", __FUNCTION__
);
62 intel
= intelScreenContext(dPriv
->driScreenPriv
->private);
66 intelScreen
= intel
->intelScreen
;
68 /* The LOCK_HARDWARE is required for the cliprects. Buffer offsets
69 * should work regardless.
73 if (dPriv
&& dPriv
->numClipRects
) {
74 struct intel_framebuffer
*intel_fb
= dPriv
->driverPrivate
;
75 struct intel_region
*src
, *dst
;
76 int nbox
= dPriv
->numClipRects
;
77 drm_clip_rect_t
*pbox
= dPriv
->pClipRects
;
79 int src_pitch
, dst_pitch
;
80 unsigned short src_x
, src_y
;
83 dri_bo
*aper_array
[3];
85 src
= intel_get_rb_region(&intel_fb
->Base
, BUFFER_BACK_LEFT
);
86 dst
= intel_get_rb_region(&intel_fb
->Base
, BUFFER_FRONT_LEFT
);
88 src_pitch
= src
->pitch
* src
->cpp
;
89 dst_pitch
= dst
->pitch
* dst
->cpp
;
94 ASSERT(intel_fb
->Base
.Name
== 0); /* Not a user-created FBO */
97 ASSERT(src
->cpp
== dst
->cpp
);
100 BR13
= (0xCC << 16) | (1 << 24);
101 CMD
= XY_SRC_COPY_BLT_CMD
;
104 BR13
= (0xCC << 16) | (1 << 24) | (1 << 25);
105 CMD
= XY_SRC_COPY_BLT_CMD
| XY_BLT_WRITE_ALPHA
| XY_BLT_WRITE_RGB
;
109 if (src
->tiling
!= I915_TILING_NONE
) {
113 if (dst
->tiling
!= I915_TILING_NONE
) {
118 /* do space/cliprects check before going any further */
119 intel_batchbuffer_require_space(intel
->batch
, 8 * 4,
120 REFERENCES_CLIPRECTS
);
122 aper_array
[0] = intel
->batch
->buf
;
123 aper_array
[1] = dst
->buffer
;
124 aper_array
[2] = src
->buffer
;
126 if (dri_bufmgr_check_aperture_space(aper_array
, 3) != 0) {
127 intel_batchbuffer_flush(intel
->batch
);
131 for (i
= 0; i
< nbox
; i
++, pbox
++) {
132 drm_clip_rect_t box
= *pbox
;
135 if (!intel_intersect_cliprects(&box
, &box
, rect
))
139 if (box
.x1
>= box
.x2
||
143 assert(box
.x1
< box
.x2
);
144 assert(box
.y1
< box
.y2
);
145 src_x
= box
.x1
- dPriv
->x
+ dPriv
->backX
;
146 src_y
= box
.y1
- dPriv
->y
+ dPriv
->backY
;
148 BEGIN_BATCH(8, REFERENCES_CLIPRECTS
);
150 OUT_BATCH(BR13
| dst_pitch
);
151 OUT_BATCH((box
.y1
<< 16) | box
.x1
);
152 OUT_BATCH((box
.y2
<< 16) | box
.x2
);
154 OUT_RELOC(dst
->buffer
,
155 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
157 OUT_BATCH((src_y
<< 16) | src_x
);
158 OUT_BATCH(src_pitch
);
159 OUT_RELOC(src
->buffer
,
160 I915_GEM_DOMAIN_RENDER
, 0,
165 /* Flush the rendering and the batch so that the results all land on the
166 * screen in a timely fashion.
168 intel_batchbuffer_emit_mi_flush(intel
->batch
);
169 intel_batchbuffer_flush(intel
->batch
);
172 UNLOCK_HARDWARE(intel
);
179 intelEmitFillBlit(struct intel_context
*intel
,
185 GLshort x
, GLshort y
,
186 GLshort w
, GLshort h
,
198 BR13
= (0xF0 << 16) | (1 << 24);
199 CMD
= XY_COLOR_BLT_CMD
;
202 BR13
= (0xF0 << 16) | (1 << 24) | (1 << 25);
203 CMD
= XY_COLOR_BLT_CMD
| XY_BLT_WRITE_ALPHA
| XY_BLT_WRITE_RGB
;
209 if (dst_tiling
!= I915_TILING_NONE
) {
215 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
216 __FUNCTION__
, dst_buffer
, dst_pitch
, dst_offset
, x
, y
, w
, h
);
221 BEGIN_BATCH(6, NO_LOOP_CLIPRECTS
);
223 OUT_BATCH(BR13
| dst_pitch
);
224 OUT_BATCH((y
<< 16) | x
);
225 OUT_BATCH(((y
+ h
) << 16) | (x
+ w
));
226 OUT_RELOC(dst_buffer
,
227 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
233 static GLuint
translate_raster_op(GLenum logicop
)
236 case GL_CLEAR
: return 0x00;
237 case GL_AND
: return 0x88;
238 case GL_AND_REVERSE
: return 0x44;
239 case GL_COPY
: return 0xCC;
240 case GL_AND_INVERTED
: return 0x22;
241 case GL_NOOP
: return 0xAA;
242 case GL_XOR
: return 0x66;
243 case GL_OR
: return 0xEE;
244 case GL_NOR
: return 0x11;
245 case GL_EQUIV
: return 0x99;
246 case GL_INVERT
: return 0x55;
247 case GL_OR_REVERSE
: return 0xDD;
248 case GL_COPY_INVERTED
: return 0x33;
249 case GL_OR_INVERTED
: return 0xBB;
250 case GL_NAND
: return 0x77;
251 case GL_SET
: return 0xFF;
260 intelEmitCopyBlit(struct intel_context
*intel
,
270 GLshort src_x
, GLshort src_y
,
271 GLshort dst_x
, GLshort dst_y
,
272 GLshort w
, GLshort h
,
276 int dst_y2
= dst_y
+ h
;
277 int dst_x2
= dst_x
+ w
;
278 dri_bo
*aper_array
[3];
281 /* do space/cliprects check before going any further */
282 intel_batchbuffer_require_space(intel
->batch
, 8 * 4, NO_LOOP_CLIPRECTS
);
284 aper_array
[0] = intel
->batch
->buf
;
285 aper_array
[1] = dst_buffer
;
286 aper_array
[2] = src_buffer
;
288 if (dri_bufmgr_check_aperture_space(aper_array
, 3) != 0) {
289 intel_batchbuffer_flush(intel
->batch
);
293 DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
295 src_buffer
, src_pitch
, src_offset
, src_x
, src_y
,
296 dst_buffer
, dst_pitch
, dst_offset
, dst_x
, dst_y
, w
, h
);
301 BR13
= translate_raster_op(logic_op
) << 16;
308 CMD
= XY_SRC_COPY_BLT_CMD
;
311 BR13
|= (1 << 24) | (1 << 25);
312 CMD
= XY_SRC_COPY_BLT_CMD
| XY_BLT_WRITE_ALPHA
| XY_BLT_WRITE_RGB
;
319 if (dst_tiling
!= I915_TILING_NONE
) {
323 if (src_tiling
!= I915_TILING_NONE
) {
329 if (dst_y2
<= dst_y
|| dst_x2
<= dst_x
) {
333 /* Initial y values don't seem to work with negative pitches. If
334 * we adjust the offsets manually (below), it seems to work fine.
336 * On the other hand, if we always adjust, the hardware doesn't
337 * know which blit directions to use, so overlapping copypixels get
340 if (dst_pitch
> 0 && src_pitch
> 0) {
341 assert(dst_x
< dst_x2
);
342 assert(dst_y
< dst_y2
);
344 BEGIN_BATCH(8, NO_LOOP_CLIPRECTS
);
346 OUT_BATCH(BR13
| dst_pitch
);
347 OUT_BATCH((dst_y
<< 16) | dst_x
);
348 OUT_BATCH((dst_y2
<< 16) | dst_x2
);
349 OUT_RELOC(dst_buffer
,
350 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
352 OUT_BATCH((src_y
<< 16) | src_x
);
353 OUT_BATCH(src_pitch
);
354 OUT_RELOC(src_buffer
,
355 I915_GEM_DOMAIN_RENDER
, 0,
360 assert(dst_x
< dst_x2
);
363 BEGIN_BATCH(8, NO_LOOP_CLIPRECTS
);
365 OUT_BATCH(BR13
| ((uint16_t)dst_pitch
));
366 OUT_BATCH((0 << 16) | dst_x
);
367 OUT_BATCH((h
<< 16) | dst_x2
);
368 OUT_RELOC(dst_buffer
,
369 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
370 dst_offset
+ dst_y
* dst_pitch
);
371 OUT_BATCH((0 << 16) | src_x
);
372 OUT_BATCH(src_pitch
);
373 OUT_RELOC(src_buffer
,
374 I915_GEM_DOMAIN_RENDER
, 0,
375 src_offset
+ src_y
* src_pitch
);
378 intel_batchbuffer_emit_mi_flush(intel
->batch
);
383 * Use blitting to clear the renderbuffers named by 'flags'.
384 * Note: we can't use the ctx->DrawBuffer->_ColorDrawBufferIndexes field
385 * since that might include software renderbuffers or renderbuffers
386 * which we're clearing with triangles.
387 * \param mask bitmask of BUFFER_BIT_* values indicating buffers to clear
390 intelClearWithBlit(GLcontext
*ctx
, GLbitfield mask
)
392 struct intel_context
*intel
= intel_context(ctx
);
393 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
395 GLbitfield skipBuffers
= 0;
399 * Compute values for clearing the buffers.
402 if (mask
& BUFFER_BIT_DEPTH
) {
403 clear_depth
= (GLuint
) (fb
->_DepthMax
* ctx
->Depth
.Clear
);
405 if (mask
& BUFFER_BIT_STENCIL
) {
406 clear_depth
|= (ctx
->Stencil
.Clear
& 0xff) << 24;
409 /* If clearing both depth and stencil, skip BUFFER_BIT_STENCIL in
412 if ((mask
& BUFFER_BIT_DEPTH
) && (mask
& BUFFER_BIT_STENCIL
)) {
413 skipBuffers
= BUFFER_BIT_STENCIL
;
416 /* XXX Move this flush/lock into the following conditional? */
417 intelFlush(&intel
->ctx
);
418 LOCK_HARDWARE(intel
);
420 if (intel
->numClipRects
) {
421 GLint cx
, cy
, cw
, ch
;
422 drm_clip_rect_t clear
;
425 /* Get clear bounds after locking */
432 /* clearing a window */
434 /* flip top to bottom */
435 clear
.x1
= cx
+ intel
->drawX
;
436 clear
.y1
= intel
->driDrawable
->y
+ intel
->driDrawable
->h
- cy
- ch
;
437 clear
.x2
= clear
.x1
+ cw
;
438 clear
.y2
= clear
.y1
+ ch
;
442 assert(intel
->numClipRects
== 1);
443 assert(intel
->pClipRects
== &intel
->fboRect
);
446 clear
.x2
= clear
.x1
+ cw
;
447 clear
.y2
= clear
.y1
+ ch
;
448 /* no change to mask */
451 for (i
= 0; i
< intel
->numClipRects
; i
++) {
452 const drm_clip_rect_t
*box
= &intel
->pClipRects
[i
];
455 GLuint clearMask
= mask
; /* use copy, since we modify it below */
456 GLboolean all
= (cw
== fb
->Width
&& ch
== fb
->Height
);
459 intel_intersect_cliprects(&b
, &clear
, box
);
465 if (b
.x1
>= b
.x2
|| b
.y1
>= b
.y2
)
469 _mesa_printf("clear %d,%d..%d,%d, mask %x\n",
470 b
.x1
, b
.y1
, b
.x2
, b
.y2
, mask
);
472 /* Loop over all renderbuffers */
473 for (buf
= 0; buf
< BUFFER_COUNT
&& clearMask
; buf
++) {
474 const GLbitfield bufBit
= 1 << buf
;
475 if ((clearMask
& bufBit
) && !(bufBit
& skipBuffers
)) {
476 /* OK, clear this renderbuffer */
477 struct intel_region
*irb_region
=
478 intel_get_rb_region(fb
, buf
);
479 dri_bo
*write_buffer
=
480 intel_region_buffer(intel
, irb_region
,
481 all
? INTEL_WRITE_FULL
:
490 pitch
= irb_region
->pitch
;
491 cpp
= irb_region
->cpp
;
493 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
495 irb_region
->buffer
, (pitch
* cpp
),
496 irb_region
->draw_offset
,
497 b
.x1
, b
.y1
, b
.x2
- b
.x1
, b
.y2
- b
.y1
);
500 CMD
= XY_COLOR_BLT_CMD
;
502 /* Setup the blit command */
504 BR13
|= (1 << 24) | (1 << 25);
505 if (buf
== BUFFER_DEPTH
|| buf
== BUFFER_STENCIL
) {
506 if (clearMask
& BUFFER_BIT_DEPTH
)
507 CMD
|= XY_BLT_WRITE_RGB
;
508 if (clearMask
& BUFFER_BIT_STENCIL
)
509 CMD
|= XY_BLT_WRITE_ALPHA
;
513 CMD
|= XY_BLT_WRITE_ALPHA
| XY_BLT_WRITE_RGB
;
517 ASSERT(cpp
== 2 || cpp
== 0);
522 if (irb_region
->tiling
!= I915_TILING_NONE
) {
527 BR13
|= (pitch
* cpp
);
529 if (buf
== BUFFER_DEPTH
|| buf
== BUFFER_STENCIL
) {
530 clearVal
= clear_depth
;
533 clearVal
= (cpp
== 4)
534 ? intel
->ClearColor8888
: intel
->ClearColor565
;
537 _mesa_debug(ctx, "hardware blit clear buf %d rb id %d\n",
538 buf, irb->Base.Name);
540 intel_wait_flips(intel
);
545 BEGIN_BATCH(6, REFERENCES_CLIPRECTS
);
548 OUT_BATCH((b
.y1
<< 16) | b
.x1
);
549 OUT_BATCH((b
.y2
<< 16) | b
.x2
);
550 OUT_RELOC(write_buffer
,
551 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
552 irb_region
->draw_offset
);
555 clearMask
&= ~bufBit
; /* turn off bit, for faster loop exit */
559 intel_batchbuffer_emit_mi_flush(intel
->batch
);
562 UNLOCK_HARDWARE(intel
);
566 intelEmitImmediateColorExpandBlit(struct intel_context
*intel
,
568 GLubyte
*src_bits
, GLuint src_size
,
574 GLshort x
, GLshort y
,
575 GLshort w
, GLshort h
,
578 int dwords
= ALIGN(src_size
, 8) / 4;
579 uint32_t opcode
, br13
, blit_cmd
;
581 assert( logic_op
- GL_CLEAR
>= 0 );
582 assert( logic_op
- GL_CLEAR
< 0x10 );
589 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
591 dst_buffer
, dst_pitch
, dst_offset
, x
, y
, w
, h
, src_size
, dwords
);
593 intel_batchbuffer_require_space( intel
->batch
,
597 REFERENCES_CLIPRECTS
);
599 opcode
= XY_SETUP_BLT_CMD
;
601 opcode
|= XY_BLT_WRITE_ALPHA
| XY_BLT_WRITE_RGB
;
603 if (dst_tiling
!= I915_TILING_NONE
) {
604 opcode
|= XY_DST_TILED
;
609 br13
= dst_pitch
| (translate_raster_op(logic_op
) << 16) | (1 << 29);
615 blit_cmd
= XY_TEXT_IMMEDIATE_BLIT_CMD
| XY_TEXT_BYTE_PACKED
; /* packing? */
616 if (dst_tiling
!= I915_TILING_NONE
)
617 blit_cmd
|= XY_DST_TILED
;
619 BEGIN_BATCH(8 + 3, REFERENCES_CLIPRECTS
);
622 OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
623 OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
624 OUT_RELOC(dst_buffer
,
625 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
627 OUT_BATCH(0); /* bg */
628 OUT_BATCH(fg_color
); /* fg */
629 OUT_BATCH(0); /* pattern base addr */
631 OUT_BATCH(blit_cmd
| ((3 - 2) + dwords
));
632 OUT_BATCH((y
<< 16) | x
);
633 OUT_BATCH(((y
+ h
) << 16) | (x
+ w
));
636 intel_batchbuffer_data( intel
->batch
,
639 REFERENCES_CLIPRECTS
);
641 intel_batchbuffer_emit_mi_flush(intel
->batch
);