src/mesa/drivers/dri/intel/intel_blit.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29 #include <stdio.h>
  30 #include <errno.h>
  31
  32 #include "mtypes.h"
  33 #include "context.h"
  34 #include "enums.h"
  35
  36 #include "intel_batchbuffer.h"
  37 #include "intel_blit.h"
  38 #include "intel_buffers.h"
  39 #include "intel_context.h"
  40 #include "intel_fbo.h"
  41 #include "intel_reg.h"
  42 #include "intel_regions.h"
  43
  44 #define FILE_DEBUG_FLAG DEBUG_BLIT
  45
  46 /**
  47  * Copy the back color buffer to the front color buffer.
  48  * Used for SwapBuffers().
  49  */
  50 void
  51 intelCopyBuffer(const __DRIdrawablePrivate * dPriv,
  52                 const drm_clip_rect_t * rect)
  53 {
  54
  55    struct intel_context *intel;
  56    const intelScreenPrivate *intelScreen;
  57
  58    DBG("%s\n", __FUNCTION__);
  59
  60    assert(dPriv);
  61
  62    intel = intelScreenContext(dPriv->driScreenPriv->private);
  63    if (!intel)
  64       return;
  65
  66    intelScreen = intel->intelScreen;
  67
  68    /* The LOCK_HARDWARE is required for the cliprects.  Buffer offsets
  69     * should work regardless.
  70     */
  71    LOCK_HARDWARE(intel);
  72
  73    if (dPriv && dPriv->numClipRects) {
  74       struct intel_framebuffer *intel_fb = dPriv->driverPrivate;
  75       struct intel_region *src, *dst;
  76       int nbox = dPriv->numClipRects;
  77       drm_clip_rect_t *pbox = dPriv->pClipRects;
  78       int cpp;
  79       int src_pitch, dst_pitch;
  80       unsigned short src_x, src_y;
  81       int BR13, CMD;
  82       int i;
  83       dri_bo *aper_array[3];
  84
  85       src = intel_get_rb_region(&intel_fb->Base, BUFFER_BACK_LEFT);
  86       dst = intel_get_rb_region(&intel_fb->Base, BUFFER_FRONT_LEFT);
  87
  88       src_pitch = src->pitch * src->cpp;
  89       dst_pitch = dst->pitch * dst->cpp;
  90
  91       cpp = src->cpp;
  92
  93       ASSERT(intel_fb);
  94       ASSERT(intel_fb->Base.Name == 0);    /* Not a user-created FBO */
  95       ASSERT(src);
  96       ASSERT(dst);
  97       ASSERT(src->cpp == dst->cpp);
  98
  99       if (cpp == 2) {
 100          BR13 = (0xCC << 16) | (1 << 24);
 101          CMD = XY_SRC_COPY_BLT_CMD;
 102       }
 103       else {
 104          BR13 = (0xCC << 16) | (1 << 24) | (1 << 25);
 105          CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 106       }
 107
 108 #ifndef I915
 109       if (src->tiling != I915_TILING_NONE) {
 110          CMD |= XY_SRC_TILED;
 111          src_pitch /= 4;
 112       }
 113       if (dst->tiling != I915_TILING_NONE) {
 114          CMD |= XY_DST_TILED;
 115          dst_pitch /= 4;
 116       }
 117 #endif
 118       /* do space/cliprects check before going any further */
 119       intel_batchbuffer_require_space(intel->batch, 8 * 4,
 120                                       REFERENCES_CLIPRECTS);
 121    again:
 122       aper_array[0] = intel->batch->buf;
 123       aper_array[1] = dst->buffer;
 124       aper_array[2] = src->buffer;
 125
 126       if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
 127         intel_batchbuffer_flush(intel->batch);
 128         goto again;
 129       }
 130
 131       for (i = 0; i < nbox; i++, pbox++) {
 132          drm_clip_rect_t box = *pbox;
 133
 134          if (rect) {
 135             if (!intel_intersect_cliprects(&box, &box, rect))
 136                continue;
 137          }
 138
 139          if (box.x1 >= box.x2 ||
 140              box.y1 >= box.y2)
 141             continue;
 142
 143          assert(box.x1 < box.x2);
 144          assert(box.y1 < box.y2);
 145          src_x = box.x1 - dPriv->x + dPriv->backX;
 146          src_y = box.y1 - dPriv->y + dPriv->backY;
 147
 148          BEGIN_BATCH(8, REFERENCES_CLIPRECTS);
 149          OUT_BATCH(CMD);
 150          OUT_BATCH(BR13 | dst_pitch);
 151          OUT_BATCH((box.y1 << 16) | box.x1);
 152          OUT_BATCH((box.y2 << 16) | box.x2);
 153
 154          OUT_RELOC(dst->buffer,
 155                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 156                    0);
 157          OUT_BATCH((src_y << 16) | src_x);
 158          OUT_BATCH(src_pitch);
 159          OUT_RELOC(src->buffer,
 160                    I915_GEM_DOMAIN_RENDER, 0,
 161                    0);
 162          ADVANCE_BATCH();
 163       }
 164
 165       /* Flush the rendering and the batch so that the results all land on the
 166        * screen in a timely fashion.
 167        */
 168       intel_batchbuffer_emit_mi_flush(intel->batch);
 169       intel_batchbuffer_flush(intel->batch);
 170    }
 171
 172    UNLOCK_HARDWARE(intel);
 173 }
 174
 175
 176
 177
 178 void
 179 intelEmitFillBlit(struct intel_context *intel,
 180                   GLuint cpp,
 181                   GLshort dst_pitch,
 182                   dri_bo *dst_buffer,
 183                   GLuint dst_offset,
 184                   uint32_t dst_tiling,
 185                   GLshort x, GLshort y,
 186                   GLshort w, GLshort h,
 187                   GLuint color)
 188 {
 189    GLuint BR13, CMD;
 190    BATCH_LOCALS;
 191
 192    dst_pitch *= cpp;
 193
 194    switch (cpp) {
 195    case 1:
 196    case 2:
 197    case 3:
 198       BR13 = (0xF0 << 16) | (1 << 24);
 199       CMD = XY_COLOR_BLT_CMD;
 200       break;
 201    case 4:
 202       BR13 = (0xF0 << 16) | (1 << 24) | (1 << 25);
 203       CMD = XY_COLOR_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 204       break;
 205    default:
 206       return;
 207    }
 208 #ifndef I915
 209    if (dst_tiling != I915_TILING_NONE) {
 210       CMD |= XY_DST_TILED;
 211       dst_pitch /= 4;
 212    }
 213 #endif
 214
 215    DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
 216        __FUNCTION__, dst_buffer, dst_pitch, dst_offset, x, y, w, h);
 217
 218    assert(w > 0);
 219    assert(h > 0);
 220
 221    BEGIN_BATCH(6, NO_LOOP_CLIPRECTS);
 222    OUT_BATCH(CMD);
 223    OUT_BATCH(BR13 | dst_pitch);
 224    OUT_BATCH((y << 16) | x);
 225    OUT_BATCH(((y + h) << 16) | (x + w));
 226    OUT_RELOC(dst_buffer,
 227              I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 228              dst_offset);
 229    OUT_BATCH(color);
 230    ADVANCE_BATCH();
 231 }
 232
 233 static GLuint translate_raster_op(GLenum logicop)
 234 {
 235    switch(logicop) {
 236    case GL_CLEAR: return 0x00;
 237    case GL_AND: return 0x88;
 238    case GL_AND_REVERSE: return 0x44;
 239    case GL_COPY: return 0xCC;
 240    case GL_AND_INVERTED: return 0x22;
 241    case GL_NOOP: return 0xAA;
 242    case GL_XOR: return 0x66;
 243    case GL_OR: return 0xEE;
 244    case GL_NOR: return 0x11;
 245    case GL_EQUIV: return 0x99;
 246    case GL_INVERT: return 0x55;
 247    case GL_OR_REVERSE: return 0xDD;
 248    case GL_COPY_INVERTED: return 0x33;
 249    case GL_OR_INVERTED: return 0xBB;
 250    case GL_NAND: return 0x77;
 251    case GL_SET: return 0xFF;
 252    default: return 0;
 253    }
 254 }
 255
 256
 257 /* Copy BitBlt
 258  */
 259 void
 260 intelEmitCopyBlit(struct intel_context *intel,
 261                   GLuint cpp,
 262                   GLshort src_pitch,
 263                   dri_bo *src_buffer,
 264                   GLuint src_offset,
 265                   uint32_t src_tiling,
 266                   GLshort dst_pitch,
 267                   dri_bo *dst_buffer,
 268                   GLuint dst_offset,
 269                   uint32_t dst_tiling,
 270                   GLshort src_x, GLshort src_y,
 271                   GLshort dst_x, GLshort dst_y,
 272                   GLshort w, GLshort h,
 273                   GLenum logic_op)
 274 {
 275    GLuint CMD, BR13;
 276    int dst_y2 = dst_y + h;
 277    int dst_x2 = dst_x + w;
 278    dri_bo *aper_array[3];
 279    BATCH_LOCALS;
 280
 281    /* do space/cliprects check before going any further */
 282    intel_batchbuffer_require_space(intel->batch, 8 * 4, NO_LOOP_CLIPRECTS);
 283  again:
 284    aper_array[0] = intel->batch->buf;
 285    aper_array[1] = dst_buffer;
 286    aper_array[2] = src_buffer;
 287
 288    if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
 289       intel_batchbuffer_flush(intel->batch);
 290       goto again;
 291    }
 292
 293    DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
 294        __FUNCTION__,
 295        src_buffer, src_pitch, src_offset, src_x, src_y,
 296        dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
 297
 298    src_pitch *= cpp;
 299    dst_pitch *= cpp;
 300
 301    BR13 = translate_raster_op(logic_op) << 16;
 302
 303    switch (cpp) {
 304    case 1:
 305    case 2:
 306    case 3:
 307       BR13 |= (1 << 24);
 308       CMD = XY_SRC_COPY_BLT_CMD;
 309       break;
 310    case 4:
 311       BR13 |= (1 << 24) | (1 << 25);
 312       CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 313       break;
 314    default:
 315       return;
 316    }
 317
 318 #ifndef I915
 319    if (dst_tiling != I915_TILING_NONE) {
 320       CMD |= XY_DST_TILED;
 321       dst_pitch /= 4;
 322    }
 323    if (src_tiling != I915_TILING_NONE) {
 324       CMD |= XY_SRC_TILED;
 325       src_pitch /= 4;
 326    }
 327 #endif
 328
 329    if (dst_y2 <= dst_y || dst_x2 <= dst_x) {
 330       return;
 331    }
 332
 333    /* Initial y values don't seem to work with negative pitches.  If
 334     * we adjust the offsets manually (below), it seems to work fine.
 335     *
 336     * On the other hand, if we always adjust, the hardware doesn't
 337     * know which blit directions to use, so overlapping copypixels get
 338     * the wrong result.
 339     */
 340    if (dst_pitch > 0 && src_pitch > 0) {
 341       assert(dst_x < dst_x2);
 342       assert(dst_y < dst_y2);
 343
 344       BEGIN_BATCH(8, NO_LOOP_CLIPRECTS);
 345       OUT_BATCH(CMD);
 346       OUT_BATCH(BR13 | dst_pitch);
 347       OUT_BATCH((dst_y << 16) | dst_x);
 348       OUT_BATCH((dst_y2 << 16) | dst_x2);
 349       OUT_RELOC(dst_buffer,
 350                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 351                 dst_offset);
 352       OUT_BATCH((src_y << 16) | src_x);
 353       OUT_BATCH(src_pitch);
 354       OUT_RELOC(src_buffer,
 355                 I915_GEM_DOMAIN_RENDER, 0,
 356                 src_offset);
 357       ADVANCE_BATCH();
 358    }
 359    else {
 360       assert(dst_x < dst_x2);
 361       assert(h > 0);
 362
 363       BEGIN_BATCH(8, NO_LOOP_CLIPRECTS);
 364       OUT_BATCH(CMD);
 365       OUT_BATCH(BR13 | ((uint16_t)dst_pitch));
 366       OUT_BATCH((0 << 16) | dst_x);
 367       OUT_BATCH((h << 16) | dst_x2);
 368       OUT_RELOC(dst_buffer,
 369                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 370                 dst_offset + dst_y * dst_pitch);
 371       OUT_BATCH((0 << 16) | src_x);
 372       OUT_BATCH(src_pitch);
 373       OUT_RELOC(src_buffer,
 374                 I915_GEM_DOMAIN_RENDER, 0,
 375                 src_offset + src_y * src_pitch);
 376       ADVANCE_BATCH();
 377    }
 378    intel_batchbuffer_emit_mi_flush(intel->batch);
 379 }
 380
 381
 382 /**
 383  * Use blitting to clear the renderbuffers named by 'flags'.
 384  * Note: we can't use the ctx->DrawBuffer->_ColorDrawBufferIndexes field
 385  * since that might include software renderbuffers or renderbuffers
 386  * which we're clearing with triangles.
 387  * \param mask  bitmask of BUFFER_BIT_* values indicating buffers to clear
 388  */
 389 void
 390 intelClearWithBlit(GLcontext *ctx, GLbitfield mask)
 391 {
 392    struct intel_context *intel = intel_context(ctx);
 393    struct gl_framebuffer *fb = ctx->DrawBuffer;
 394    GLuint clear_depth;
 395    GLbitfield skipBuffers = 0;
 396    BATCH_LOCALS;
 397
 398    /*
 399     * Compute values for clearing the buffers.
 400     */
 401    clear_depth = 0;
 402    if (mask & BUFFER_BIT_DEPTH) {
 403       clear_depth = (GLuint) (fb->_DepthMax * ctx->Depth.Clear);
 404    }
 405    if (mask & BUFFER_BIT_STENCIL) {
 406       clear_depth |= (ctx->Stencil.Clear & 0xff) << 24;
 407    }
 408
 409    /* If clearing both depth and stencil, skip BUFFER_BIT_STENCIL in
 410     * the loop below.
 411     */
 412    if ((mask & BUFFER_BIT_DEPTH) && (mask & BUFFER_BIT_STENCIL)) {
 413       skipBuffers = BUFFER_BIT_STENCIL;
 414    }
 415
 416    /* XXX Move this flush/lock into the following conditional? */
 417    intelFlush(&intel->ctx);
 418    LOCK_HARDWARE(intel);
 419
 420    if (intel->numClipRects) {
 421       GLint cx, cy, cw, ch;
 422       drm_clip_rect_t clear;
 423       int i;
 424
 425       /* Get clear bounds after locking */
 426       cx = fb->_Xmin;
 427       cy = fb->_Ymin;
 428       cw = fb->_Xmax - cx;
 429       ch = fb->_Ymax - cy;
 430
 431       if (fb->Name == 0) {
 432          /* clearing a window */
 433
 434          /* flip top to bottom */
 435          clear.x1 = cx + intel->drawX;
 436          clear.y1 = intel->driDrawable->y + intel->driDrawable->h - cy - ch;
 437          clear.x2 = clear.x1 + cw;
 438          clear.y2 = clear.y1 + ch;
 439       }
 440       else {
 441          /* clearing FBO */
 442          assert(intel->numClipRects == 1);
 443          assert(intel->pClipRects == &intel->fboRect);
 444          clear.x1 = cx;
 445          clear.y1 = cy;
 446          clear.x2 = clear.x1 + cw;
 447          clear.y2 = clear.y1 + ch;
 448          /* no change to mask */
 449       }
 450
 451       for (i = 0; i < intel->numClipRects; i++) {
 452          const drm_clip_rect_t *box = &intel->pClipRects[i];
 453          drm_clip_rect_t b;
 454          GLuint buf;
 455          GLuint clearMask = mask;      /* use copy, since we modify it below */
 456          GLboolean all = (cw == fb->Width && ch == fb->Height);
 457
 458          if (!all) {
 459             intel_intersect_cliprects(&b, &clear, box);
 460          }
 461          else {
 462             b = *box;
 463          }
 464
 465          if (b.x1 >= b.x2 || b.y1 >= b.y2)
 466             continue;
 467
 468          if (0)
 469             _mesa_printf("clear %d,%d..%d,%d, mask %x\n",
 470                          b.x1, b.y1, b.x2, b.y2, mask);
 471
 472          /* Loop over all renderbuffers */
 473          for (buf = 0; buf < BUFFER_COUNT && clearMask; buf++) {
 474             const GLbitfield bufBit = 1 << buf;
 475             if ((clearMask & bufBit) && !(bufBit & skipBuffers)) {
 476                /* OK, clear this renderbuffer */
 477                struct intel_region *irb_region =
 478                   intel_get_rb_region(fb, buf);
 479                dri_bo *write_buffer =
 480                   intel_region_buffer(intel, irb_region,
 481                                       all ? INTEL_WRITE_FULL :
 482                                       INTEL_WRITE_PART);
 483
 484                GLuint clearVal;
 485                GLint pitch, cpp;
 486                GLuint BR13, CMD;
 487
 488                ASSERT(irb_region);
 489
 490                pitch = irb_region->pitch;
 491                cpp = irb_region->cpp;
 492
 493                DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
 494                    __FUNCTION__,
 495                    irb_region->buffer, (pitch * cpp),
 496                    irb_region->draw_offset,
 497                    b.x1, b.y1, b.x2 - b.x1, b.y2 - b.y1);
 498
 499                BR13 = 0xf0 << 16;
 500                CMD = XY_COLOR_BLT_CMD;
 501
 502                /* Setup the blit command */
 503                if (cpp == 4) {
 504                   BR13 |= (1 << 24) | (1 << 25);
 505                   if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) {
 506                      if (clearMask & BUFFER_BIT_DEPTH)
 507                         CMD |= XY_BLT_WRITE_RGB;
 508                      if (clearMask & BUFFER_BIT_STENCIL)
 509                         CMD |= XY_BLT_WRITE_ALPHA;
 510                   }
 511                   else {
 512                      /* clearing RGBA */
 513                      CMD |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 514                   }
 515                }
 516                else {
 517                   ASSERT(cpp == 2 || cpp == 0);
 518                   BR13 |= (1 << 24);
 519                }
 520
 521 #ifndef I915
 522                if (irb_region->tiling != I915_TILING_NONE) {
 523                   CMD |= XY_DST_TILED;
 524                   pitch /= 4;
 525                }
 526 #endif
 527                BR13 |= (pitch * cpp);
 528
 529                if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) {
 530                   clearVal = clear_depth;
 531                }
 532                else {
 533                   clearVal = (cpp == 4)
 534                      ? intel->ClearColor8888 : intel->ClearColor565;
 535                }
 536                /*
 537                   _mesa_debug(ctx, "hardware blit clear buf %d rb id %d\n",
 538                   buf, irb->Base.Name);
 539                 */
 540                intel_wait_flips(intel);
 541
 542                assert(b.x1 < b.x2);
 543                assert(b.y1 < b.y2);
 544
 545                BEGIN_BATCH(6, REFERENCES_CLIPRECTS);
 546                OUT_BATCH(CMD);
 547                OUT_BATCH(BR13);
 548                OUT_BATCH((b.y1 << 16) | b.x1);
 549                OUT_BATCH((b.y2 << 16) | b.x2);
 550                OUT_RELOC(write_buffer,
 551                          I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 552                          irb_region->draw_offset);
 553                OUT_BATCH(clearVal);
 554                ADVANCE_BATCH();
 555                clearMask &= ~bufBit;    /* turn off bit, for faster loop exit */
 556             }
 557          }
 558       }
 559       intel_batchbuffer_emit_mi_flush(intel->batch);
 560    }
 561
 562    UNLOCK_HARDWARE(intel);
 563 }
 564
 565 void
 566 intelEmitImmediateColorExpandBlit(struct intel_context *intel,
 567                                   GLuint cpp,
 568                                   GLubyte *src_bits, GLuint src_size,
 569                                   GLuint fg_color,
 570                                   GLshort dst_pitch,
 571                                   dri_bo *dst_buffer,
 572                                   GLuint dst_offset,
 573                                   uint32_t dst_tiling,
 574                                   GLshort x, GLshort y,
 575                                   GLshort w, GLshort h,
 576                                   GLenum logic_op)
 577 {
 578    int dwords = ALIGN(src_size, 8) / 4;
 579    uint32_t opcode, br13, blit_cmd;
 580
 581    assert( logic_op - GL_CLEAR >= 0 );
 582    assert( logic_op - GL_CLEAR < 0x10 );
 583
 584    if (w < 0 || h < 0)
 585       return;
 586
 587    dst_pitch *= cpp;
 588
 589    DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
 590        __FUNCTION__,
 591        dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords);
 592
 593    intel_batchbuffer_require_space( intel->batch,
 594                                     (8 * 4) +
 595                                     (3 * 4) +
 596                                     dwords,
 597                                     REFERENCES_CLIPRECTS );
 598
 599    opcode = XY_SETUP_BLT_CMD;
 600    if (cpp == 4)
 601       opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 602 #ifndef I915
 603    if (dst_tiling != I915_TILING_NONE) {
 604       opcode |= XY_DST_TILED;
 605       dst_pitch /= 4;
 606    }
 607 #endif
 608
 609    br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29);
 610    if (cpp == 2)
 611       br13 |= BR13_565;
 612    else
 613       br13 |= BR13_8888;
 614
 615    blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */
 616    if (dst_tiling != I915_TILING_NONE)
 617       blit_cmd |= XY_DST_TILED;
 618
 619    BEGIN_BATCH(8 + 3, REFERENCES_CLIPRECTS);
 620    OUT_BATCH(opcode);
 621    OUT_BATCH(br13);
 622    OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
 623    OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
 624    OUT_RELOC(dst_buffer,
 625              I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 626              dst_offset);
 627    OUT_BATCH(0); /* bg */
 628    OUT_BATCH(fg_color); /* fg */
 629    OUT_BATCH(0); /* pattern base addr */
 630
 631    OUT_BATCH(blit_cmd | ((3 - 2) + dwords));
 632    OUT_BATCH((y << 16) | x);
 633    OUT_BATCH(((y + h) << 16) | (x + w));
 634    ADVANCE_BATCH();
 635
 636    intel_batchbuffer_data( intel->batch,
 637                            src_bits,
 638                            dwords * 4,
 639                            REFERENCES_CLIPRECTS );
 640
 641    intel_batchbuffer_emit_mi_flush(intel->batch);
 642 }