Merge commit 'origin/perrtblend'
[mesa.git] / src / mesa / drivers / dri / intel / intel_blit.c
1 /**************************************************************************
2 *
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28
29 #include "main/mtypes.h"
30 #include "main/context.h"
31 #include "main/enums.h"
32 #include "main/colormac.h"
33
34 #include "intel_blit.h"
35 #include "intel_buffers.h"
36 #include "intel_context.h"
37 #include "intel_fbo.h"
38 #include "intel_reg.h"
39 #include "intel_regions.h"
40 #include "intel_batchbuffer.h"
41
42 #define FILE_DEBUG_FLAG DEBUG_BLIT
43
44 static GLuint translate_raster_op(GLenum logicop)
45 {
46 switch(logicop) {
47 case GL_CLEAR: return 0x00;
48 case GL_AND: return 0x88;
49 case GL_AND_REVERSE: return 0x44;
50 case GL_COPY: return 0xCC;
51 case GL_AND_INVERTED: return 0x22;
52 case GL_NOOP: return 0xAA;
53 case GL_XOR: return 0x66;
54 case GL_OR: return 0xEE;
55 case GL_NOR: return 0x11;
56 case GL_EQUIV: return 0x99;
57 case GL_INVERT: return 0x55;
58 case GL_OR_REVERSE: return 0xDD;
59 case GL_COPY_INVERTED: return 0x33;
60 case GL_OR_INVERTED: return 0xBB;
61 case GL_NAND: return 0x77;
62 case GL_SET: return 0xFF;
63 default: return 0;
64 }
65 }
66
67
68 /* Copy BitBlt
69 */
70 GLboolean
71 intelEmitCopyBlit(struct intel_context *intel,
72 GLuint cpp,
73 GLshort src_pitch,
74 dri_bo *src_buffer,
75 GLuint src_offset,
76 uint32_t src_tiling,
77 GLshort dst_pitch,
78 dri_bo *dst_buffer,
79 GLuint dst_offset,
80 uint32_t dst_tiling,
81 GLshort src_x, GLshort src_y,
82 GLshort dst_x, GLshort dst_y,
83 GLshort w, GLshort h,
84 GLenum logic_op)
85 {
86 GLuint CMD, BR13, pass = 0;
87 int dst_y2 = dst_y + h;
88 int dst_x2 = dst_x + w;
89 dri_bo *aper_array[3];
90 BATCH_LOCALS;
91
92 if (dst_tiling != I915_TILING_NONE) {
93 if (dst_offset & 4095)
94 return GL_FALSE;
95 if (dst_tiling == I915_TILING_Y)
96 return GL_FALSE;
97 }
98 if (src_tiling != I915_TILING_NONE) {
99 if (src_offset & 4095)
100 return GL_FALSE;
101 if (src_tiling == I915_TILING_Y)
102 return GL_FALSE;
103 }
104
105 /* do space check before going any further */
106 do {
107 aper_array[0] = intel->batch->buf;
108 aper_array[1] = dst_buffer;
109 aper_array[2] = src_buffer;
110
111 if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
112 intel_batchbuffer_flush(intel->batch);
113 pass++;
114 } else
115 break;
116 } while (pass < 2);
117
118 if (pass >= 2) {
119 dri_bo_map(dst_buffer, GL_TRUE);
120 dri_bo_map(src_buffer, GL_FALSE);
121 _mesa_copy_rect((GLubyte *)dst_buffer->virtual + dst_offset,
122 cpp,
123 dst_pitch,
124 dst_x, dst_y,
125 w, h,
126 (GLubyte *)src_buffer->virtual + src_offset,
127 src_pitch,
128 src_x, src_y);
129
130 dri_bo_unmap(src_buffer);
131 dri_bo_unmap(dst_buffer);
132
133 return GL_TRUE;
134 }
135
136 intel_batchbuffer_require_space(intel->batch, 8 * 4);
137 DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
138 __FUNCTION__,
139 src_buffer, src_pitch, src_offset, src_x, src_y,
140 dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
141
142 src_pitch *= cpp;
143 dst_pitch *= cpp;
144
145 BR13 = translate_raster_op(logic_op) << 16;
146
147 switch (cpp) {
148 case 1:
149 CMD = XY_SRC_COPY_BLT_CMD;
150 break;
151 case 2:
152 BR13 |= BR13_565;
153 CMD = XY_SRC_COPY_BLT_CMD;
154 break;
155 case 4:
156 BR13 |= BR13_8888;
157 CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
158 break;
159 default:
160 return GL_FALSE;
161 }
162
163 #ifndef I915
164 if (dst_tiling != I915_TILING_NONE) {
165 CMD |= XY_DST_TILED;
166 dst_pitch /= 4;
167 }
168 if (src_tiling != I915_TILING_NONE) {
169 CMD |= XY_SRC_TILED;
170 src_pitch /= 4;
171 }
172 #endif
173
174 if (dst_y2 <= dst_y || dst_x2 <= dst_x) {
175 return GL_TRUE;
176 }
177
178 assert(dst_x < dst_x2);
179 assert(dst_y < dst_y2);
180
181 BEGIN_BATCH(8);
182 OUT_BATCH(CMD);
183 OUT_BATCH(BR13 | (uint16_t)dst_pitch);
184 OUT_BATCH((dst_y << 16) | dst_x);
185 OUT_BATCH((dst_y2 << 16) | dst_x2);
186 OUT_RELOC(dst_buffer,
187 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
188 dst_offset);
189 OUT_BATCH((src_y << 16) | src_x);
190 OUT_BATCH((uint16_t)src_pitch);
191 OUT_RELOC(src_buffer,
192 I915_GEM_DOMAIN_RENDER, 0,
193 src_offset);
194 ADVANCE_BATCH();
195
196 intel_batchbuffer_emit_mi_flush(intel->batch);
197
198 return GL_TRUE;
199 }
200
201
202 /**
203 * Use blitting to clear the renderbuffers named by 'flags'.
204 * Note: we can't use the ctx->DrawBuffer->_ColorDrawBufferIndexes field
205 * since that might include software renderbuffers or renderbuffers
206 * which we're clearing with triangles.
207 * \param mask bitmask of BUFFER_BIT_* values indicating buffers to clear
208 */
209 void
210 intelClearWithBlit(GLcontext *ctx, GLbitfield mask)
211 {
212 struct intel_context *intel = intel_context(ctx);
213 struct gl_framebuffer *fb = ctx->DrawBuffer;
214 GLuint clear_depth;
215 GLboolean all;
216 GLint cx, cy, cw, ch;
217 BATCH_LOCALS;
218
219 /*
220 * Compute values for clearing the buffers.
221 */
222 clear_depth = 0;
223 if (mask & BUFFER_BIT_DEPTH) {
224 clear_depth = (GLuint) (fb->_DepthMax * ctx->Depth.Clear);
225 }
226 if (mask & BUFFER_BIT_STENCIL) {
227 clear_depth |= (ctx->Stencil.Clear & 0xff) << 24;
228 }
229
230 cx = fb->_Xmin;
231 if (fb->Name == 0)
232 cy = fb->_Ymin;
233 else
234 cy = ctx->DrawBuffer->Height - fb->_Ymax;
235 cw = fb->_Xmax - fb->_Xmin;
236 ch = fb->_Ymax - fb->_Ymin;
237
238 if (cw == 0 || ch == 0)
239 return;
240
241 GLuint buf;
242 all = (cw == fb->Width && ch == fb->Height);
243
244 /* Loop over all renderbuffers */
245 for (buf = 0; buf < BUFFER_COUNT && mask; buf++) {
246 const GLbitfield bufBit = 1 << buf;
247 struct intel_renderbuffer *irb;
248 drm_intel_bo *write_buffer;
249 int x1, y1, x2, y2;
250 uint32_t clear_val;
251 uint32_t BR13, CMD;
252 int pitch, cpp;
253
254 if (!(mask & bufBit))
255 continue;
256
257 /* OK, clear this renderbuffer */
258 irb = intel_get_renderbuffer(fb, buf);
259 write_buffer = intel_region_buffer(intel, irb->region,
260 all ? INTEL_WRITE_FULL :
261 INTEL_WRITE_PART);
262 x1 = cx + irb->region->draw_x;
263 y1 = cy + irb->region->draw_y;
264 x2 = cx + cw + irb->region->draw_x;
265 y2 = cy + ch + irb->region->draw_y;
266
267 pitch = irb->region->pitch;
268 cpp = irb->region->cpp;
269
270 DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
271 __FUNCTION__,
272 irb->region->buffer, (pitch * cpp),
273 x1, y1, x2 - x1, y2 - y1);
274
275 BR13 = 0xf0 << 16;
276 CMD = XY_COLOR_BLT_CMD;
277
278 /* Setup the blit command */
279 if (cpp == 4) {
280 BR13 |= BR13_8888;
281 if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) {
282 if (mask & BUFFER_BIT_DEPTH)
283 CMD |= XY_BLT_WRITE_RGB;
284 if (mask & BUFFER_BIT_STENCIL)
285 CMD |= XY_BLT_WRITE_ALPHA;
286 } else {
287 /* clearing RGBA */
288 CMD |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
289 }
290 } else {
291 ASSERT(cpp == 2);
292 BR13 |= BR13_565;
293 }
294
295 assert(irb->region->tiling != I915_TILING_Y);
296
297 #ifndef I915
298 if (irb->region->tiling != I915_TILING_NONE) {
299 CMD |= XY_DST_TILED;
300 pitch /= 4;
301 }
302 #endif
303 BR13 |= (pitch * cpp);
304
305 if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) {
306 clear_val = clear_depth;
307 } else {
308 uint8_t clear[4];
309 GLclampf *color = ctx->Color.ClearColor;
310
311 CLAMPED_FLOAT_TO_UBYTE(clear[0], color[0]);
312 CLAMPED_FLOAT_TO_UBYTE(clear[1], color[1]);
313 CLAMPED_FLOAT_TO_UBYTE(clear[2], color[2]);
314 CLAMPED_FLOAT_TO_UBYTE(clear[3], color[3]);
315
316 switch (irb->Base.Format) {
317 case MESA_FORMAT_ARGB8888:
318 case MESA_FORMAT_XRGB8888:
319 clear_val = PACK_COLOR_8888(clear[3], clear[0],
320 clear[1], clear[2]);
321 break;
322 case MESA_FORMAT_RGB565:
323 clear_val = PACK_COLOR_565(clear[0], clear[1], clear[2]);
324 break;
325 case MESA_FORMAT_ARGB4444:
326 clear_val = PACK_COLOR_4444(clear[3], clear[0],
327 clear[1], clear[2]);
328 break;
329 case MESA_FORMAT_ARGB1555:
330 clear_val = PACK_COLOR_1555(clear[3], clear[0],
331 clear[1], clear[2]);
332 break;
333 default:
334 _mesa_problem(ctx, "Unexpected renderbuffer format: %d\n",
335 irb->Base.Format);
336 clear_val = 0;
337 }
338 }
339
340 assert(x1 < x2);
341 assert(y1 < y2);
342
343 BEGIN_BATCH(6);
344 OUT_BATCH(CMD);
345 OUT_BATCH(BR13);
346 OUT_BATCH((y1 << 16) | x1);
347 OUT_BATCH((y2 << 16) | x2);
348 OUT_RELOC(write_buffer,
349 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
350 0);
351 OUT_BATCH(clear_val);
352 ADVANCE_BATCH();
353
354 if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL)
355 mask &= ~(BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL);
356 else
357 mask &= ~bufBit; /* turn off bit, for faster loop exit */
358 }
359 }
360
361 GLboolean
362 intelEmitImmediateColorExpandBlit(struct intel_context *intel,
363 GLuint cpp,
364 GLubyte *src_bits, GLuint src_size,
365 GLuint fg_color,
366 GLshort dst_pitch,
367 dri_bo *dst_buffer,
368 GLuint dst_offset,
369 uint32_t dst_tiling,
370 GLshort x, GLshort y,
371 GLshort w, GLshort h,
372 GLenum logic_op)
373 {
374 int dwords = ALIGN(src_size, 8) / 4;
375 uint32_t opcode, br13, blit_cmd;
376
377 if (dst_tiling != I915_TILING_NONE) {
378 if (dst_offset & 4095)
379 return GL_FALSE;
380 if (dst_tiling == I915_TILING_Y)
381 return GL_FALSE;
382 }
383
384 assert( logic_op - GL_CLEAR >= 0 );
385 assert( logic_op - GL_CLEAR < 0x10 );
386 assert(dst_pitch > 0);
387
388 if (w < 0 || h < 0)
389 return GL_TRUE;
390
391 dst_pitch *= cpp;
392
393 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
394 __FUNCTION__,
395 dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords);
396
397 intel_batchbuffer_require_space( intel->batch,
398 (8 * 4) +
399 (3 * 4) +
400 dwords * 4 );
401
402 opcode = XY_SETUP_BLT_CMD;
403 if (cpp == 4)
404 opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
405 #ifndef I915
406 if (dst_tiling != I915_TILING_NONE) {
407 opcode |= XY_DST_TILED;
408 dst_pitch /= 4;
409 }
410 #endif
411
412 br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29);
413 if (cpp == 2)
414 br13 |= BR13_565;
415 else
416 br13 |= BR13_8888;
417
418 blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */
419 if (dst_tiling != I915_TILING_NONE)
420 blit_cmd |= XY_DST_TILED;
421
422 BEGIN_BATCH(8 + 3);
423 OUT_BATCH(opcode);
424 OUT_BATCH(br13);
425 OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
426 OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
427 OUT_RELOC(dst_buffer,
428 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
429 dst_offset);
430 OUT_BATCH(0); /* bg */
431 OUT_BATCH(fg_color); /* fg */
432 OUT_BATCH(0); /* pattern base addr */
433
434 OUT_BATCH(blit_cmd | ((3 - 2) + dwords));
435 OUT_BATCH((y << 16) | x);
436 OUT_BATCH(((y + h) << 16) | (x + w));
437 ADVANCE_BATCH();
438
439 intel_batchbuffer_data( intel->batch,
440 src_bits,
441 dwords * 4 );
442
443 intel_batchbuffer_emit_mi_flush(intel->batch);
444
445 return GL_TRUE;
446 }
447
448 /* We don't have a memmove-type blit like some other hardware, so we'll do a
449 * rectangular blit covering a large space, then emit 1-scanline blit at the
450 * end to cover the last if we need.
451 */
452 void
453 intel_emit_linear_blit(struct intel_context *intel,
454 drm_intel_bo *dst_bo,
455 unsigned int dst_offset,
456 drm_intel_bo *src_bo,
457 unsigned int src_offset,
458 unsigned int size)
459 {
460 GLuint pitch, height;
461
462 /* The pitch is a signed value. */
463 pitch = MIN2(size, (1 << 15) - 1);
464 height = size / pitch;
465 intelEmitCopyBlit(intel, 1,
466 pitch, src_bo, src_offset, I915_TILING_NONE,
467 pitch, dst_bo, dst_offset, I915_TILING_NONE,
468 0, 0, /* src x/y */
469 0, 0, /* dst x/y */
470 pitch, height, /* w, h */
471 GL_COPY);
472
473 src_offset += pitch * height;
474 dst_offset += pitch * height;
475 size -= pitch * height;
476 assert (size < (1 << 15));
477 if (size != 0) {
478 intelEmitCopyBlit(intel, 1,
479 size, src_bo, src_offset, I915_TILING_NONE,
480 size, dst_bo, dst_offset, I915_TILING_NONE,
481 0, 0, /* src x/y */
482 0, 0, /* dst x/y */
483 size, 1, /* w, h */
484 GL_COPY);
485 }
486 }