src/mesa/drivers/dri/intel/intel_blit.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29 #include "main/mtypes.h"
  30 #include "main/context.h"
  31 #include "main/enums.h"
  32 #include "main/colormac.h"
  33
  34 #include "intel_blit.h"
  35 #include "intel_buffers.h"
  36 #include "intel_context.h"
  37 #include "intel_fbo.h"
  38 #include "intel_reg.h"
  39 #include "intel_regions.h"
  40 #include "intel_batchbuffer.h"
  41
  42 #define FILE_DEBUG_FLAG DEBUG_BLIT
  43
  44 static GLuint translate_raster_op(GLenum logicop)
  45 {
  46    switch(logicop) {
  47    case GL_CLEAR: return 0x00;
  48    case GL_AND: return 0x88;
  49    case GL_AND_REVERSE: return 0x44;
  50    case GL_COPY: return 0xCC;
  51    case GL_AND_INVERTED: return 0x22;
  52    case GL_NOOP: return 0xAA;
  53    case GL_XOR: return 0x66;
  54    case GL_OR: return 0xEE;
  55    case GL_NOR: return 0x11;
  56    case GL_EQUIV: return 0x99;
  57    case GL_INVERT: return 0x55;
  58    case GL_OR_REVERSE: return 0xDD;
  59    case GL_COPY_INVERTED: return 0x33;
  60    case GL_OR_INVERTED: return 0xBB;
  61    case GL_NAND: return 0x77;
  62    case GL_SET: return 0xFF;
  63    default: return 0;
  64    }
  65 }
  66
  67 static uint32_t
  68 br13_for_cpp(int cpp)
  69 {
  70    switch (cpp) {
  71    case 4:
  72       return BR13_8888;
  73       break;
  74    case 2:
  75       return BR13_565;
  76       break;
  77    case 1:
  78       return BR13_8;
  79       break;
  80    default:
  81       assert(0);
  82       return 0;
  83    }
  84 }
  85
  86 /* Copy BitBlt
  87  */
  88 GLboolean
  89 intelEmitCopyBlit(struct intel_context *intel,
  90                   GLuint cpp,
  91                   GLshort src_pitch,
  92                   drm_intel_bo *src_buffer,
  93                   GLuint src_offset,
  94                   uint32_t src_tiling,
  95                   GLshort dst_pitch,
  96                   drm_intel_bo *dst_buffer,
  97                   GLuint dst_offset,
  98                   uint32_t dst_tiling,
  99                   GLshort src_x, GLshort src_y,
 100                   GLshort dst_x, GLshort dst_y,
 101                   GLshort w, GLshort h,
 102                   GLenum logic_op)
 103 {
 104    GLuint CMD, BR13, pass = 0;
 105    int dst_y2 = dst_y + h;
 106    int dst_x2 = dst_x + w;
 107    drm_intel_bo *aper_array[3];
 108    BATCH_LOCALS;
 109
 110    if (dst_tiling != I915_TILING_NONE) {
 111       if (dst_offset & 4095)
 112          return GL_FALSE;
 113       if (dst_tiling == I915_TILING_Y)
 114          return GL_FALSE;
 115    }
 116    if (src_tiling != I915_TILING_NONE) {
 117       if (src_offset & 4095)
 118          return GL_FALSE;
 119       if (src_tiling == I915_TILING_Y)
 120          return GL_FALSE;
 121    }
 122
 123    /* do space check before going any further */
 124    do {
 125        aper_array[0] = intel->batch->buf;
 126        aper_array[1] = dst_buffer;
 127        aper_array[2] = src_buffer;
 128
 129        if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
 130            intel_batchbuffer_flush(intel->batch);
 131            pass++;
 132        } else
 133            break;
 134    } while (pass < 2);
 135
 136    if (pass >= 2)
 137       return GL_FALSE;
 138
 139    intel_batchbuffer_require_space(intel->batch, 8 * 4, true);
 140    DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
 141        __FUNCTION__,
 142        src_buffer, src_pitch, src_offset, src_x, src_y,
 143        dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
 144
 145    src_pitch *= cpp;
 146    dst_pitch *= cpp;
 147
 148    BR13 = br13_for_cpp(cpp) | translate_raster_op(logic_op) << 16;
 149
 150    switch (cpp) {
 151    case 1:
 152    case 2:
 153       CMD = XY_SRC_COPY_BLT_CMD;
 154       break;
 155    case 4:
 156       CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 157       break;
 158    default:
 159       return GL_FALSE;
 160    }
 161
 162 #ifndef I915
 163    if (dst_tiling != I915_TILING_NONE) {
 164       CMD |= XY_DST_TILED;
 165       dst_pitch /= 4;
 166    }
 167    if (src_tiling != I915_TILING_NONE) {
 168       CMD |= XY_SRC_TILED;
 169       src_pitch /= 4;
 170    }
 171 #endif
 172
 173    if (dst_y2 <= dst_y || dst_x2 <= dst_x) {
 174       return GL_TRUE;
 175    }
 176
 177    assert(dst_x < dst_x2);
 178    assert(dst_y < dst_y2);
 179
 180    BEGIN_BATCH_BLT(8);
 181    OUT_BATCH(CMD);
 182    OUT_BATCH(BR13 | (uint16_t)dst_pitch);
 183    OUT_BATCH((dst_y << 16) | dst_x);
 184    OUT_BATCH((dst_y2 << 16) | dst_x2);
 185    OUT_RELOC_FENCED(dst_buffer,
 186                     I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 187                     dst_offset);
 188    OUT_BATCH((src_y << 16) | src_x);
 189    OUT_BATCH((uint16_t)src_pitch);
 190    OUT_RELOC_FENCED(src_buffer,
 191                     I915_GEM_DOMAIN_RENDER, 0,
 192                     src_offset);
 193    ADVANCE_BATCH();
 194
 195    intel_batchbuffer_emit_mi_flush(intel->batch);
 196
 197    return GL_TRUE;
 198 }
 199
 200
 201 /**
 202  * Use blitting to clear the renderbuffers named by 'flags'.
 203  * Note: we can't use the ctx->DrawBuffer->_ColorDrawBufferIndexes field
 204  * since that might include software renderbuffers or renderbuffers
 205  * which we're clearing with triangles.
 206  * \param mask  bitmask of BUFFER_BIT_* values indicating buffers to clear
 207  */
 208 void
 209 intelClearWithBlit(struct gl_context *ctx, GLbitfield mask)
 210 {
 211    struct intel_context *intel = intel_context(ctx);
 212    struct gl_framebuffer *fb = ctx->DrawBuffer;
 213    GLuint clear_depth;
 214    GLboolean all;
 215    GLint cx, cy, cw, ch;
 216    BATCH_LOCALS;
 217
 218    /*
 219     * Compute values for clearing the buffers.
 220     */
 221    clear_depth = 0;
 222    if (mask & BUFFER_BIT_DEPTH) {
 223       clear_depth = (GLuint) (fb->_DepthMax * ctx->Depth.Clear);
 224    }
 225    if (mask & BUFFER_BIT_STENCIL) {
 226       clear_depth |= (ctx->Stencil.Clear & 0xff) << 24;
 227    }
 228
 229    cx = fb->_Xmin;
 230    if (fb->Name == 0)
 231       cy = ctx->DrawBuffer->Height - fb->_Ymax;
 232    else
 233       cy = fb->_Ymin;
 234    cw = fb->_Xmax - fb->_Xmin;
 235    ch = fb->_Ymax - fb->_Ymin;
 236
 237    if (cw == 0 || ch == 0)
 238       return;
 239
 240    GLuint buf;
 241    all = (cw == fb->Width && ch == fb->Height);
 242
 243    /* Loop over all renderbuffers */
 244    for (buf = 0; buf < BUFFER_COUNT && mask; buf++) {
 245       const GLbitfield bufBit = 1 << buf;
 246       struct intel_renderbuffer *irb;
 247       drm_intel_bo *write_buffer;
 248       int x1, y1, x2, y2;
 249       uint32_t clear_val;
 250       uint32_t BR13, CMD;
 251       int pitch, cpp;
 252       drm_intel_bo *aper_array[2];
 253
 254       if (!(mask & bufBit))
 255          continue;
 256
 257       /* OK, clear this renderbuffer */
 258       irb = intel_get_renderbuffer(fb, buf);
 259       write_buffer = intel_region_buffer(intel, irb->region,
 260                                          all ? INTEL_WRITE_FULL :
 261                                          INTEL_WRITE_PART);
 262       x1 = cx + irb->region->draw_x;
 263       y1 = cy + irb->region->draw_y;
 264       x2 = cx + cw + irb->region->draw_x;
 265       y2 = cy + ch + irb->region->draw_y;
 266
 267       pitch = irb->region->pitch;
 268       cpp = irb->region->cpp;
 269
 270       DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
 271           __FUNCTION__,
 272           irb->region->buffer, (pitch * cpp),
 273           x1, y1, x2 - x1, y2 - y1);
 274
 275       BR13 = br13_for_cpp(cpp) | 0xf0 << 16;
 276       CMD = XY_COLOR_BLT_CMD;
 277
 278       /* Setup the blit command */
 279       if (cpp == 4) {
 280          if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) {
 281             if (mask & BUFFER_BIT_DEPTH)
 282                CMD |= XY_BLT_WRITE_RGB;
 283             if (mask & BUFFER_BIT_STENCIL)
 284                CMD |= XY_BLT_WRITE_ALPHA;
 285          } else {
 286             /* clearing RGBA */
 287             CMD |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 288          }
 289       }
 290
 291       assert(irb->region->tiling != I915_TILING_Y);
 292
 293 #ifndef I915
 294       if (irb->region->tiling != I915_TILING_NONE) {
 295          CMD |= XY_DST_TILED;
 296          pitch /= 4;
 297       }
 298 #endif
 299       BR13 |= (pitch * cpp);
 300
 301       if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) {
 302          clear_val = clear_depth;
 303       } else {
 304          uint8_t clear[4];
 305          GLclampf *color = ctx->Color.ClearColor;
 306
 307          CLAMPED_FLOAT_TO_UBYTE(clear[0], color[0]);
 308          CLAMPED_FLOAT_TO_UBYTE(clear[1], color[1]);
 309          CLAMPED_FLOAT_TO_UBYTE(clear[2], color[2]);
 310          CLAMPED_FLOAT_TO_UBYTE(clear[3], color[3]);
 311
 312          switch (irb->Base.Format) {
 313          case MESA_FORMAT_ARGB8888:
 314          case MESA_FORMAT_XRGB8888:
 315             clear_val = PACK_COLOR_8888(clear[3], clear[0],
 316                                         clear[1], clear[2]);
 317             break;
 318          case MESA_FORMAT_RGB565:
 319             clear_val = PACK_COLOR_565(clear[0], clear[1], clear[2]);
 320             break;
 321          case MESA_FORMAT_ARGB4444:
 322             clear_val = PACK_COLOR_4444(clear[3], clear[0],
 323                                         clear[1], clear[2]);
 324             break;
 325          case MESA_FORMAT_ARGB1555:
 326             clear_val = PACK_COLOR_1555(clear[3], clear[0],
 327                                         clear[1], clear[2]);
 328             break;
 329          case MESA_FORMAT_A8:
 330             clear_val = PACK_COLOR_8888(clear[3], clear[3],
 331                                         clear[3], clear[3]);
 332             break;
 333          default:
 334             _mesa_problem(ctx, "Unexpected renderbuffer format: %d\n",
 335                           irb->Base.Format);
 336             clear_val = 0;
 337          }
 338       }
 339
 340       assert(x1 < x2);
 341       assert(y1 < y2);
 342
 343       /* do space check before going any further */
 344       aper_array[0] = intel->batch->buf;
 345       aper_array[1] = write_buffer;
 346
 347       if (drm_intel_bufmgr_check_aperture_space(aper_array,
 348                                                 ARRAY_SIZE(aper_array)) != 0) {
 349          intel_batchbuffer_flush(intel->batch);
 350       }
 351
 352       BEGIN_BATCH_BLT(6);
 353       OUT_BATCH(CMD);
 354       OUT_BATCH(BR13);
 355       OUT_BATCH((y1 << 16) | x1);
 356       OUT_BATCH((y2 << 16) | x2);
 357       OUT_RELOC_FENCED(write_buffer,
 358                        I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 359                        0);
 360       OUT_BATCH(clear_val);
 361       ADVANCE_BATCH();
 362
 363       if (intel->always_flush_cache)
 364          intel_batchbuffer_emit_mi_flush(intel->batch);
 365
 366       if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL)
 367          mask &= ~(BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL);
 368       else
 369          mask &= ~bufBit;    /* turn off bit, for faster loop exit */
 370    }
 371 }
 372
 373 GLboolean
 374 intelEmitImmediateColorExpandBlit(struct intel_context *intel,
 375                                   GLuint cpp,
 376                                   GLubyte *src_bits, GLuint src_size,
 377                                   GLuint fg_color,
 378                                   GLshort dst_pitch,
 379                                   drm_intel_bo *dst_buffer,
 380                                   GLuint dst_offset,
 381                                   uint32_t dst_tiling,
 382                                   GLshort x, GLshort y,
 383                                   GLshort w, GLshort h,
 384                                   GLenum logic_op)
 385 {
 386    int dwords = ALIGN(src_size, 8) / 4;
 387    uint32_t opcode, br13, blit_cmd;
 388
 389    if (dst_tiling != I915_TILING_NONE) {
 390       if (dst_offset & 4095)
 391          return GL_FALSE;
 392       if (dst_tiling == I915_TILING_Y)
 393          return GL_FALSE;
 394    }
 395
 396    assert( logic_op - GL_CLEAR >= 0 );
 397    assert( logic_op - GL_CLEAR < 0x10 );
 398    assert(dst_pitch > 0);
 399
 400    if (w < 0 || h < 0)
 401       return GL_TRUE;
 402
 403    dst_pitch *= cpp;
 404
 405    DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
 406        __FUNCTION__,
 407        dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords);
 408
 409    intel_batchbuffer_require_space( intel->batch,
 410                                     (8 * 4) +
 411                                     (3 * 4) +
 412                                     dwords * 4, true);
 413
 414    opcode = XY_SETUP_BLT_CMD;
 415    if (cpp == 4)
 416       opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 417 #ifndef I915
 418    if (dst_tiling != I915_TILING_NONE) {
 419       opcode |= XY_DST_TILED;
 420       dst_pitch /= 4;
 421    }
 422 #endif
 423
 424    br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29);
 425    br13 |= br13_for_cpp(cpp);
 426
 427    blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */
 428    if (dst_tiling != I915_TILING_NONE)
 429       blit_cmd |= XY_DST_TILED;
 430
 431    BEGIN_BATCH_BLT(8 + 3);
 432    OUT_BATCH(opcode);
 433    OUT_BATCH(br13);
 434    OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
 435    OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
 436    OUT_RELOC_FENCED(dst_buffer,
 437                     I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 438                     dst_offset);
 439    OUT_BATCH(0); /* bg */
 440    OUT_BATCH(fg_color); /* fg */
 441    OUT_BATCH(0); /* pattern base addr */
 442
 443    OUT_BATCH(blit_cmd | ((3 - 2) + dwords));
 444    OUT_BATCH((y << 16) | x);
 445    OUT_BATCH(((y + h) << 16) | (x + w));
 446    ADVANCE_BATCH();
 447
 448    intel_batchbuffer_data(intel->batch,
 449                           src_bits,
 450                           dwords * 4, true);
 451
 452    intel_batchbuffer_emit_mi_flush(intel->batch);
 453
 454    return GL_TRUE;
 455 }
 456
 457 /* We don't have a memmove-type blit like some other hardware, so we'll do a
 458  * rectangular blit covering a large space, then emit 1-scanline blit at the
 459  * end to cover the last if we need.
 460  */
 461 void
 462 intel_emit_linear_blit(struct intel_context *intel,
 463                        drm_intel_bo *dst_bo,
 464                        unsigned int dst_offset,
 465                        drm_intel_bo *src_bo,
 466                        unsigned int src_offset,
 467                        unsigned int size)
 468 {
 469    GLuint pitch, height;
 470    GLboolean ok;
 471
 472    /* The pitch given to the GPU must be DWORD aligned, and
 473     * we want width to match pitch. Max width is (1 << 15 - 1),
 474     * rounding that down to the nearest DWORD is 1 << 15 - 4
 475     */
 476    pitch = MIN2(size, (1 << 15) - 4);
 477    height = size / pitch;
 478    ok = intelEmitCopyBlit(intel, 1,
 479                           pitch, src_bo, src_offset, I915_TILING_NONE,
 480                           pitch, dst_bo, dst_offset, I915_TILING_NONE,
 481                           0, 0, /* src x/y */
 482                           0, 0, /* dst x/y */
 483                           pitch, height, /* w, h */
 484                           GL_COPY);
 485    assert(ok);
 486
 487    src_offset += pitch * height;
 488    dst_offset += pitch * height;
 489    size -= pitch * height;
 490    assert (size < (1 << 15));
 491    assert ((size & 3) == 0); /* Pitch must be DWORD aligned */
 492    if (size != 0) {
 493       ok = intelEmitCopyBlit(intel, 1,
 494                              size, src_bo, src_offset, I915_TILING_NONE,
 495                              size, dst_bo, dst_offset, I915_TILING_NONE,
 496                              0, 0, /* src x/y */
 497                              0, 0, /* dst x/y */
 498                              size, 1, /* w, h */
 499                              GL_COPY);
 500       assert(ok);
 501    }
 502 }