src/mesa/drivers/dri/intel/intel_chipset.h

   1  /*
   2  * Copyright © 2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #define PCI_CHIP_I810                   0x7121
  29 #define PCI_CHIP_I810_DC100             0x7123
  30 #define PCI_CHIP_I810_E                 0x7125
  31 #define PCI_CHIP_I815                   0x1132
  32
  33 #define PCI_CHIP_I830_M                 0x3577
  34 #define PCI_CHIP_845_G                  0x2562
  35 #define PCI_CHIP_I855_GM                0x3582
  36 #define PCI_CHIP_I865_G                 0x2572
  37
  38 #define PCI_CHIP_I915_G                 0x2582
  39 #define PCI_CHIP_E7221_G                0x258A
  40 #define PCI_CHIP_I915_GM                0x2592
  41 #define PCI_CHIP_I945_G                 0x2772
  42 #define PCI_CHIP_I945_GM                0x27A2
  43 #define PCI_CHIP_I945_GME               0x27AE
  44
  45 #define PCI_CHIP_Q35_G                  0x29B2
  46 #define PCI_CHIP_G33_G                  0x29C2
  47 #define PCI_CHIP_Q33_G                  0x29D2
  48
  49 #define PCI_CHIP_IGD_GM                 0xA011
  50 #define PCI_CHIP_IGD_G                  0xA001
  51
  52 #define IS_IGDGM(devid) (devid == PCI_CHIP_IGD_GM)
  53 #define IS_IGDG(devid)  (devid == PCI_CHIP_IGD_G)
  54 #define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid))
  55
  56 #define PCI_CHIP_I965_G                 0x29A2
  57 #define PCI_CHIP_I965_Q                 0x2992
  58 #define PCI_CHIP_I965_G_1               0x2982
  59 #define PCI_CHIP_I946_GZ                0x2972
  60 #define PCI_CHIP_I965_GM                0x2A02
  61 #define PCI_CHIP_I965_GME               0x2A12
  62
  63 #define PCI_CHIP_GM45_GM                0x2A42
  64
  65 #define PCI_CHIP_IGD_E_G                0x2E02
  66 #define PCI_CHIP_Q45_G                  0x2E12
  67 #define PCI_CHIP_G45_G                  0x2E22
  68 #define PCI_CHIP_G41_G                  0x2E32
  69 #define PCI_CHIP_B43_G                  0x2E42
  70
  71 #define PCI_CHIP_ILD_G                  0x0042
  72 #define PCI_CHIP_ILM_G                  0x0046
  73
  74 #define PCI_CHIP_SANDYBRIDGE_GT1        0x0102  /* Desktop */
  75 #define PCI_CHIP_SANDYBRIDGE_GT2        0x0112
  76 #define PCI_CHIP_SANDYBRIDGE_GT2_PLUS   0x0122
  77 #define PCI_CHIP_SANDYBRIDGE_M_GT1      0x0106  /* Mobile */
  78 #define PCI_CHIP_SANDYBRIDGE_M_GT2      0x0116
  79 #define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126
  80 #define PCI_CHIP_SANDYBRIDGE_S          0x010A  /* Server */
  81
  82 #define IS_MOBILE(devid)        (devid == PCI_CHIP_I855_GM || \
  83                                  devid == PCI_CHIP_I915_GM || \
  84                                  devid == PCI_CHIP_I945_GM || \
  85                                  devid == PCI_CHIP_I945_GME || \
  86                                  devid == PCI_CHIP_I965_GM || \
  87                                  devid == PCI_CHIP_I965_GME || \
  88                                  devid == PCI_CHIP_GM45_GM || \
  89                                  IS_IGD(devid) || \
  90                                  devid == PCI_CHIP_ILM_G)
  91
  92 #define IS_G45(devid)           (devid == PCI_CHIP_IGD_E_G || \
  93                                  devid == PCI_CHIP_Q45_G || \
  94                                  devid == PCI_CHIP_G45_G || \
  95                                  devid == PCI_CHIP_G41_G || \
  96                                  devid == PCI_CHIP_B43_G)
  97 #define IS_GM45(devid)          (devid == PCI_CHIP_GM45_GM)
  98 #define IS_G4X(devid)           (IS_G45(devid) || IS_GM45(devid))
  99
 100 #define IS_ILD(devid)           (devid == PCI_CHIP_ILD_G)
 101 #define IS_ILM(devid)           (devid == PCI_CHIP_ILM_G)
 102 #define IS_GEN5(devid)          (IS_ILD(devid) || IS_ILM(devid))
 103
 104 #define IS_915(devid)           (devid == PCI_CHIP_I915_G || \
 105                                  devid == PCI_CHIP_E7221_G || \
 106                                  devid == PCI_CHIP_I915_GM)
 107
 108 #define IS_945(devid)           (devid == PCI_CHIP_I945_G || \
 109                                  devid == PCI_CHIP_I945_GM || \
 110                                  devid == PCI_CHIP_I945_GME || \
 111                                  devid == PCI_CHIP_G33_G || \
 112                                  devid == PCI_CHIP_Q33_G || \
 113                                  devid == PCI_CHIP_Q35_G || IS_IGD(devid))
 114
 115 #define IS_GEN4(devid)          (devid == PCI_CHIP_I965_G || \
 116                                  devid == PCI_CHIP_I965_Q || \
 117                                  devid == PCI_CHIP_I965_G_1 || \
 118                                  devid == PCI_CHIP_I965_GM || \
 119                                  devid == PCI_CHIP_I965_GME || \
 120                                  devid == PCI_CHIP_I946_GZ || \
 121                                  IS_G4X(devid))
 122
 123 /* Compat macro for intel_decode.c */
 124 #define IS_IRONLAKE(devid)      IS_GEN5(devid)
 125
 126 #define IS_GEN6(devid)          (devid == PCI_CHIP_SANDYBRIDGE_GT1 || \
 127                                  devid == PCI_CHIP_SANDYBRIDGE_GT2 || \
 128                                  devid == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
 129                                  devid == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
 130                                  devid == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
 131                                  devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
 132                                  devid == PCI_CHIP_SANDYBRIDGE_S)
 133
 134 #define IS_965(devid)           (IS_GEN4(devid) || \
 135                                  IS_G4X(devid) || \
 136                                  IS_GEN5(devid) || \
 137                                  IS_GEN6(devid))
 138
 139 #define IS_9XX(devid)           (IS_915(devid) || \
 140                                  IS_945(devid) || \
 141                                  IS_965(devid))