2 * Copyright © 2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
28 #define PCI_CHIP_I810 0x7121
29 #define PCI_CHIP_I810_DC100 0x7123
30 #define PCI_CHIP_I810_E 0x7125
31 #define PCI_CHIP_I815 0x1132
33 #define PCI_CHIP_I830_M 0x3577
34 #define PCI_CHIP_845_G 0x2562
35 #define PCI_CHIP_I855_GM 0x3582
36 #define PCI_CHIP_I865_G 0x2572
38 #define PCI_CHIP_I915_G 0x2582
39 #define PCI_CHIP_E7221_G 0x258A
40 #define PCI_CHIP_I915_GM 0x2592
41 #define PCI_CHIP_I945_G 0x2772
42 #define PCI_CHIP_I945_GM 0x27A2
43 #define PCI_CHIP_I945_GME 0x27AE
45 #define PCI_CHIP_Q35_G 0x29B2
46 #define PCI_CHIP_G33_G 0x29C2
47 #define PCI_CHIP_Q33_G 0x29D2
49 #define PCI_CHIP_IGD_GM 0xA011
50 #define PCI_CHIP_IGD_G 0xA001
52 #define IS_IGDGM(devid) (devid == PCI_CHIP_IGD_GM)
53 #define IS_IGDG(devid) (devid == PCI_CHIP_IGD_G)
54 #define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid))
56 #define PCI_CHIP_I965_G 0x29A2
57 #define PCI_CHIP_I965_Q 0x2992
58 #define PCI_CHIP_I965_G_1 0x2982
59 #define PCI_CHIP_I946_GZ 0x2972
60 #define PCI_CHIP_I965_GM 0x2A02
61 #define PCI_CHIP_I965_GME 0x2A12
63 #define PCI_CHIP_GM45_GM 0x2A42
65 #define PCI_CHIP_IGD_E_G 0x2E02
66 #define PCI_CHIP_Q45_G 0x2E12
67 #define PCI_CHIP_G45_G 0x2E22
68 #define PCI_CHIP_G41_G 0x2E32
69 #define PCI_CHIP_B43_G 0x2E42
71 #define PCI_CHIP_ILD_G 0x0042
72 #define PCI_CHIP_ILM_G 0x0046
74 #define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \
75 devid == PCI_CHIP_I915_GM || \
76 devid == PCI_CHIP_I945_GM || \
77 devid == PCI_CHIP_I945_GME || \
78 devid == PCI_CHIP_I965_GM || \
79 devid == PCI_CHIP_I965_GME || \
80 devid == PCI_CHIP_GM45_GM || \
82 devid == PCI_CHIP_ILM_G)
84 #define IS_G45(devid) (devid == PCI_CHIP_IGD_E_G || \
85 devid == PCI_CHIP_Q45_G || \
86 devid == PCI_CHIP_G45_G || \
87 devid == PCI_CHIP_G41_G || \
88 devid == PCI_CHIP_B43_G)
89 #define IS_GM45(devid) (devid == PCI_CHIP_GM45_GM)
90 #define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid))
92 #define IS_ILD(devid) (devid == PCI_CHIP_ILD_G)
93 #define IS_ILM(devid) (devid == PCI_CHIP_ILM_G)
94 #define IS_IGDNG(devid) (IS_ILD(devid) || IS_ILM(devid))
96 #define IS_915(devid) (devid == PCI_CHIP_I915_G || \
97 devid == PCI_CHIP_E7221_G || \
98 devid == PCI_CHIP_I915_GM)
100 #define IS_945(devid) (devid == PCI_CHIP_I945_G || \
101 devid == PCI_CHIP_I945_GM || \
102 devid == PCI_CHIP_I945_GME || \
103 devid == PCI_CHIP_G33_G || \
104 devid == PCI_CHIP_Q33_G || \
105 devid == PCI_CHIP_Q35_G || IS_IGD(devid))
107 #define IS_965(devid) (devid == PCI_CHIP_I965_G || \
108 devid == PCI_CHIP_I965_Q || \
109 devid == PCI_CHIP_I965_G_1 || \
110 devid == PCI_CHIP_I965_GM || \
111 devid == PCI_CHIP_I965_GME || \
112 devid == PCI_CHIP_I946_GZ || \
116 #define IS_9XX(devid) (IS_915(devid) || \