src/mesa/drivers/dri/intel/intel_clear.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * Copyright 2009 Intel Corporation.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  **************************************************************************/
  28
  29 #include "main/glheader.h"
  30 #include "main/mtypes.h"
  31 #include "swrast/swrast.h"
  32 #include "drivers/common/meta.h"
  33
  34 #include "intel_context.h"
  35 #include "intel_blit.h"
  36 #include "intel_chipset.h"
  37 #include "intel_clear.h"
  38 #include "intel_fbo.h"
  39 #include "intel_pixel.h"
  40 #include "intel_regions.h"
  41 #include "intel_batchbuffer.h"
  42
  43 #define FILE_DEBUG_FLAG DEBUG_BLIT
  44
  45 static const char *buffer_names[] = {
  46    [BUFFER_FRONT_LEFT] = "front",
  47    [BUFFER_BACK_LEFT] = "back",
  48    [BUFFER_FRONT_RIGHT] = "front right",
  49    [BUFFER_BACK_RIGHT] = "back right",
  50    [BUFFER_DEPTH] = "depth",
  51    [BUFFER_STENCIL] = "stencil",
  52    [BUFFER_ACCUM] = "accum",
  53    [BUFFER_AUX0] = "aux0",
  54    [BUFFER_COLOR0] = "color0",
  55    [BUFFER_COLOR1] = "color1",
  56    [BUFFER_COLOR2] = "color2",
  57    [BUFFER_COLOR3] = "color3",
  58    [BUFFER_COLOR4] = "color4",
  59    [BUFFER_COLOR5] = "color5",
  60    [BUFFER_COLOR6] = "color6",
  61    [BUFFER_COLOR7] = "color7",
  62 };
  63
  64 /**
  65  * Called by ctx->Driver.Clear.
  66  */
  67 static void
  68 intelClear(GLcontext *ctx, GLbitfield mask)
  69 {
  70    struct intel_context *intel = intel_context(ctx);
  71    const GLuint colorMask = *((GLuint *) & ctx->Color.ColorMask);
  72    GLbitfield tri_mask = 0;
  73    GLbitfield blit_mask = 0;
  74    GLbitfield swrast_mask = 0;
  75    struct gl_framebuffer *fb = ctx->DrawBuffer;
  76    GLuint i;
  77
  78    if (0)
  79       fprintf(stderr, "%s\n", __FUNCTION__);
  80
  81    /* HW color buffers (front, back, aux, generic FBO, etc) */
  82    if (colorMask == ~0) {
  83       /* clear all R,G,B,A */
  84       /* XXX FBO: need to check if colorbuffers are software RBOs! */
  85       blit_mask |= (mask & BUFFER_BITS_COLOR);
  86    }
  87    else {
  88       /* glColorMask in effect */
  89       tri_mask |= (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_BACK_LEFT));
  90    }
  91
  92    /* HW stencil */
  93    if (mask & BUFFER_BIT_STENCIL) {
  94       const struct intel_region *stencilRegion
  95          = intel_get_rb_region(fb, BUFFER_STENCIL);
  96       if (stencilRegion) {
  97          /* have hw stencil */
  98          if (stencilRegion->tiling == I915_TILING_Y ||
  99              (ctx->Stencil.WriteMask[0] & 0xff) != 0xff) {
 100             /* We have to use the 3D engine if we're clearing a partial mask
 101              * of the stencil buffer, or if we're on a 965 which has a tiled
 102              * depth/stencil buffer in a layout we can't blit to.
 103              */
 104             tri_mask |= BUFFER_BIT_STENCIL;
 105          }
 106          else {
 107             /* clearing all stencil bits, use blitting */
 108             blit_mask |= BUFFER_BIT_STENCIL;
 109          }
 110       }
 111    }
 112
 113    /* HW depth */
 114    if (mask & BUFFER_BIT_DEPTH) {
 115       const struct intel_region *irb = intel_get_rb_region(fb, BUFFER_DEPTH);
 116
 117       /* clear depth with whatever method is used for stencil (see above) */
 118       if (irb->tiling == I915_TILING_Y || tri_mask & BUFFER_BIT_STENCIL)
 119          tri_mask |= BUFFER_BIT_DEPTH;
 120       else
 121          blit_mask |= BUFFER_BIT_DEPTH;
 122    }
 123
 124    /* If we're doing a tri pass for depth/stencil, include a likely color
 125     * buffer with it.
 126     */
 127    if (mask & (BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL)) {
 128       int color_bit = _mesa_ffs(mask & BUFFER_BITS_COLOR);
 129       if (color_bit != 0) {
 130          tri_mask |= blit_mask & (1 << (color_bit - 1));
 131          blit_mask &= ~(1 << (color_bit - 1));
 132       }
 133    }
 134
 135    /* SW fallback clearing */
 136    swrast_mask = mask & ~tri_mask & ~blit_mask;
 137
 138    {
 139       /* look for non-Intel renderbuffers (clear them with swrast) */
 140       GLbitfield blit_or_tri = blit_mask | tri_mask;
 141       while (blit_or_tri) {
 142          GLuint i = _mesa_ffs(blit_or_tri) - 1;
 143          GLbitfield bufBit = 1 << i;
 144          if (!fb->Attachment[i].Renderbuffer->ClassID) {
 145             blit_mask &= ~bufBit;
 146             tri_mask &= ~bufBit;
 147             swrast_mask |= bufBit;
 148          }
 149          blit_or_tri ^= bufBit;
 150       }
 151    }
 152
 153    if (blit_mask) {
 154       if (INTEL_DEBUG & DEBUG_BLIT) {
 155          DBG("blit clear:");
 156          for (i = 0; i < BUFFER_COUNT; i++) {
 157             if (blit_mask & (1 << i))
 158                DBG(" %s", buffer_names[i]);
 159          }
 160          DBG("\n");
 161       }
 162       intelClearWithBlit(ctx, blit_mask);
 163    }
 164
 165    if (tri_mask) {
 166       if (INTEL_DEBUG & DEBUG_BLIT) {
 167          DBG("tri clear:");
 168          for (i = 0; i < BUFFER_COUNT; i++) {
 169             if (tri_mask & (1 << i))
 170                DBG(" %s", buffer_names[i]);
 171          }
 172          DBG("\n");
 173       }
 174
 175       _mesa_meta_Clear(&intel->ctx, tri_mask);
 176    }
 177
 178    if (swrast_mask) {
 179       if (INTEL_DEBUG & DEBUG_BLIT) {
 180          DBG("swrast clear:");
 181          for (i = 0; i < BUFFER_COUNT; i++) {
 182             if (swrast_mask & (1 << i))
 183                DBG(" %s", buffer_names[i]);
 184          }
 185          DBG("\n");
 186       }
 187       _swrast_Clear(ctx, swrast_mask);
 188    }
 189 }
 190
 191
 192 void
 193 intelInitClearFuncs(struct dd_function_table *functions)
 194 {
 195    functions->Clear = intelClear;
 196 }