src/mesa/drivers/dri/intel/intel_context.h

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #ifndef INTELCONTEXT_INC
  29 #define INTELCONTEXT_INC
  30
  31
  32 #include <stdbool.h>
  33 #include <string.h>
  34 #include "main/mtypes.h"
  35 #include "main/mm.h"
  36
  37 #ifdef __cplusplus
  38 extern "C" {
  39         /* Evil hack for using libdrm in a c++ compiler. */
  40         #define virtual virt
  41 #endif
  42
  43 #include "drm.h"
  44 #include "intel_bufmgr.h"
  45
  46 #include "intel_screen.h"
  47 #include "intel_tex_obj.h"
  48 #include "i915_drm.h"
  49
  50 #ifdef __cplusplus
  51         #undef virtual
  52 }
  53 #endif
  54
  55 #include "tnl/t_vertex.h"
  56
  57 #define TAG(x) intel##x
  58 #include "tnl_dd/t_dd_vertex.h"
  59 #undef TAG
  60
  61 #define DV_PF_555  (1<<8)
  62 #define DV_PF_565  (2<<8)
  63 #define DV_PF_8888 (3<<8)
  64 #define DV_PF_4444 (8<<8)
  65 #define DV_PF_1555 (9<<8)
  66
  67 struct intel_region;
  68 struct intel_context;
  69
  70 typedef void (*intel_tri_func) (struct intel_context *, intelVertex *,
  71                                 intelVertex *, intelVertex *);
  72 typedef void (*intel_line_func) (struct intel_context *, intelVertex *,
  73                                  intelVertex *);
  74 typedef void (*intel_point_func) (struct intel_context *, intelVertex *);
  75
  76 /**
  77  * Bits for intel->Fallback field
  78  */
  79 /*@{*/
  80 #define INTEL_FALLBACK_DRAW_BUFFER       0x1
  81 #define INTEL_FALLBACK_READ_BUFFER       0x2
  82 #define INTEL_FALLBACK_DEPTH_BUFFER      0x4
  83 #define INTEL_FALLBACK_STENCIL_BUFFER    0x8
  84 #define INTEL_FALLBACK_USER              0x10
  85 #define INTEL_FALLBACK_RENDERMODE        0x20
  86 #define INTEL_FALLBACK_TEXTURE           0x40
  87 #define INTEL_FALLBACK_DRIVER            0x1000  /**< first for drivers */
  88 /*@}*/
  89
  90 extern void intelFallback(struct intel_context *intel, GLbitfield bit,
  91                           bool mode);
  92 #define FALLBACK( intel, bit, mode ) intelFallback( intel, bit, mode )
  93
  94
  95 #define INTEL_WRITE_PART  0x1
  96 #define INTEL_WRITE_FULL  0x2
  97 #define INTEL_READ        0x4
  98
  99 #define INTEL_MAX_FIXUP 64
 100
 101 #ifndef likely
 102 #ifdef __GNUC__
 103 #define likely(expr) (__builtin_expect(expr, 1))
 104 #define unlikely(expr) (__builtin_expect(expr, 0))
 105 #else
 106 #define likely(expr) (expr)
 107 #define unlikely(expr) (expr)
 108 #endif
 109 #endif
 110
 111 struct intel_sync_object {
 112    struct gl_sync_object Base;
 113
 114    /** Batch associated with this sync object */
 115    drm_intel_bo *bo;
 116 };
 117
 118 struct brw_context;
 119
 120 /**
 121  * intel_context is derived from Mesa's context class: struct gl_context.
 122  */
 123 struct intel_context
 124 {
 125    struct gl_context ctx;  /**< base class, must be first field */
 126
 127    struct
 128    {
 129       void (*destroy) (struct intel_context * intel);
 130       void (*emit_state) (struct intel_context * intel);
 131       void (*finish_batch) (struct intel_context * intel);
 132       void (*new_batch) (struct intel_context * intel);
 133       void (*emit_invarient_state) (struct intel_context * intel);
 134       void (*update_texture_state) (struct intel_context * intel);
 135
 136       void (*render_start) (struct intel_context * intel);
 137       void (*render_prevalidate) (struct intel_context * intel);
 138       void (*set_draw_region) (struct intel_context * intel,
 139                                struct intel_region * draw_regions[],
 140                                struct intel_region * depth_region,
 141                                GLuint num_regions);
 142       void (*update_draw_buffer)(struct intel_context *intel);
 143
 144       void (*reduced_primitive_state) (struct intel_context * intel,
 145                                        GLenum rprim);
 146
 147       bool (*check_vertex_size) (struct intel_context * intel,
 148                                       GLuint expected);
 149       void (*invalidate_state) (struct intel_context *intel,
 150                                 GLuint new_state);
 151
 152       void (*assert_not_dirty) (struct intel_context *intel);
 153
 154       void (*debug_batch)(struct intel_context *intel);
 155       bool (*render_target_supported)(struct intel_context *intel,
 156                                       struct gl_renderbuffer *rb);
 157
 158       /** Can HiZ be enabled on a depthbuffer of the given format? */
 159       bool (*is_hiz_depth_format)(struct intel_context *intel,
 160                                   gl_format format);
 161
 162       /**
 163        * \name HiZ operations
 164        *
 165        * See the following sections of the Sandy Bridge PRM, Volume 1, Part2:
 166        *   - 7.5.3.1 Depth Buffer Clear
 167        *   - 7.5.3.2 Depth Buffer Resolve
 168        *   - 7.5.3.3 Hierarchical Depth Buffer Resolve
 169        * \{
 170        */
 171       void (*resolve_hiz_slice)(struct intel_context *intel,
 172                                 struct intel_mipmap_tree *mt,
 173                                 uint32_t level,
 174                                 uint32_t layer);
 175
 176       void (*resolve_depth_slice)(struct intel_context *intel,
 177                                   struct intel_mipmap_tree *mt,
 178                                   uint32_t level,
 179                                   uint32_t layer);
 180       /** \} */
 181
 182       /**
 183        * Surface state operations (i965+ only)
 184        * \{
 185        */
 186       void (*update_texture_surface)(struct gl_context *ctx, unsigned unit);
 187       void (*update_renderbuffer_surface)(struct brw_context *brw,
 188                                           struct gl_renderbuffer *rb,
 189                                           unsigned unit);
 190       void (*update_null_renderbuffer_surface)(struct brw_context *brw,
 191                                                unsigned unit);
 192       void (*create_constant_surface)(struct brw_context *brw,
 193                                       drm_intel_bo *bo,
 194                                       int width,
 195                                       uint32_t *out_offset);
 196       /** \} */
 197    } vtbl;
 198
 199    GLbitfield Fallback;  /**< mask of INTEL_FALLBACK_x bits */
 200    GLuint NewGLState;
 201
 202    dri_bufmgr *bufmgr;
 203    unsigned int maxBatchSize;
 204
 205    /**
 206     * Generation number of the hardware: 2 is 8xx, 3 is 9xx pre-965, 4 is 965.
 207     */
 208    int gen;
 209    int gt;
 210    bool needs_ff_sync;
 211    bool is_g4x;
 212    bool is_945;
 213    bool has_separate_stencil;
 214    bool must_use_separate_stencil;
 215    bool has_hiz;
 216    bool has_llc;
 217
 218    int urb_size;
 219
 220    struct intel_batchbuffer {
 221       /** Current batchbuffer being queued up. */
 222       drm_intel_bo *bo;
 223       /** Last BO submitted to the hardware.  Used for glFinish(). */
 224       drm_intel_bo *last_bo;
 225       /** BO for post-sync nonzero writes for gen6 workaround. */
 226       drm_intel_bo *workaround_bo;
 227       bool need_workaround_flush;
 228
 229       struct cached_batch_item *cached_items;
 230
 231       uint16_t emit, total;
 232       uint16_t used, reserved_space;
 233       uint32_t map[8192];
 234 #define BATCH_SZ (8192*sizeof(uint32_t))
 235
 236       uint32_t state_batch_offset;
 237       bool is_blit;
 238       bool needs_sol_reset;
 239
 240       struct {
 241          uint16_t used;
 242          int reloc_count;
 243       } saved;
 244    } batch;
 245
 246    drm_intel_bo *first_post_swapbuffers_batch;
 247    bool need_throttle;
 248    bool no_batch_wrap;
 249    bool tnl_pipeline_running; /**< Set while i915's _tnl_run_pipeline. */
 250
 251    struct
 252    {
 253       GLuint id;
 254       uint32_t start_ptr; /**< for i8xx */
 255       uint32_t primitive;       /**< Current hardware primitive type */
 256       void (*flush) (struct intel_context *);
 257       drm_intel_bo *vb_bo;
 258       uint8_t *vb;
 259       unsigned int start_offset; /**< Byte offset of primitive sequence */
 260       unsigned int current_offset; /**< Byte offset of next vertex */
 261       unsigned int count;       /**< Number of vertices in current primitive */
 262    } prim;
 263
 264    struct {
 265       drm_intel_bo *bo;
 266       GLuint offset;
 267       uint32_t buffer_len;
 268       uint32_t buffer_offset;
 269       char buffer[4096];
 270    } upload;
 271
 272    GLuint stats_wm;
 273
 274    /* Offsets of fields within the current vertex:
 275     */
 276    GLuint coloroffset;
 277    GLuint specoffset;
 278    GLuint wpos_offset;
 279
 280    struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
 281    GLuint vertex_attr_count;
 282
 283    GLfloat polygon_offset_scale;        /* dependent on depth_scale, bpp */
 284
 285    bool hw_stencil;
 286    bool hw_stipple;
 287    bool no_rast;
 288    bool always_flush_batch;
 289    bool always_flush_cache;
 290
 291    /* 0 - nonconformant, best performance;
 292     * 1 - fallback to sw for known conformance bugs
 293     * 2 - always fallback to sw
 294     */
 295    GLuint conformance_mode;
 296
 297    /* State for intelvb.c and inteltris.c.
 298     */
 299    GLuint RenderIndex;
 300    GLmatrix ViewportMatrix;
 301    GLenum render_primitive;
 302    GLenum reduced_primitive; /*< Only gen < 6 */
 303    GLuint vertex_size;
 304    GLubyte *verts;              /* points to tnl->clipspace.vertex_buf */
 305
 306    /* Fallback rasterization functions
 307     */
 308    intel_point_func draw_point;
 309    intel_line_func draw_line;
 310    intel_tri_func draw_tri;
 311
 312    /**
 313     * Set if rendering has occured to the drawable's front buffer.
 314     *
 315     * This is used in the DRI2 case to detect that glFlush should also copy
 316     * the contents of the fake front buffer to the real front buffer.
 317     */
 318    bool front_buffer_dirty;
 319
 320    /**
 321     * Track whether front-buffer rendering is currently enabled
 322     *
 323     * A separate flag is used to track this in order to support MRT more
 324     * easily.
 325     */
 326    bool is_front_buffer_rendering;
 327    /**
 328     * Track whether front-buffer is the current read target.
 329     *
 330     * This is closely associated with is_front_buffer_rendering, but may
 331     * be set separately.  The DRI2 fake front buffer must be referenced
 332     * either way.
 333     */
 334    bool is_front_buffer_reading;
 335
 336    /**
 337     * Count of intel_regions that are mapped.
 338     *
 339     * This allows us to assert that no batch buffer is emitted if a
 340     * region is mapped.
 341     */
 342    int num_mapped_regions;
 343
 344    bool use_texture_tiling;
 345    bool use_early_z;
 346
 347    int driFd;
 348
 349    __DRIcontext *driContext;
 350    struct intel_screen *intelScreen;
 351    void (*saved_viewport)(struct gl_context * ctx,
 352                           GLint x, GLint y, GLsizei width, GLsizei height);
 353
 354    /**
 355     * Configuration cache
 356     */
 357    driOptionCache optionCache;
 358 };
 359
 360 extern char *__progname;
 361
 362
 363 #define SUBPIXEL_X 0.125
 364 #define SUBPIXEL_Y 0.125
 365
 366 #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
 367
 368 /**
 369  * Align a value up to an alignment value
 370  *
 371  * If \c value is not already aligned to the requested alignment value, it
 372  * will be rounded up.
 373  *
 374  * \param value  Value to be rounded
 375  * \param alignment  Alignment value to be used.  This must be a power of two.
 376  *
 377  * \sa ROUND_DOWN_TO()
 378  */
 379 #define ALIGN(value, alignment)  (((value) + alignment - 1) & ~(alignment - 1))
 380
 381 /**
 382  * Align a value down to an alignment value
 383  *
 384  * If \c value is not already aligned to the requested alignment value, it
 385  * will be rounded down.
 386  *
 387  * \param value  Value to be rounded
 388  * \param alignment  Alignment value to be used.  This must be a power of two.
 389  *
 390  * \sa ALIGN()
 391  */
 392 #define ROUND_DOWN_TO(value, alignment) ((value) & ~(alignment - 1))
 393
 394 #define IS_POWER_OF_TWO(val) (((val) & (val - 1)) == 0)
 395
 396 static INLINE uint32_t
 397 U_FIXED(float value, uint32_t frac_bits)
 398 {
 399    value *= (1 << frac_bits);
 400    return value < 0 ? 0 : value;
 401 }
 402
 403 static INLINE uint32_t
 404 S_FIXED(float value, uint32_t frac_bits)
 405 {
 406    return value * (1 << frac_bits);
 407 }
 408
 409 #define INTEL_FIREVERTICES(intel)               \
 410 do {                                            \
 411    if ((intel)->prim.flush)                     \
 412       (intel)->prim.flush(intel);               \
 413 } while (0)
 414
 415 /* ================================================================
 416  * From linux kernel i386 header files, copes with odd sizes better
 417  * than COPY_DWORDS would:
 418  * XXX Put this in src/mesa/main/imports.h ???
 419  */
 420 #if defined(i386) || defined(__i386__)
 421 static INLINE void * __memcpy(void * to, const void * from, size_t n)
 422 {
 423    int d0, d1, d2;
 424    __asm__ __volatile__(
 425       "rep ; movsl\n\t"
 426       "testb $2,%b4\n\t"
 427       "je 1f\n\t"
 428       "movsw\n"
 429       "1:\ttestb $1,%b4\n\t"
 430       "je 2f\n\t"
 431       "movsb\n"
 432       "2:"
 433       : "=&c" (d0), "=&D" (d1), "=&S" (d2)
 434       :"0" (n/4), "q" (n),"1" ((long) to),"2" ((long) from)
 435       : "memory");
 436    return (to);
 437 }
 438 #else
 439 #define __memcpy(a,b,c) memcpy(a,b,c)
 440 #endif
 441
 442
 443 /* ================================================================
 444  * Debugging:
 445  */
 446 extern int INTEL_DEBUG;
 447
 448 #define DEBUG_TEXTURE   0x1
 449 #define DEBUG_STATE     0x2
 450 #define DEBUG_IOCTL     0x4
 451 #define DEBUG_BLIT      0x8
 452 #define DEBUG_MIPTREE   0x10
 453 #define DEBUG_FALLBACKS 0x20
 454 #define DEBUG_VERBOSE   0x40
 455 #define DEBUG_BATCH     0x80
 456 #define DEBUG_PIXEL     0x100
 457 #define DEBUG_BUFMGR    0x200
 458 #define DEBUG_REGION    0x400
 459 #define DEBUG_FBO       0x800
 460 #define DEBUG_GS        0x1000
 461 #define DEBUG_SYNC      0x2000
 462 #define DEBUG_PRIMS     0x4000
 463 #define DEBUG_VERTS     0x8000
 464 #define DEBUG_DRI       0x10000
 465 #define DEBUG_SF        0x20000
 466 #define DEBUG_SANITY    0x40000
 467 #define DEBUG_SLEEP     0x80000
 468 #define DEBUG_STATS     0x100000
 469 #define DEBUG_TILE      0x200000
 470 #define DEBUG_WM        0x400000
 471 #define DEBUG_URB       0x800000
 472 #define DEBUG_VS        0x1000000
 473 #define DEBUG_CLIP      0x2000000
 474
 475 #define DBG(...) do {                                           \
 476         if (unlikely(INTEL_DEBUG & FILE_DEBUG_FLAG))            \
 477                 printf(__VA_ARGS__);                    \
 478 } while(0)
 479
 480 #define fallback_debug(...) do {                                \
 481         if (unlikely(INTEL_DEBUG & DEBUG_FALLBACKS))            \
 482                 printf(__VA_ARGS__);                            \
 483 } while(0)
 484
 485 #define PCI_CHIP_845_G                  0x2562
 486 #define PCI_CHIP_I830_M                 0x3577
 487 #define PCI_CHIP_I855_GM                0x3582
 488 #define PCI_CHIP_I865_G                 0x2572
 489 #define PCI_CHIP_I915_G                 0x2582
 490 #define PCI_CHIP_I915_GM                0x2592
 491 #define PCI_CHIP_I945_G                 0x2772
 492 #define PCI_CHIP_I945_GM                0x27A2
 493 #define PCI_CHIP_I945_GME               0x27AE
 494 #define PCI_CHIP_G33_G                  0x29C2
 495 #define PCI_CHIP_Q35_G                  0x29B2
 496 #define PCI_CHIP_Q33_G                  0x29D2
 497
 498
 499 /* ================================================================
 500  * intel_context.c:
 501  */
 502
 503 extern bool intelInitContext(struct intel_context *intel,
 504                                   int api,
 505                                   const struct gl_config * mesaVis,
 506                                   __DRIcontext * driContextPriv,
 507                                   void *sharedContextPrivate,
 508                                   struct dd_function_table *functions);
 509
 510 extern void intelFinish(struct gl_context * ctx);
 511 extern void intel_flush_rendering_to_batch(struct gl_context *ctx);
 512 extern void _intel_flush(struct gl_context * ctx, const char *file, int line);
 513
 514 #define intel_flush(ctx) _intel_flush(ctx, __FILE__, __LINE__)
 515
 516 extern void intelInitDriverFunctions(struct dd_function_table *functions);
 517
 518 void intel_init_syncobj_functions(struct dd_function_table *functions);
 519
 520
 521 /* ================================================================
 522  * intel_state.c:
 523  */
 524 extern void intelInitStateFuncs(struct dd_function_table *functions);
 525
 526 #define COMPAREFUNC_ALWAYS              0
 527 #define COMPAREFUNC_NEVER               0x1
 528 #define COMPAREFUNC_LESS                0x2
 529 #define COMPAREFUNC_EQUAL               0x3
 530 #define COMPAREFUNC_LEQUAL              0x4
 531 #define COMPAREFUNC_GREATER             0x5
 532 #define COMPAREFUNC_NOTEQUAL            0x6
 533 #define COMPAREFUNC_GEQUAL              0x7
 534
 535 #define STENCILOP_KEEP                  0
 536 #define STENCILOP_ZERO                  0x1
 537 #define STENCILOP_REPLACE               0x2
 538 #define STENCILOP_INCRSAT               0x3
 539 #define STENCILOP_DECRSAT               0x4
 540 #define STENCILOP_INCR                  0x5
 541 #define STENCILOP_DECR                  0x6
 542 #define STENCILOP_INVERT                0x7
 543
 544 #define LOGICOP_CLEAR                   0
 545 #define LOGICOP_NOR                     0x1
 546 #define LOGICOP_AND_INV                 0x2
 547 #define LOGICOP_COPY_INV                0x3
 548 #define LOGICOP_AND_RVRSE               0x4
 549 #define LOGICOP_INV                     0x5
 550 #define LOGICOP_XOR                     0x6
 551 #define LOGICOP_NAND                    0x7
 552 #define LOGICOP_AND                     0x8
 553 #define LOGICOP_EQUIV                   0x9
 554 #define LOGICOP_NOOP                    0xa
 555 #define LOGICOP_OR_INV                  0xb
 556 #define LOGICOP_COPY                    0xc
 557 #define LOGICOP_OR_RVRSE                0xd
 558 #define LOGICOP_OR                      0xe
 559 #define LOGICOP_SET                     0xf
 560
 561 #define BLENDFACT_ZERO                  0x01
 562 #define BLENDFACT_ONE                   0x02
 563 #define BLENDFACT_SRC_COLR              0x03
 564 #define BLENDFACT_INV_SRC_COLR          0x04
 565 #define BLENDFACT_SRC_ALPHA             0x05
 566 #define BLENDFACT_INV_SRC_ALPHA         0x06
 567 #define BLENDFACT_DST_ALPHA             0x07
 568 #define BLENDFACT_INV_DST_ALPHA         0x08
 569 #define BLENDFACT_DST_COLR              0x09
 570 #define BLENDFACT_INV_DST_COLR          0x0a
 571 #define BLENDFACT_SRC_ALPHA_SATURATE    0x0b
 572 #define BLENDFACT_CONST_COLOR           0x0c
 573 #define BLENDFACT_INV_CONST_COLOR       0x0d
 574 #define BLENDFACT_CONST_ALPHA           0x0e
 575 #define BLENDFACT_INV_CONST_ALPHA       0x0f
 576 #define BLENDFACT_MASK                  0x0f
 577
 578 enum {
 579    DRI_CONF_BO_REUSE_DISABLED,
 580    DRI_CONF_BO_REUSE_ALL
 581 };
 582
 583 extern int intel_translate_shadow_compare_func(GLenum func);
 584 extern int intel_translate_compare_func(GLenum func);
 585 extern int intel_translate_stencil_op(GLenum op);
 586 extern int intel_translate_blend_factor(GLenum factor);
 587 extern int intel_translate_logic_op(GLenum opcode);
 588
 589 void intel_update_renderbuffers(__DRIcontext *context,
 590                                 __DRIdrawable *drawable);
 591 void intel_prepare_render(struct intel_context *intel);
 592
 593 void i915_set_buf_info_for_region(uint32_t *state, struct intel_region *region,
 594                                   uint32_t buffer_id);
 595 void intel_init_texture_formats(struct gl_context *ctx);
 596
 597 /*======================================================================
 598  * Inline conversion functions.
 599  * These are better-typed than the macros used previously:
 600  */
 601 static INLINE struct intel_context *
 602 intel_context(struct gl_context * ctx)
 603 {
 604    return (struct intel_context *) ctx;
 605 }
 606
 607 static INLINE bool
 608 is_power_of_two(uint32_t value)
 609 {
 610    return (value & (value - 1)) == 0;
 611 }
 612
 613 #endif