1 /**************************************************************************
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #ifndef INTELCONTEXT_INC
29 #define INTELCONTEXT_INC
34 #include "main/mtypes.h"
39 /* Evil hack for using libdrm in a c++ compiler. */
44 #include "intel_bufmgr.h"
46 #include "intel_screen.h"
47 #include "intel_tex_obj.h"
54 #include "tnl/t_vertex.h"
56 #define TAG(x) intel##x
57 #include "tnl_dd/t_dd_vertex.h"
60 #define DV_PF_555 (1<<8)
61 #define DV_PF_565 (2<<8)
62 #define DV_PF_8888 (3<<8)
63 #define DV_PF_4444 (8<<8)
64 #define DV_PF_1555 (9<<8)
69 typedef void (*intel_tri_func
) (struct intel_context
*, intelVertex
*,
70 intelVertex
*, intelVertex
*);
71 typedef void (*intel_line_func
) (struct intel_context
*, intelVertex
*,
73 typedef void (*intel_point_func
) (struct intel_context
*, intelVertex
*);
76 * Bits for intel->Fallback field
79 #define INTEL_FALLBACK_DRAW_BUFFER 0x1
80 #define INTEL_FALLBACK_READ_BUFFER 0x2
81 #define INTEL_FALLBACK_DEPTH_BUFFER 0x4
82 #define INTEL_FALLBACK_STENCIL_BUFFER 0x8
83 #define INTEL_FALLBACK_USER 0x10
84 #define INTEL_FALLBACK_RENDERMODE 0x20
85 #define INTEL_FALLBACK_TEXTURE 0x40
86 #define INTEL_FALLBACK_DRIVER 0x1000 /**< first for drivers */
89 extern void intelFallback(struct intel_context
*intel
, GLbitfield bit
,
91 #define FALLBACK( intel, bit, mode ) intelFallback( intel, bit, mode )
94 #define INTEL_WRITE_PART 0x1
95 #define INTEL_WRITE_FULL 0x2
96 #define INTEL_READ 0x4
98 #define INTEL_MAX_FIXUP 64
102 #define likely(expr) (__builtin_expect(expr, 1))
103 #define unlikely(expr) (__builtin_expect(expr, 0))
105 #define likely(expr) (expr)
106 #define unlikely(expr) (expr)
110 struct intel_sync_object
{
111 struct gl_sync_object Base
;
113 /** Batch associated with this sync object */
119 struct intel_batchbuffer
{
120 /** Current batchbuffer being queued up. */
122 /** Last BO submitted to the hardware. Used for glFinish(). */
123 drm_intel_bo
*last_bo
;
124 /** BO for post-sync nonzero writes for gen6 workaround. */
125 drm_intel_bo
*workaround_bo
;
126 bool need_workaround_flush
;
128 struct cached_batch_item
*cached_items
;
130 uint16_t emit
, total
;
131 uint16_t used
, reserved_space
;
134 #define BATCH_SZ (8192*sizeof(uint32_t))
136 uint32_t state_batch_offset
;
138 bool needs_sol_reset
;
147 * intel_context is derived from Mesa's context class: struct gl_context.
151 struct gl_context ctx
; /**< base class, must be first field */
155 void (*destroy
) (struct intel_context
* intel
);
156 void (*emit_state
) (struct intel_context
* intel
);
157 void (*finish_batch
) (struct intel_context
* intel
);
158 void (*new_batch
) (struct intel_context
* intel
);
159 void (*emit_invarient_state
) (struct intel_context
* intel
);
160 void (*update_texture_state
) (struct intel_context
* intel
);
162 void (*render_start
) (struct intel_context
* intel
);
163 void (*render_prevalidate
) (struct intel_context
* intel
);
164 void (*set_draw_region
) (struct intel_context
* intel
,
165 struct intel_region
* draw_regions
[],
166 struct intel_region
* depth_region
,
168 void (*update_draw_buffer
)(struct intel_context
*intel
);
170 void (*reduced_primitive_state
) (struct intel_context
* intel
,
173 bool (*check_vertex_size
) (struct intel_context
* intel
,
175 void (*invalidate_state
) (struct intel_context
*intel
,
178 void (*assert_not_dirty
) (struct intel_context
*intel
);
180 void (*debug_batch
)(struct intel_context
*intel
);
181 void (*annotate_aub
)(struct intel_context
*intel
);
182 bool (*render_target_supported
)(struct intel_context
*intel
,
183 struct gl_renderbuffer
*rb
);
185 /** Can HiZ be enabled on a depthbuffer of the given format? */
186 bool (*is_hiz_depth_format
)(struct intel_context
*intel
,
190 * Surface state operations (i965+ only)
193 void (*update_texture_surface
)(struct gl_context
*ctx
,
195 uint32_t *binding_table
,
196 unsigned surf_index
);
197 void (*update_renderbuffer_surface
)(struct brw_context
*brw
,
198 struct gl_renderbuffer
*rb
,
201 void (*update_null_renderbuffer_surface
)(struct brw_context
*brw
,
203 void (*create_constant_surface
)(struct brw_context
*brw
,
207 uint32_t *out_offset
,
212 * Send the appropriate state packets to configure depth, stencil, and
213 * HiZ buffers (i965+ only)
215 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
216 struct intel_mipmap_tree
*depth_mt
,
217 uint32_t depth_offset
,
218 uint32_t depthbuffer_format
,
219 uint32_t depth_surface_type
,
220 struct intel_mipmap_tree
*stencil_mt
,
221 bool hiz
, bool separate_stencil
,
222 uint32_t width
, uint32_t height
,
223 uint32_t tile_x
, uint32_t tile_y
);
227 GLbitfield Fallback
; /**< mask of INTEL_FALLBACK_x bits */
231 unsigned int maxBatchSize
;
234 * Generation number of the hardware: 2 is 8xx, 3 is 9xx pre-965, 4 is 965.
243 bool has_separate_stencil
;
244 bool must_use_separate_stencil
;
251 drm_intel_context
*hw_ctx
;
253 struct intel_batchbuffer batch
;
255 drm_intel_bo
*first_post_swapbuffers_batch
;
258 bool tnl_pipeline_running
; /**< Set while i915's _tnl_run_pipeline. */
261 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
262 * variable is set, this is the flag indicating to do expensive work that
263 * might lead to a perf_debug() call.
270 uint32_t start_ptr
; /**< for i8xx */
271 uint32_t primitive
; /**< Current hardware primitive type */
272 void (*flush
) (struct intel_context
*);
275 unsigned int start_offset
; /**< Byte offset of primitive sequence */
276 unsigned int current_offset
; /**< Byte offset of next vertex */
277 unsigned int count
; /**< Number of vertices in current primitive */
284 uint32_t buffer_offset
;
288 uint32_t max_gtt_map_object_size
;
292 /* Offsets of fields within the current vertex:
298 struct tnl_attr_map vertex_attrs
[VERT_ATTRIB_MAX
];
299 GLuint vertex_attr_count
;
301 GLfloat polygon_offset_scale
; /* dependent on depth_scale, bpp */
306 bool always_flush_batch
;
307 bool always_flush_cache
;
308 bool disable_throttling
;
310 /* State for intelvb.c and inteltris.c.
313 GLmatrix ViewportMatrix
;
314 GLenum render_primitive
;
315 GLenum reduced_primitive
; /*< Only gen < 6 */
317 GLubyte
*verts
; /* points to tnl->clipspace.vertex_buf */
319 /* Fallback rasterization functions
321 intel_point_func draw_point
;
322 intel_line_func draw_line
;
323 intel_tri_func draw_tri
;
326 * Set if rendering has occured to the drawable's front buffer.
328 * This is used in the DRI2 case to detect that glFlush should also copy
329 * the contents of the fake front buffer to the real front buffer.
331 bool front_buffer_dirty
;
334 * Track whether front-buffer rendering is currently enabled
336 * A separate flag is used to track this in order to support MRT more
339 bool is_front_buffer_rendering
;
341 * Track whether front-buffer is the current read target.
343 * This is closely associated with is_front_buffer_rendering, but may
344 * be set separately. The DRI2 fake front buffer must be referenced
347 bool is_front_buffer_reading
;
353 __DRIcontext
*driContext
;
354 struct intel_screen
*intelScreen
;
355 void (*saved_viewport
)(struct gl_context
* ctx
,
356 GLint x
, GLint y
, GLsizei width
, GLsizei height
);
359 * Configuration cache
361 driOptionCache optionCache
;
364 extern char *__progname
;
367 #define SUBPIXEL_X 0.125
368 #define SUBPIXEL_Y 0.125
371 * Align a value down to an alignment value
373 * If \c value is not already aligned to the requested alignment value, it
374 * will be rounded down.
376 * \param value Value to be rounded
377 * \param alignment Alignment value to be used. This must be a power of two.
381 #define ROUND_DOWN_TO(value, alignment) ((value) & ~(alignment - 1))
383 #define IS_POWER_OF_TWO(val) (((val) & (val - 1)) == 0)
385 static INLINE
uint32_t
386 U_FIXED(float value
, uint32_t frac_bits
)
388 value
*= (1 << frac_bits
);
389 return value
< 0 ? 0 : value
;
392 static INLINE
uint32_t
393 S_FIXED(float value
, uint32_t frac_bits
)
395 return value
* (1 << frac_bits
);
398 #define INTEL_FIREVERTICES(intel) \
400 if ((intel)->prim.flush) \
401 (intel)->prim.flush(intel); \
404 /* ================================================================
405 * From linux kernel i386 header files, copes with odd sizes better
406 * than COPY_DWORDS would:
407 * XXX Put this in src/mesa/main/imports.h ???
409 #if defined(i386) || defined(__i386__)
410 static INLINE
void * __memcpy(void * to
, const void * from
, size_t n
)
413 __asm__
__volatile__(
418 "1:\ttestb $1,%b4\n\t"
422 : "=&c" (d0
), "=&D" (d1
), "=&S" (d2
)
423 :"0" (n
/4), "q" (n
),"1" ((long) to
),"2" ((long) from
)
428 #define __memcpy(a,b,c) memcpy(a,b,c)
432 /* ================================================================
435 extern int INTEL_DEBUG
;
437 #define DEBUG_TEXTURE 0x1
438 #define DEBUG_STATE 0x2
439 #define DEBUG_IOCTL 0x4
440 #define DEBUG_BLIT 0x8
441 #define DEBUG_MIPTREE 0x10
442 #define DEBUG_PERF 0x20
443 #define DEBUG_BATCH 0x80
444 #define DEBUG_PIXEL 0x100
445 #define DEBUG_BUFMGR 0x200
446 #define DEBUG_REGION 0x400
447 #define DEBUG_FBO 0x800
448 #define DEBUG_GS 0x1000
449 #define DEBUG_SYNC 0x2000
450 #define DEBUG_PRIMS 0x4000
451 #define DEBUG_VERTS 0x8000
452 #define DEBUG_DRI 0x10000
453 #define DEBUG_SF 0x20000
454 #define DEBUG_STATS 0x100000
455 #define DEBUG_WM 0x400000
456 #define DEBUG_URB 0x800000
457 #define DEBUG_VS 0x1000000
458 #define DEBUG_CLIP 0x2000000
459 #define DEBUG_AUB 0x4000000
460 #define DEBUG_SHADER_TIME 0x8000000
461 #define DEBUG_BLORP 0x10000000
462 #define DEBUG_NO16 0x20000000
464 #ifdef HAVE_ANDROID_PLATFORM
465 #define LOG_TAG "INTEL-MESA"
466 #include <cutils/log.h>
470 #define dbg_printf(...) ALOGW(__VA_ARGS__)
472 #define dbg_printf(...) printf(__VA_ARGS__)
473 #endif /* HAVE_ANDROID_PLATFORM */
475 #define DBG(...) do { \
476 if (unlikely(INTEL_DEBUG & FILE_DEBUG_FLAG)) \
477 dbg_printf(__VA_ARGS__); \
480 #define perf_debug(...) do { \
481 static GLuint msg_id = 0; \
482 if (unlikely(INTEL_DEBUG & DEBUG_PERF)) \
483 dbg_printf(__VA_ARGS__); \
484 if (intel->perf_debug) \
485 _mesa_gl_debug(&intel->ctx, &msg_id, \
486 MESA_DEBUG_TYPE_PERFORMANCE, \
487 MESA_DEBUG_SEVERITY_MEDIUM, \
491 #define WARN_ONCE(cond, fmt...) do { \
492 if (unlikely(cond)) { \
493 static bool _warned = false; \
494 static GLuint msg_id = 0; \
496 fprintf(stderr, "WARNING: "); \
497 fprintf(stderr, fmt); \
500 _mesa_gl_debug(ctx, &msg_id, \
501 MESA_DEBUG_TYPE_OTHER, \
502 MESA_DEBUG_SEVERITY_HIGH, fmt); \
507 #define PCI_CHIP_845_G 0x2562
508 #define PCI_CHIP_I830_M 0x3577
509 #define PCI_CHIP_I855_GM 0x3582
510 #define PCI_CHIP_I865_G 0x2572
511 #define PCI_CHIP_I915_G 0x2582
512 #define PCI_CHIP_I915_GM 0x2592
513 #define PCI_CHIP_I945_G 0x2772
514 #define PCI_CHIP_I945_GM 0x27A2
515 #define PCI_CHIP_I945_GME 0x27AE
516 #define PCI_CHIP_G33_G 0x29C2
517 #define PCI_CHIP_Q35_G 0x29B2
518 #define PCI_CHIP_Q33_G 0x29D2
521 /* ================================================================
525 extern bool intelInitContext(struct intel_context
*intel
,
527 unsigned major_version
,
528 unsigned minor_version
,
529 const struct gl_config
* mesaVis
,
530 __DRIcontext
* driContextPriv
,
531 void *sharedContextPrivate
,
532 struct dd_function_table
*functions
,
533 unsigned *dri_ctx_error
);
535 extern void intelFinish(struct gl_context
* ctx
);
536 extern void intel_flush_rendering_to_batch(struct gl_context
*ctx
);
537 extern void _intel_flush(struct gl_context
* ctx
, const char *file
, int line
);
539 #define intel_flush(ctx) _intel_flush(ctx, __FILE__, __LINE__)
541 extern void intelInitDriverFunctions(struct dd_function_table
*functions
);
543 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
546 /* ================================================================
550 #define COMPAREFUNC_ALWAYS 0
551 #define COMPAREFUNC_NEVER 0x1
552 #define COMPAREFUNC_LESS 0x2
553 #define COMPAREFUNC_EQUAL 0x3
554 #define COMPAREFUNC_LEQUAL 0x4
555 #define COMPAREFUNC_GREATER 0x5
556 #define COMPAREFUNC_NOTEQUAL 0x6
557 #define COMPAREFUNC_GEQUAL 0x7
559 #define STENCILOP_KEEP 0
560 #define STENCILOP_ZERO 0x1
561 #define STENCILOP_REPLACE 0x2
562 #define STENCILOP_INCRSAT 0x3
563 #define STENCILOP_DECRSAT 0x4
564 #define STENCILOP_INCR 0x5
565 #define STENCILOP_DECR 0x6
566 #define STENCILOP_INVERT 0x7
568 #define LOGICOP_CLEAR 0
569 #define LOGICOP_NOR 0x1
570 #define LOGICOP_AND_INV 0x2
571 #define LOGICOP_COPY_INV 0x3
572 #define LOGICOP_AND_RVRSE 0x4
573 #define LOGICOP_INV 0x5
574 #define LOGICOP_XOR 0x6
575 #define LOGICOP_NAND 0x7
576 #define LOGICOP_AND 0x8
577 #define LOGICOP_EQUIV 0x9
578 #define LOGICOP_NOOP 0xa
579 #define LOGICOP_OR_INV 0xb
580 #define LOGICOP_COPY 0xc
581 #define LOGICOP_OR_RVRSE 0xd
582 #define LOGICOP_OR 0xe
583 #define LOGICOP_SET 0xf
585 #define BLENDFACT_ZERO 0x01
586 #define BLENDFACT_ONE 0x02
587 #define BLENDFACT_SRC_COLR 0x03
588 #define BLENDFACT_INV_SRC_COLR 0x04
589 #define BLENDFACT_SRC_ALPHA 0x05
590 #define BLENDFACT_INV_SRC_ALPHA 0x06
591 #define BLENDFACT_DST_ALPHA 0x07
592 #define BLENDFACT_INV_DST_ALPHA 0x08
593 #define BLENDFACT_DST_COLR 0x09
594 #define BLENDFACT_INV_DST_COLR 0x0a
595 #define BLENDFACT_SRC_ALPHA_SATURATE 0x0b
596 #define BLENDFACT_CONST_COLOR 0x0c
597 #define BLENDFACT_INV_CONST_COLOR 0x0d
598 #define BLENDFACT_CONST_ALPHA 0x0e
599 #define BLENDFACT_INV_CONST_ALPHA 0x0f
600 #define BLENDFACT_MASK 0x0f
603 DRI_CONF_BO_REUSE_DISABLED
,
604 DRI_CONF_BO_REUSE_ALL
607 extern int intel_translate_shadow_compare_func(GLenum func
);
608 extern int intel_translate_compare_func(GLenum func
);
609 extern int intel_translate_stencil_op(GLenum op
);
610 extern int intel_translate_blend_factor(GLenum factor
);
611 extern int intel_translate_logic_op(GLenum opcode
);
613 void intel_update_renderbuffers(__DRIcontext
*context
,
614 __DRIdrawable
*drawable
);
615 void intel_prepare_render(struct intel_context
*intel
);
618 intel_downsample_for_dri2_flush(struct intel_context
*intel
,
619 __DRIdrawable
*drawable
);
621 void i915_set_buf_info_for_region(uint32_t *state
, struct intel_region
*region
,
623 void intel_init_texture_formats(struct gl_context
*ctx
);
625 /*======================================================================
626 * Inline conversion functions.
627 * These are better-typed than the macros used previously:
629 static INLINE
struct intel_context
*
630 intel_context(struct gl_context
* ctx
)
632 return (struct intel_context
*) ctx
;
636 is_power_of_two(uint32_t value
)
638 return (value
& (value
- 1)) == 0;