src/mesa/drivers/dri/intel/intel_context.h

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #ifndef INTELCONTEXT_INC
  29 #define INTELCONTEXT_INC
  30
  31
  32 #include <stdbool.h>
  33 #include "main/mtypes.h"
  34 #include "main/mm.h"
  35
  36 #ifdef __cplusplus
  37 extern "C" {
  38         /* Evil hack for using libdrm in a c++ compiler. */
  39         #define virtual virt
  40 #endif
  41
  42 #include "drm.h"
  43 #include "intel_bufmgr.h"
  44
  45 #include "intel_screen.h"
  46 #include "intel_tex_obj.h"
  47 #include "i915_drm.h"
  48
  49 #ifdef __cplusplus
  50         #undef virtual
  51 }
  52 #endif
  53
  54 #include "tnl/t_vertex.h"
  55
  56 #define TAG(x) intel##x
  57 #include "tnl_dd/t_dd_vertex.h"
  58 #undef TAG
  59
  60 #define DV_PF_555  (1<<8)
  61 #define DV_PF_565  (2<<8)
  62 #define DV_PF_8888 (3<<8)
  63 #define DV_PF_4444 (8<<8)
  64 #define DV_PF_1555 (9<<8)
  65
  66 struct intel_region;
  67 struct intel_context;
  68
  69 typedef void (*intel_tri_func) (struct intel_context *, intelVertex *,
  70                                 intelVertex *, intelVertex *);
  71 typedef void (*intel_line_func) (struct intel_context *, intelVertex *,
  72                                  intelVertex *);
  73 typedef void (*intel_point_func) (struct intel_context *, intelVertex *);
  74
  75 /**
  76  * Bits for intel->Fallback field
  77  */
  78 /*@{*/
  79 #define INTEL_FALLBACK_DRAW_BUFFER       0x1
  80 #define INTEL_FALLBACK_READ_BUFFER       0x2
  81 #define INTEL_FALLBACK_DEPTH_BUFFER      0x4
  82 #define INTEL_FALLBACK_STENCIL_BUFFER    0x8
  83 #define INTEL_FALLBACK_USER              0x10
  84 #define INTEL_FALLBACK_RENDERMODE        0x20
  85 #define INTEL_FALLBACK_TEXTURE           0x40
  86 #define INTEL_FALLBACK_DRIVER            0x1000  /**< first for drivers */
  87 /*@}*/
  88
  89 extern void intelFallback(struct intel_context *intel, GLbitfield bit,
  90                           bool mode);
  91 #define FALLBACK( intel, bit, mode ) intelFallback( intel, bit, mode )
  92
  93
  94 #define INTEL_WRITE_PART  0x1
  95 #define INTEL_WRITE_FULL  0x2
  96 #define INTEL_READ        0x4
  97
  98 #define INTEL_MAX_FIXUP 64
  99
 100 #ifndef likely
 101 #ifdef __GNUC__
 102 #define likely(expr) (__builtin_expect(expr, 1))
 103 #define unlikely(expr) (__builtin_expect(expr, 0))
 104 #else
 105 #define likely(expr) (expr)
 106 #define unlikely(expr) (expr)
 107 #endif
 108 #endif
 109
 110 struct intel_sync_object {
 111    struct gl_sync_object Base;
 112
 113    /** Batch associated with this sync object */
 114    drm_intel_bo *bo;
 115 };
 116
 117 struct brw_context;
 118
 119 /**
 120  * intel_context is derived from Mesa's context class: struct gl_context.
 121  */
 122 struct intel_context
 123 {
 124    struct gl_context ctx;  /**< base class, must be first field */
 125
 126    struct
 127    {
 128       void (*destroy) (struct intel_context * intel);
 129       void (*emit_state) (struct intel_context * intel);
 130       void (*finish_batch) (struct intel_context * intel);
 131       void (*new_batch) (struct intel_context * intel);
 132       void (*emit_invarient_state) (struct intel_context * intel);
 133       void (*update_texture_state) (struct intel_context * intel);
 134
 135       void (*render_start) (struct intel_context * intel);
 136       void (*render_prevalidate) (struct intel_context * intel);
 137       void (*set_draw_region) (struct intel_context * intel,
 138                                struct intel_region * draw_regions[],
 139                                struct intel_region * depth_region,
 140                                GLuint num_regions);
 141       void (*update_draw_buffer)(struct intel_context *intel);
 142
 143       void (*reduced_primitive_state) (struct intel_context * intel,
 144                                        GLenum rprim);
 145
 146       bool (*check_vertex_size) (struct intel_context * intel,
 147                                       GLuint expected);
 148       void (*invalidate_state) (struct intel_context *intel,
 149                                 GLuint new_state);
 150
 151       void (*assert_not_dirty) (struct intel_context *intel);
 152
 153       void (*debug_batch)(struct intel_context *intel);
 154       bool (*render_target_supported)(struct intel_context *intel,
 155                                       gl_format format);
 156
 157       /** Can HiZ be enabled on a depthbuffer of the given format? */
 158       bool (*is_hiz_depth_format)(struct intel_context *intel,
 159                                   gl_format format);
 160
 161       /**
 162        * \name HiZ operations
 163        *
 164        * See the following sections of the Sandy Bridge PRM, Volume 1, Part2:
 165        *   - 7.5.3.1 Depth Buffer Clear
 166        *   - 7.5.3.2 Depth Buffer Resolve
 167        *   - 7.5.3.3 Hierarchical Depth Buffer Resolve
 168        * \{
 169        */
 170       void (*resolve_hiz_slice)(struct intel_context *intel,
 171                                 struct intel_mipmap_tree *mt,
 172                                 uint32_t level,
 173                                 uint32_t layer);
 174
 175       void (*resolve_depth_slice)(struct intel_context *intel,
 176                                   struct intel_mipmap_tree *mt,
 177                                   uint32_t level,
 178                                   uint32_t layer);
 179       /** \} */
 180
 181       /**
 182        * Surface state operations (i965+ only)
 183        * \{
 184        */
 185       void (*update_texture_surface)(struct gl_context *ctx, unsigned unit);
 186       void (*update_renderbuffer_surface)(struct brw_context *brw,
 187                                           struct gl_renderbuffer *rb,
 188                                           unsigned unit);
 189       void (*update_null_renderbuffer_surface)(struct brw_context *brw,
 190                                                unsigned unit);
 191       void (*create_constant_surface)(struct brw_context *brw,
 192                                       drm_intel_bo *bo,
 193                                       int width,
 194                                       uint32_t *out_offset);
 195       /** \} */
 196    } vtbl;
 197
 198    GLbitfield Fallback;  /**< mask of INTEL_FALLBACK_x bits */
 199    GLuint NewGLState;
 200
 201    dri_bufmgr *bufmgr;
 202    unsigned int maxBatchSize;
 203
 204    /**
 205     * Generation number of the hardware: 2 is 8xx, 3 is 9xx pre-965, 4 is 965.
 206     */
 207    int gen;
 208    int gt;
 209    bool needs_ff_sync;
 210    bool is_g4x;
 211    bool is_945;
 212    bool has_separate_stencil;
 213    bool must_use_separate_stencil;
 214    bool has_hiz;
 215
 216    int urb_size;
 217
 218    struct intel_batchbuffer {
 219       /** Current batchbuffer being queued up. */
 220       drm_intel_bo *bo;
 221       /** Last BO submitted to the hardware.  Used for glFinish(). */
 222       drm_intel_bo *last_bo;
 223       /** BO for post-sync nonzero writes for gen6 workaround. */
 224       drm_intel_bo *workaround_bo;
 225       bool need_workaround_flush;
 226
 227       struct cached_batch_item *cached_items;
 228
 229       uint16_t emit, total;
 230       uint16_t used, reserved_space;
 231       uint32_t map[8192];
 232 #define BATCH_SZ (8192*sizeof(uint32_t))
 233
 234       uint32_t state_batch_offset;
 235       bool is_blit;
 236
 237       struct {
 238          uint16_t used;
 239          int reloc_count;
 240       } saved;
 241    } batch;
 242
 243    drm_intel_bo *first_post_swapbuffers_batch;
 244    bool need_throttle;
 245    bool no_batch_wrap;
 246    bool tnl_pipeline_running; /**< Set while i915's _tnl_run_pipeline. */
 247
 248    struct
 249    {
 250       GLuint id;
 251       uint32_t start_ptr; /**< for i8xx */
 252       uint32_t primitive;       /**< Current hardware primitive type */
 253       void (*flush) (struct intel_context *);
 254       drm_intel_bo *vb_bo;
 255       uint8_t *vb;
 256       unsigned int start_offset; /**< Byte offset of primitive sequence */
 257       unsigned int current_offset; /**< Byte offset of next vertex */
 258       unsigned int count;       /**< Number of vertices in current primitive */
 259    } prim;
 260
 261    struct {
 262       drm_intel_bo *bo;
 263       GLuint offset;
 264       uint32_t buffer_len;
 265       uint32_t buffer_offset;
 266       char buffer[4096];
 267    } upload;
 268
 269    GLuint stats_wm;
 270
 271    /* Offsets of fields within the current vertex:
 272     */
 273    GLuint coloroffset;
 274    GLuint specoffset;
 275    GLuint wpos_offset;
 276
 277    struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
 278    GLuint vertex_attr_count;
 279
 280    GLfloat polygon_offset_scale;        /* dependent on depth_scale, bpp */
 281
 282    bool hw_stencil;
 283    bool hw_stipple;
 284    bool no_rast;
 285    bool always_flush_batch;
 286    bool always_flush_cache;
 287
 288    /* 0 - nonconformant, best performance;
 289     * 1 - fallback to sw for known conformance bugs
 290     * 2 - always fallback to sw
 291     */
 292    GLuint conformance_mode;
 293
 294    /* State for intelvb.c and inteltris.c.
 295     */
 296    GLuint RenderIndex;
 297    GLmatrix ViewportMatrix;
 298    GLenum render_primitive;
 299    GLenum reduced_primitive; /*< Only gen < 6 */
 300    GLuint vertex_size;
 301    GLubyte *verts;              /* points to tnl->clipspace.vertex_buf */
 302
 303    /* Fallback rasterization functions
 304     */
 305    intel_point_func draw_point;
 306    intel_line_func draw_line;
 307    intel_tri_func draw_tri;
 308
 309    /**
 310     * Set if rendering has occured to the drawable's front buffer.
 311     *
 312     * This is used in the DRI2 case to detect that glFlush should also copy
 313     * the contents of the fake front buffer to the real front buffer.
 314     */
 315    bool front_buffer_dirty;
 316
 317    /**
 318     * Track whether front-buffer rendering is currently enabled
 319     *
 320     * A separate flag is used to track this in order to support MRT more
 321     * easily.
 322     */
 323    bool is_front_buffer_rendering;
 324    /**
 325     * Track whether front-buffer is the current read target.
 326     *
 327     * This is closely associated with is_front_buffer_rendering, but may
 328     * be set separately.  The DRI2 fake front buffer must be referenced
 329     * either way.
 330     */
 331    bool is_front_buffer_reading;
 332
 333    /**
 334     * Count of intel_regions that are mapped.
 335     *
 336     * This allows us to assert that no batch buffer is emitted if a
 337     * region is mapped.
 338     */
 339    int num_mapped_regions;
 340
 341    bool use_texture_tiling;
 342    bool use_early_z;
 343
 344    int driFd;
 345
 346    __DRIcontext *driContext;
 347    struct intel_screen *intelScreen;
 348    void (*saved_viewport)(struct gl_context * ctx,
 349                           GLint x, GLint y, GLsizei width, GLsizei height);
 350
 351    /**
 352     * Configuration cache
 353     */
 354    driOptionCache optionCache;
 355 };
 356
 357 extern char *__progname;
 358
 359
 360 #define SUBPIXEL_X 0.125
 361 #define SUBPIXEL_Y 0.125
 362
 363 #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
 364
 365 /**
 366  * Align a value up to an alignment value
 367  *
 368  * If \c value is not already aligned to the requested alignment value, it
 369  * will be rounded up.
 370  *
 371  * \param value  Value to be rounded
 372  * \param alignment  Alignment value to be used.  This must be a power of two.
 373  *
 374  * \sa ROUND_DOWN_TO()
 375  */
 376 #define ALIGN(value, alignment)  (((value) + alignment - 1) & ~(alignment - 1))
 377
 378 /**
 379  * Align a value down to an alignment value
 380  *
 381  * If \c value is not already aligned to the requested alignment value, it
 382  * will be rounded down.
 383  *
 384  * \param value  Value to be rounded
 385  * \param alignment  Alignment value to be used.  This must be a power of two.
 386  *
 387  * \sa ALIGN()
 388  */
 389 #define ROUND_DOWN_TO(value, alignment) ((value) & ~(alignment - 1))
 390
 391 #define IS_POWER_OF_TWO(val) (((val) & (val - 1)) == 0)
 392
 393 static INLINE uint32_t
 394 U_FIXED(float value, uint32_t frac_bits)
 395 {
 396    value *= (1 << frac_bits);
 397    return value < 0 ? 0 : value;
 398 }
 399
 400 static INLINE uint32_t
 401 S_FIXED(float value, uint32_t frac_bits)
 402 {
 403    return value * (1 << frac_bits);
 404 }
 405
 406 #define INTEL_FIREVERTICES(intel)               \
 407 do {                                            \
 408    if ((intel)->prim.flush)                     \
 409       (intel)->prim.flush(intel);               \
 410 } while (0)
 411
 412 /* ================================================================
 413  * From linux kernel i386 header files, copes with odd sizes better
 414  * than COPY_DWORDS would:
 415  * XXX Put this in src/mesa/main/imports.h ???
 416  */
 417 #if defined(i386) || defined(__i386__)
 418 static INLINE void * __memcpy(void * to, const void * from, size_t n)
 419 {
 420    int d0, d1, d2;
 421    __asm__ __volatile__(
 422       "rep ; movsl\n\t"
 423       "testb $2,%b4\n\t"
 424       "je 1f\n\t"
 425       "movsw\n"
 426       "1:\ttestb $1,%b4\n\t"
 427       "je 2f\n\t"
 428       "movsb\n"
 429       "2:"
 430       : "=&c" (d0), "=&D" (d1), "=&S" (d2)
 431       :"0" (n/4), "q" (n),"1" ((long) to),"2" ((long) from)
 432       : "memory");
 433    return (to);
 434 }
 435 #else
 436 #define __memcpy(a,b,c) memcpy(a,b,c)
 437 #endif
 438
 439
 440 /* ================================================================
 441  * Debugging:
 442  */
 443 extern int INTEL_DEBUG;
 444
 445 #define DEBUG_TEXTURE   0x1
 446 #define DEBUG_STATE     0x2
 447 #define DEBUG_IOCTL     0x4
 448 #define DEBUG_BLIT      0x8
 449 #define DEBUG_MIPTREE   0x10
 450 #define DEBUG_FALLBACKS 0x20
 451 #define DEBUG_VERBOSE   0x40
 452 #define DEBUG_BATCH     0x80
 453 #define DEBUG_PIXEL     0x100
 454 #define DEBUG_BUFMGR    0x200
 455 #define DEBUG_REGION    0x400
 456 #define DEBUG_FBO       0x800
 457 #define DEBUG_GS        0x1000
 458 #define DEBUG_SYNC      0x2000
 459 #define DEBUG_PRIMS     0x4000
 460 #define DEBUG_VERTS     0x8000
 461 #define DEBUG_DRI       0x10000
 462 #define DEBUG_SF        0x20000
 463 #define DEBUG_SANITY    0x40000
 464 #define DEBUG_SLEEP     0x80000
 465 #define DEBUG_STATS     0x100000
 466 #define DEBUG_TILE      0x200000
 467 #define DEBUG_WM        0x400000
 468 #define DEBUG_URB       0x800000
 469 #define DEBUG_VS        0x1000000
 470 #define DEBUG_CLIP      0x2000000
 471
 472 #define DBG(...) do {                                           \
 473         if (unlikely(INTEL_DEBUG & FILE_DEBUG_FLAG))            \
 474                 printf(__VA_ARGS__);                    \
 475 } while(0)
 476
 477 #define fallback_debug(...) do {                                \
 478         if (unlikely(INTEL_DEBUG & DEBUG_FALLBACKS))            \
 479                 printf(__VA_ARGS__);                            \
 480 } while(0)
 481
 482 #define PCI_CHIP_845_G                  0x2562
 483 #define PCI_CHIP_I830_M                 0x3577
 484 #define PCI_CHIP_I855_GM                0x3582
 485 #define PCI_CHIP_I865_G                 0x2572
 486 #define PCI_CHIP_I915_G                 0x2582
 487 #define PCI_CHIP_I915_GM                0x2592
 488 #define PCI_CHIP_I945_G                 0x2772
 489 #define PCI_CHIP_I945_GM                0x27A2
 490 #define PCI_CHIP_I945_GME               0x27AE
 491 #define PCI_CHIP_G33_G                  0x29C2
 492 #define PCI_CHIP_Q35_G                  0x29B2
 493 #define PCI_CHIP_Q33_G                  0x29D2
 494
 495
 496 /* ================================================================
 497  * intel_context.c:
 498  */
 499
 500 extern bool intelInitContext(struct intel_context *intel,
 501                                   int api,
 502                                   const struct gl_config * mesaVis,
 503                                   __DRIcontext * driContextPriv,
 504                                   void *sharedContextPrivate,
 505                                   struct dd_function_table *functions);
 506
 507 extern void intelFinish(struct gl_context * ctx);
 508 extern void intel_flush_rendering_to_batch(struct gl_context *ctx);
 509 extern void _intel_flush(struct gl_context * ctx, const char *file, int line);
 510
 511 #define intel_flush(ctx) _intel_flush(ctx, __FILE__, __LINE__)
 512
 513 extern void intelInitDriverFunctions(struct dd_function_table *functions);
 514
 515 void intel_init_syncobj_functions(struct dd_function_table *functions);
 516
 517
 518 /* ================================================================
 519  * intel_state.c:
 520  */
 521 extern void intelInitStateFuncs(struct dd_function_table *functions);
 522
 523 #define COMPAREFUNC_ALWAYS              0
 524 #define COMPAREFUNC_NEVER               0x1
 525 #define COMPAREFUNC_LESS                0x2
 526 #define COMPAREFUNC_EQUAL               0x3
 527 #define COMPAREFUNC_LEQUAL              0x4
 528 #define COMPAREFUNC_GREATER             0x5
 529 #define COMPAREFUNC_NOTEQUAL            0x6
 530 #define COMPAREFUNC_GEQUAL              0x7
 531
 532 #define STENCILOP_KEEP                  0
 533 #define STENCILOP_ZERO                  0x1
 534 #define STENCILOP_REPLACE               0x2
 535 #define STENCILOP_INCRSAT               0x3
 536 #define STENCILOP_DECRSAT               0x4
 537 #define STENCILOP_INCR                  0x5
 538 #define STENCILOP_DECR                  0x6
 539 #define STENCILOP_INVERT                0x7
 540
 541 #define LOGICOP_CLEAR                   0
 542 #define LOGICOP_NOR                     0x1
 543 #define LOGICOP_AND_INV                 0x2
 544 #define LOGICOP_COPY_INV                0x3
 545 #define LOGICOP_AND_RVRSE               0x4
 546 #define LOGICOP_INV                     0x5
 547 #define LOGICOP_XOR                     0x6
 548 #define LOGICOP_NAND                    0x7
 549 #define LOGICOP_AND                     0x8
 550 #define LOGICOP_EQUIV                   0x9
 551 #define LOGICOP_NOOP                    0xa
 552 #define LOGICOP_OR_INV                  0xb
 553 #define LOGICOP_COPY                    0xc
 554 #define LOGICOP_OR_RVRSE                0xd
 555 #define LOGICOP_OR                      0xe
 556 #define LOGICOP_SET                     0xf
 557
 558 #define BLENDFACT_ZERO                  0x01
 559 #define BLENDFACT_ONE                   0x02
 560 #define BLENDFACT_SRC_COLR              0x03
 561 #define BLENDFACT_INV_SRC_COLR          0x04
 562 #define BLENDFACT_SRC_ALPHA             0x05
 563 #define BLENDFACT_INV_SRC_ALPHA         0x06
 564 #define BLENDFACT_DST_ALPHA             0x07
 565 #define BLENDFACT_INV_DST_ALPHA         0x08
 566 #define BLENDFACT_DST_COLR              0x09
 567 #define BLENDFACT_INV_DST_COLR          0x0a
 568 #define BLENDFACT_SRC_ALPHA_SATURATE    0x0b
 569 #define BLENDFACT_CONST_COLOR           0x0c
 570 #define BLENDFACT_INV_CONST_COLOR       0x0d
 571 #define BLENDFACT_CONST_ALPHA           0x0e
 572 #define BLENDFACT_INV_CONST_ALPHA       0x0f
 573 #define BLENDFACT_MASK                  0x0f
 574
 575 enum {
 576    DRI_CONF_BO_REUSE_DISABLED,
 577    DRI_CONF_BO_REUSE_ALL
 578 };
 579
 580 extern int intel_translate_shadow_compare_func(GLenum func);
 581 extern int intel_translate_compare_func(GLenum func);
 582 extern int intel_translate_stencil_op(GLenum op);
 583 extern int intel_translate_blend_factor(GLenum factor);
 584 extern int intel_translate_logic_op(GLenum opcode);
 585
 586 void intel_update_renderbuffers(__DRIcontext *context,
 587                                 __DRIdrawable *drawable);
 588 void intel_prepare_render(struct intel_context *intel);
 589
 590 void i915_set_buf_info_for_region(uint32_t *state, struct intel_region *region,
 591                                   uint32_t buffer_id);
 592 void intel_init_texture_formats(struct gl_context *ctx);
 593
 594 /*======================================================================
 595  * Inline conversion functions.
 596  * These are better-typed than the macros used previously:
 597  */
 598 static INLINE struct intel_context *
 599 intel_context(struct gl_context * ctx)
 600 {
 601    return (struct intel_context *) ctx;
 602 }
 603
 604 static INLINE bool
 605 is_power_of_two(uint32_t value)
 606 {
 607    return (value & (value - 1)) == 0;
 608 }
 609
 610 #endif