1 /**************************************************************************
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #ifndef INTELCONTEXT_INC
29 #define INTELCONTEXT_INC
34 #include "main/mtypes.h"
39 /* Evil hack for using libdrm in a c++ compiler. */
44 #include "intel_bufmgr.h"
46 #include "intel_screen.h"
47 #include "intel_tex_obj.h"
54 #include "tnl/t_vertex.h"
56 #define TAG(x) intel##x
57 #include "tnl_dd/t_dd_vertex.h"
60 #define DV_PF_555 (1<<8)
61 #define DV_PF_565 (2<<8)
62 #define DV_PF_8888 (3<<8)
63 #define DV_PF_4444 (8<<8)
64 #define DV_PF_1555 (9<<8)
69 typedef void (*intel_tri_func
) (struct intel_context
*, intelVertex
*,
70 intelVertex
*, intelVertex
*);
71 typedef void (*intel_line_func
) (struct intel_context
*, intelVertex
*,
73 typedef void (*intel_point_func
) (struct intel_context
*, intelVertex
*);
76 * Bits for intel->Fallback field
79 #define INTEL_FALLBACK_DRAW_BUFFER 0x1
80 #define INTEL_FALLBACK_READ_BUFFER 0x2
81 #define INTEL_FALLBACK_DEPTH_BUFFER 0x4
82 #define INTEL_FALLBACK_STENCIL_BUFFER 0x8
83 #define INTEL_FALLBACK_USER 0x10
84 #define INTEL_FALLBACK_RENDERMODE 0x20
85 #define INTEL_FALLBACK_TEXTURE 0x40
86 #define INTEL_FALLBACK_DRIVER 0x1000 /**< first for drivers */
89 extern void intelFallback(struct intel_context
*intel
, GLbitfield bit
,
91 #define FALLBACK( intel, bit, mode ) intelFallback( intel, bit, mode )
94 #define INTEL_WRITE_PART 0x1
95 #define INTEL_WRITE_FULL 0x2
96 #define INTEL_READ 0x4
98 #define INTEL_MAX_FIXUP 64
102 #define likely(expr) (__builtin_expect(expr, 1))
103 #define unlikely(expr) (__builtin_expect(expr, 0))
105 #define likely(expr) (expr)
106 #define unlikely(expr) (expr)
110 struct intel_sync_object
{
111 struct gl_sync_object Base
;
113 /** Batch associated with this sync object */
119 struct intel_batchbuffer
{
120 /** Current batchbuffer being queued up. */
122 /** Last BO submitted to the hardware. Used for glFinish(). */
123 drm_intel_bo
*last_bo
;
124 /** BO for post-sync nonzero writes for gen6 workaround. */
125 drm_intel_bo
*workaround_bo
;
126 bool need_workaround_flush
;
128 struct cached_batch_item
*cached_items
;
130 uint16_t emit
, total
;
131 uint16_t used
, reserved_space
;
134 #define BATCH_SZ (8192*sizeof(uint32_t))
136 uint32_t state_batch_offset
;
138 bool needs_sol_reset
;
147 * intel_context is derived from Mesa's context class: struct gl_context.
151 struct gl_context ctx
; /**< base class, must be first field */
155 void (*destroy
) (struct intel_context
* intel
);
156 void (*emit_state
) (struct intel_context
* intel
);
157 void (*finish_batch
) (struct intel_context
* intel
);
158 void (*new_batch
) (struct intel_context
* intel
);
159 void (*emit_invarient_state
) (struct intel_context
* intel
);
160 void (*update_texture_state
) (struct intel_context
* intel
);
162 void (*render_start
) (struct intel_context
* intel
);
163 void (*render_prevalidate
) (struct intel_context
* intel
);
164 void (*set_draw_region
) (struct intel_context
* intel
,
165 struct intel_region
* draw_regions
[],
166 struct intel_region
* depth_region
,
168 void (*update_draw_buffer
)(struct intel_context
*intel
);
170 void (*reduced_primitive_state
) (struct intel_context
* intel
,
173 bool (*check_vertex_size
) (struct intel_context
* intel
,
175 void (*invalidate_state
) (struct intel_context
*intel
,
178 void (*assert_not_dirty
) (struct intel_context
*intel
);
180 void (*debug_batch
)(struct intel_context
*intel
);
181 void (*annotate_aub
)(struct intel_context
*intel
);
182 bool (*render_target_supported
)(struct intel_context
*intel
,
183 struct gl_renderbuffer
*rb
);
185 /** Can HiZ be enabled on a depthbuffer of the given format? */
186 bool (*is_hiz_depth_format
)(struct intel_context
*intel
,
190 * Surface state operations (i965+ only)
193 void (*update_texture_surface
)(struct gl_context
*ctx
,
195 uint32_t *binding_table
,
196 unsigned surf_index
);
197 void (*update_renderbuffer_surface
)(struct brw_context
*brw
,
198 struct gl_renderbuffer
*rb
,
200 void (*update_null_renderbuffer_surface
)(struct brw_context
*brw
,
202 void (*create_constant_surface
)(struct brw_context
*brw
,
206 uint32_t *out_offset
);
210 GLbitfield Fallback
; /**< mask of INTEL_FALLBACK_x bits */
214 unsigned int maxBatchSize
;
217 * Generation number of the hardware: 2 is 8xx, 3 is 9xx pre-965, 4 is 965.
225 bool has_separate_stencil
;
226 bool must_use_separate_stencil
;
233 drm_intel_context
*hw_ctx
;
235 struct intel_batchbuffer batch
;
237 drm_intel_bo
*first_post_swapbuffers_batch
;
240 bool tnl_pipeline_running
; /**< Set while i915's _tnl_run_pipeline. */
245 uint32_t start_ptr
; /**< for i8xx */
246 uint32_t primitive
; /**< Current hardware primitive type */
247 void (*flush
) (struct intel_context
*);
250 unsigned int start_offset
; /**< Byte offset of primitive sequence */
251 unsigned int current_offset
; /**< Byte offset of next vertex */
252 unsigned int count
; /**< Number of vertices in current primitive */
259 uint32_t buffer_offset
;
265 /* Offsets of fields within the current vertex:
271 struct tnl_attr_map vertex_attrs
[VERT_ATTRIB_MAX
];
272 GLuint vertex_attr_count
;
274 GLfloat polygon_offset_scale
; /* dependent on depth_scale, bpp */
279 bool always_flush_batch
;
280 bool always_flush_cache
;
282 /* State for intelvb.c and inteltris.c.
285 GLmatrix ViewportMatrix
;
286 GLenum render_primitive
;
287 GLenum reduced_primitive
; /*< Only gen < 6 */
289 GLubyte
*verts
; /* points to tnl->clipspace.vertex_buf */
291 /* Fallback rasterization functions
293 intel_point_func draw_point
;
294 intel_line_func draw_line
;
295 intel_tri_func draw_tri
;
298 * Set if rendering has occured to the drawable's front buffer.
300 * This is used in the DRI2 case to detect that glFlush should also copy
301 * the contents of the fake front buffer to the real front buffer.
303 bool front_buffer_dirty
;
306 * Track whether front-buffer rendering is currently enabled
308 * A separate flag is used to track this in order to support MRT more
311 bool is_front_buffer_rendering
;
313 * Track whether front-buffer is the current read target.
315 * This is closely associated with is_front_buffer_rendering, but may
316 * be set separately. The DRI2 fake front buffer must be referenced
319 bool is_front_buffer_reading
;
322 * Count of intel_regions that are mapped.
324 * This allows us to assert that no batch buffer is emitted if a
327 int num_mapped_regions
;
329 bool use_texture_tiling
;
334 __DRIcontext
*driContext
;
335 struct intel_screen
*intelScreen
;
336 void (*saved_viewport
)(struct gl_context
* ctx
,
337 GLint x
, GLint y
, GLsizei width
, GLsizei height
);
340 * Configuration cache
342 driOptionCache optionCache
;
345 extern char *__progname
;
348 #define SUBPIXEL_X 0.125
349 #define SUBPIXEL_Y 0.125
352 * Align a value down to an alignment value
354 * If \c value is not already aligned to the requested alignment value, it
355 * will be rounded down.
357 * \param value Value to be rounded
358 * \param alignment Alignment value to be used. This must be a power of two.
362 #define ROUND_DOWN_TO(value, alignment) ((value) & ~(alignment - 1))
364 #define IS_POWER_OF_TWO(val) (((val) & (val - 1)) == 0)
366 static INLINE
uint32_t
367 U_FIXED(float value
, uint32_t frac_bits
)
369 value
*= (1 << frac_bits
);
370 return value
< 0 ? 0 : value
;
373 static INLINE
uint32_t
374 S_FIXED(float value
, uint32_t frac_bits
)
376 return value
* (1 << frac_bits
);
379 #define INTEL_FIREVERTICES(intel) \
381 if ((intel)->prim.flush) \
382 (intel)->prim.flush(intel); \
385 /* ================================================================
386 * From linux kernel i386 header files, copes with odd sizes better
387 * than COPY_DWORDS would:
388 * XXX Put this in src/mesa/main/imports.h ???
390 #if defined(i386) || defined(__i386__)
391 static INLINE
void * __memcpy(void * to
, const void * from
, size_t n
)
394 __asm__
__volatile__(
399 "1:\ttestb $1,%b4\n\t"
403 : "=&c" (d0
), "=&D" (d1
), "=&S" (d2
)
404 :"0" (n
/4), "q" (n
),"1" ((long) to
),"2" ((long) from
)
409 #define __memcpy(a,b,c) memcpy(a,b,c)
413 /* ================================================================
416 extern int INTEL_DEBUG
;
418 #define DEBUG_TEXTURE 0x1
419 #define DEBUG_STATE 0x2
420 #define DEBUG_IOCTL 0x4
421 #define DEBUG_BLIT 0x8
422 #define DEBUG_MIPTREE 0x10
423 #define DEBUG_PERF 0x20
424 #define DEBUG_VERBOSE 0x40
425 #define DEBUG_BATCH 0x80
426 #define DEBUG_PIXEL 0x100
427 #define DEBUG_BUFMGR 0x200
428 #define DEBUG_REGION 0x400
429 #define DEBUG_FBO 0x800
430 #define DEBUG_GS 0x1000
431 #define DEBUG_SYNC 0x2000
432 #define DEBUG_PRIMS 0x4000
433 #define DEBUG_VERTS 0x8000
434 #define DEBUG_DRI 0x10000
435 #define DEBUG_SF 0x20000
436 #define DEBUG_SANITY 0x40000
437 #define DEBUG_SLEEP 0x80000
438 #define DEBUG_STATS 0x100000
439 #define DEBUG_TILE 0x200000
440 #define DEBUG_WM 0x400000
441 #define DEBUG_URB 0x800000
442 #define DEBUG_VS 0x1000000
443 #define DEBUG_CLIP 0x2000000
444 #define DEBUG_AUB 0x4000000
445 #define DEBUG_SHADER_TIME 0x8000000
446 #define DEBUG_NO16 0x20000000
448 #ifdef HAVE_ANDROID_PLATFORM
449 #define LOG_TAG "INTEL-MESA"
450 #include <cutils/log.h>
454 #define dbg_printf(...) ALOGW(__VA_ARGS__)
456 #define dbg_printf(...) printf(__VA_ARGS__)
457 #endif /* HAVE_ANDROID_PLATFORM */
459 #define DBG(...) do { \
460 if (unlikely(INTEL_DEBUG & FILE_DEBUG_FLAG)) \
461 dbg_printf(__VA_ARGS__); \
464 #define perf_debug(...) do { \
465 if (unlikely(INTEL_DEBUG & DEBUG_PERF)) \
466 dbg_printf(__VA_ARGS__); \
469 #define WARN_ONCE(cond, fmt...) do { \
470 if (unlikely(cond)) { \
471 static bool _warned = false; \
472 static GLuint msg_id = 0; \
474 fprintf(stderr, "WARNING: "); \
475 fprintf(stderr, fmt); \
478 _mesa_gl_debug(ctx, &msg_id, \
479 MESA_DEBUG_TYPE_OTHER, \
480 MESA_DEBUG_SEVERITY_HIGH, fmt); \
485 #define PCI_CHIP_845_G 0x2562
486 #define PCI_CHIP_I830_M 0x3577
487 #define PCI_CHIP_I855_GM 0x3582
488 #define PCI_CHIP_I865_G 0x2572
489 #define PCI_CHIP_I915_G 0x2582
490 #define PCI_CHIP_I915_GM 0x2592
491 #define PCI_CHIP_I945_G 0x2772
492 #define PCI_CHIP_I945_GM 0x27A2
493 #define PCI_CHIP_I945_GME 0x27AE
494 #define PCI_CHIP_G33_G 0x29C2
495 #define PCI_CHIP_Q35_G 0x29B2
496 #define PCI_CHIP_Q33_G 0x29D2
499 /* ================================================================
503 extern bool intelInitContext(struct intel_context
*intel
,
505 unsigned major_version
,
506 unsigned minor_version
,
507 const struct gl_config
* mesaVis
,
508 __DRIcontext
* driContextPriv
,
509 void *sharedContextPrivate
,
510 struct dd_function_table
*functions
,
511 unsigned *dri_ctx_error
);
513 extern void intelFinish(struct gl_context
* ctx
);
514 extern void intel_flush_rendering_to_batch(struct gl_context
*ctx
);
515 extern void _intel_flush(struct gl_context
* ctx
, const char *file
, int line
);
517 #define intel_flush(ctx) _intel_flush(ctx, __FILE__, __LINE__)
519 extern void intelInitDriverFunctions(struct dd_function_table
*functions
);
521 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
524 /* ================================================================
528 #define COMPAREFUNC_ALWAYS 0
529 #define COMPAREFUNC_NEVER 0x1
530 #define COMPAREFUNC_LESS 0x2
531 #define COMPAREFUNC_EQUAL 0x3
532 #define COMPAREFUNC_LEQUAL 0x4
533 #define COMPAREFUNC_GREATER 0x5
534 #define COMPAREFUNC_NOTEQUAL 0x6
535 #define COMPAREFUNC_GEQUAL 0x7
537 #define STENCILOP_KEEP 0
538 #define STENCILOP_ZERO 0x1
539 #define STENCILOP_REPLACE 0x2
540 #define STENCILOP_INCRSAT 0x3
541 #define STENCILOP_DECRSAT 0x4
542 #define STENCILOP_INCR 0x5
543 #define STENCILOP_DECR 0x6
544 #define STENCILOP_INVERT 0x7
546 #define LOGICOP_CLEAR 0
547 #define LOGICOP_NOR 0x1
548 #define LOGICOP_AND_INV 0x2
549 #define LOGICOP_COPY_INV 0x3
550 #define LOGICOP_AND_RVRSE 0x4
551 #define LOGICOP_INV 0x5
552 #define LOGICOP_XOR 0x6
553 #define LOGICOP_NAND 0x7
554 #define LOGICOP_AND 0x8
555 #define LOGICOP_EQUIV 0x9
556 #define LOGICOP_NOOP 0xa
557 #define LOGICOP_OR_INV 0xb
558 #define LOGICOP_COPY 0xc
559 #define LOGICOP_OR_RVRSE 0xd
560 #define LOGICOP_OR 0xe
561 #define LOGICOP_SET 0xf
563 #define BLENDFACT_ZERO 0x01
564 #define BLENDFACT_ONE 0x02
565 #define BLENDFACT_SRC_COLR 0x03
566 #define BLENDFACT_INV_SRC_COLR 0x04
567 #define BLENDFACT_SRC_ALPHA 0x05
568 #define BLENDFACT_INV_SRC_ALPHA 0x06
569 #define BLENDFACT_DST_ALPHA 0x07
570 #define BLENDFACT_INV_DST_ALPHA 0x08
571 #define BLENDFACT_DST_COLR 0x09
572 #define BLENDFACT_INV_DST_COLR 0x0a
573 #define BLENDFACT_SRC_ALPHA_SATURATE 0x0b
574 #define BLENDFACT_CONST_COLOR 0x0c
575 #define BLENDFACT_INV_CONST_COLOR 0x0d
576 #define BLENDFACT_CONST_ALPHA 0x0e
577 #define BLENDFACT_INV_CONST_ALPHA 0x0f
578 #define BLENDFACT_MASK 0x0f
581 DRI_CONF_BO_REUSE_DISABLED
,
582 DRI_CONF_BO_REUSE_ALL
585 extern int intel_translate_shadow_compare_func(GLenum func
);
586 extern int intel_translate_compare_func(GLenum func
);
587 extern int intel_translate_stencil_op(GLenum op
);
588 extern int intel_translate_blend_factor(GLenum factor
);
589 extern int intel_translate_logic_op(GLenum opcode
);
591 void intel_update_renderbuffers(__DRIcontext
*context
,
592 __DRIdrawable
*drawable
);
593 void intel_prepare_render(struct intel_context
*intel
);
596 intel_downsample_for_dri2_flush(struct intel_context
*intel
,
597 __DRIdrawable
*drawable
);
599 void i915_set_buf_info_for_region(uint32_t *state
, struct intel_region
*region
,
601 void intel_init_texture_formats(struct gl_context
*ctx
);
603 /*======================================================================
604 * Inline conversion functions.
605 * These are better-typed than the macros used previously:
607 static INLINE
struct intel_context
*
608 intel_context(struct gl_context
* ctx
)
610 return (struct intel_context
*) ctx
;
614 is_power_of_two(uint32_t value
)
616 return (value
& (value
- 1)) == 0;