1 /**************************************************************************
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
36 #include "swrast/swrast.h"
38 #include "intel_context.h"
39 #include "intel_ioctl.h"
40 #include "intel_batchbuffer.h"
41 #include "intel_blit.h"
42 #include "intel_regions.h"
46 #include "intel_bufmgr_ttm.h"
48 #define FILE_DEBUG_FLAG DEBUG_IOCTL
51 intelEmitIrqLocked(struct intel_context
*intel
)
60 assert(((*(int *)intel->driHwLock) & ~DRM_LOCK_CONT) ==
61 (DRM_LOCK_HELD|intel->hHWContext));
66 ret
= drmCommandWriteRead(intel
->driFd
, DRM_I830_IRQ_EMIT
, &ie
, sizeof(ie
));
68 fprintf(stderr
, "%s: drmI830IrqEmit: %d\n", __FUNCTION__
, ret
);
72 DBG("%s --> %d\n", __FUNCTION__
, seq
);
78 intelWaitIrq(struct intel_context
*intel
, int seq
)
80 drm_i915_irq_wait_t iw
;
81 int ret
, lastdispatch
;
82 volatile drmI830Sarea
*sarea
= intel
->sarea
;
87 DBG("%s %d\n", __FUNCTION__
, seq
);
92 lastdispatch
= sarea
->last_dispatch
;
93 ret
= drmCommandWrite(intel
->driFd
, DRM_I830_IRQ_WAIT
, &iw
, sizeof(iw
));
94 } while (ret
== -EAGAIN
||
96 (ret
== -EBUSY
&& lastdispatch
!= sarea
->last_dispatch
) ||
97 (ret
== 0 && seq
> sarea
->last_dispatch
) ||
98 (ret
== 0 && sarea
->last_dispatch
- seq
>= (1 << 24)));
101 fprintf(stderr
, "%s: drmI830IrqWait: %d\n", __FUNCTION__
, ret
);
108 intel_batch_ioctl(struct intel_context
*intel
,
111 GLboolean ignore_cliprects
, GLboolean allow_unlock
)
113 drmI830BatchBuffer batch
;
118 assert(intel
->locked
);
121 DBG("%s used %d offset %x..%x ignore_cliprects %d\n",
123 used
, start_offset
, start_offset
+ used
, ignore_cliprects
);
125 /* Throw away non-effective packets. Won't work once we have
126 * hardware contexts which would preserve statechanges beyond a
129 batch
.start
= start_offset
;
131 batch
.cliprects
= intel
->pClipRects
;
132 batch
.num_cliprects
= ignore_cliprects
? 0 : intel
->numClipRects
;
134 batch
.DR4
= ((((GLuint
) intel
->drawX
) & 0xffff) |
135 (((GLuint
) intel
->drawY
) << 16));
137 DBG("%s: 0x%x..0x%x DR4: %x cliprects: %d\n",
140 batch
.start
+ batch
.used
* 4, batch
.DR4
, batch
.num_cliprects
);
142 if (drmCommandWrite(intel
->driFd
, DRM_I830_BATCHBUFFER
, &batch
,
144 fprintf(stderr
, "DRM_I830_BATCHBUFFER: %d\n", -errno
);
145 UNLOCK_HARDWARE(intel
);
151 intel_exec_ioctl(struct intel_context
*intel
,
153 GLboolean ignore_cliprects
, GLboolean allow_unlock
,
154 void *start
, GLuint count
, dri_fence
**fence
)
156 struct drm_i915_execbuffer execbuf
;
159 assert(intel
->locked
);
166 dri_fence_unreference(*fence
);
169 memset(&execbuf
, 0, sizeof(execbuf
));
171 execbuf
.num_buffers
= count
;
172 execbuf
.batch
.used
= used
;
173 execbuf
.batch
.cliprects
= intel
->pClipRects
;
174 execbuf
.batch
.num_cliprects
= ignore_cliprects
? 0 : intel
->numClipRects
;
175 execbuf
.batch
.DR1
= 0;
176 execbuf
.batch
.DR4
= ((((GLuint
) intel
->drawX
) & 0xffff) |
177 (((GLuint
) intel
->drawY
) << 16));
179 execbuf
.ops_list
= (unsigned long)start
; // TODO
180 execbuf
.fence_arg
.flags
= DRM_FENCE_FLAG_SHAREABLE
| DRM_I915_FENCE_FLAG_FLUSHED
;
182 if (drmCommandWriteRead(intel
->driFd
, DRM_I915_EXECBUFFER
, &execbuf
,
184 fprintf(stderr
, "DRM_I830_EXECBUFFER: %d\n", -errno
);
185 UNLOCK_HARDWARE(intel
);
190 fo
= intel_ttm_fence_create_from_arg(intel
->bufmgr
, "fence buffers",
193 fprintf(stderr
, "failed to fence handle: %08x\n", execbuf
.fence_arg
.handle
);
194 UNLOCK_HARDWARE(intel
);