src/mesa/drivers/dri/intel/intel_ioctl.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29 #include <stdio.h>
  30 #include <unistd.h>
  31 #include <errno.h>
  32 #include <sched.h>
  33
  34 #include "mtypes.h"
  35 #include "context.h"
  36 #include "swrast/swrast.h"
  37
  38 #include "intel_context.h"
  39 #include "intel_ioctl.h"
  40 #include "intel_batchbuffer.h"
  41 #include "intel_blit.h"
  42 #include "intel_regions.h"
  43 #include "drm.h"
  44 #include "i915_drm.h"
  45
  46 #include "intel_bufmgr_ttm.h"
  47
  48 #define FILE_DEBUG_FLAG DEBUG_IOCTL
  49
  50 int
  51 intelEmitIrqLocked(struct intel_context *intel)
  52 {
  53    struct drm_i915_irq_emit ie;
  54    int ret, seq = 1;
  55
  56    if (intel->no_hw)
  57       return 1;
  58
  59    /*
  60      assert(((*(int *)intel->driHwLock) & ~DRM_LOCK_CONT) ==
  61      (DRM_LOCK_HELD|intel->hHWContext));
  62    */
  63
  64    ie.irq_seq = &seq;
  65
  66    ret = drmCommandWriteRead(intel->driFd, DRM_I915_IRQ_EMIT, &ie, sizeof(ie));
  67    if (ret) {
  68       fprintf(stderr, "%s: drm_i915_irq_emit: %d\n", __FUNCTION__, ret);
  69       exit(1);
  70    }
  71
  72    DBG("%s -->  %d\n", __FUNCTION__, seq);
  73
  74    return seq;
  75 }
  76
  77 void
  78 intelWaitIrq(struct intel_context *intel, int seq)
  79 {
  80    struct drm_i915_irq_wait iw;
  81    int ret, lastdispatch;
  82    volatile struct drm_i915_sarea *sarea = intel->sarea;
  83
  84    if (intel->no_hw)
  85       return;
  86
  87    DBG("%s %d\n", __FUNCTION__, seq);
  88
  89    iw.irq_seq = seq;
  90
  91    do {
  92       lastdispatch = sarea->last_dispatch;
  93       ret = drmCommandWrite(intel->driFd, DRM_I915_IRQ_WAIT, &iw, sizeof(iw));
  94    } while (ret == -EAGAIN ||
  95             ret == -EINTR ||
  96             (ret == -EBUSY && lastdispatch != sarea->last_dispatch) ||
  97             (ret == 0 && seq > sarea->last_dispatch) ||
  98             (ret == 0 && sarea->last_dispatch - seq >= (1 << 24)));
  99
 100    if (ret) {
 101       fprintf(stderr, "%s: drm_i915_irq_wait: %d\n", __FUNCTION__, ret);
 102       exit(1);
 103    }
 104 }
 105
 106
 107 void
 108 intel_batch_ioctl(struct intel_context *intel,
 109                   GLuint start_offset,
 110                   GLuint used,
 111                   GLboolean ignore_cliprects, GLboolean allow_unlock)
 112 {
 113    struct drm_i915_batchbuffer batch;
 114
 115    if (intel->no_hw)
 116       return;
 117
 118    assert(intel->locked);
 119    assert(used);
 120
 121    DBG("%s used %d offset %x..%x ignore_cliprects %d\n",
 122        __FUNCTION__,
 123        used, start_offset, start_offset + used, ignore_cliprects);
 124
 125    /* Throw away non-effective packets.  Won't work once we have
 126     * hardware contexts which would preserve statechanges beyond a
 127     * single buffer.
 128     */
 129    batch.start = start_offset;
 130    batch.used = used;
 131    batch.cliprects = intel->pClipRects;
 132    batch.num_cliprects = ignore_cliprects ? 0 : intel->numClipRects;
 133    batch.DR1 = 0;
 134    batch.DR4 = ((((GLuint) intel->drawX) & 0xffff) |
 135                 (((GLuint) intel->drawY) << 16));
 136
 137    DBG("%s: 0x%x..0x%x DR4: %x cliprects: %d\n",
 138        __FUNCTION__,
 139        batch.start,
 140        batch.start + batch.used * 4, batch.DR4, batch.num_cliprects);
 141
 142    if (drmCommandWrite(intel->driFd, DRM_I915_BATCHBUFFER, &batch,
 143                        sizeof(batch))) {
 144       fprintf(stderr, "DRM_I915_BATCHBUFFER: %d\n", -errno);
 145       UNLOCK_HARDWARE(intel);
 146       exit(1);
 147    }
 148 }
 149
 150 void
 151 intel_exec_ioctl(struct intel_context *intel,
 152                  GLuint used,
 153                  GLboolean ignore_cliprects, GLboolean allow_unlock,
 154                  void *start, GLuint count, dri_fence **fence)
 155 {
 156    struct drm_i915_execbuffer execbuf;
 157    dri_fence *fo;
 158    int ret;
 159
 160    assert(intel->locked);
 161    assert(used);
 162
 163    if (intel->no_hw)
 164       return;
 165
 166    if (*fence) {
 167      dri_fence_unreference(*fence);
 168    }
 169
 170    memset(&execbuf, 0, sizeof(execbuf));
 171
 172    execbuf.num_buffers = count;
 173    execbuf.batch.used = used;
 174    execbuf.batch.cliprects = intel->pClipRects;
 175    execbuf.batch.num_cliprects = ignore_cliprects ? 0 : intel->numClipRects;
 176    execbuf.batch.DR1 = 0;
 177    execbuf.batch.DR4 = ((((GLuint) intel->drawX) & 0xffff) |
 178                         (((GLuint) intel->drawY) << 16));
 179
 180    execbuf.ops_list = (unsigned long)start; // TODO
 181    execbuf.fence_arg.flags = DRM_FENCE_FLAG_SHAREABLE | DRM_I915_FENCE_FLAG_FLUSHED;
 182
 183    do {
 184       ret = drmCommandWriteRead(intel->driFd, DRM_I915_EXECBUFFER, &execbuf,
 185                                 sizeof(execbuf));
 186    } while (ret == -EAGAIN);
 187
 188    if (ret != 0) {
 189       fprintf(stderr, "DRM_I915_EXECBUFFER: %d\n", -errno);
 190       UNLOCK_HARDWARE(intel);
 191       exit(1);
 192    }
 193
 194    if (execbuf.fence_arg.error != 0) {
 195
 196       /*
 197        * Fence creation has failed, but the GPU has been
 198        * idled by the kernel. Safe to continue.
 199        */
 200
 201       *fence = NULL;
 202       return;
 203    }
 204
 205    fo = intel_ttm_fence_create_from_arg(intel->bufmgr, "fence buffers",
 206                                         &execbuf.fence_arg);
 207    if (!fo) {
 208       fprintf(stderr, "failed to fence handle: %08x\n", execbuf.fence_arg.handle);
 209       UNLOCK_HARDWARE(intel);
 210       exit(1);
 211    }
 212    *fence = fo;
 213 }