1 /**************************************************************************
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include <GL/internal/dri_interface.h>
31 #include "intel_batchbuffer.h"
32 #include "intel_chipset.h"
33 #include "intel_context.h"
34 #include "intel_mipmap_tree.h"
35 #include "intel_regions.h"
36 #include "intel_resolve_map.h"
37 #include "intel_tex_layout.h"
38 #include "intel_tex.h"
39 #include "intel_blit.h"
42 #include "brw_blorp.h"
45 #include "main/enums.h"
46 #include "main/formats.h"
47 #include "main/glformats.h"
48 #include "main/texcompress_etc.h"
49 #include "main/teximage.h"
51 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
54 target_to_target(GLenum target
)
57 case GL_TEXTURE_CUBE_MAP_POSITIVE_X_ARB
:
58 case GL_TEXTURE_CUBE_MAP_NEGATIVE_X_ARB
:
59 case GL_TEXTURE_CUBE_MAP_POSITIVE_Y_ARB
:
60 case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y_ARB
:
61 case GL_TEXTURE_CUBE_MAP_POSITIVE_Z_ARB
:
62 case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z_ARB
:
63 return GL_TEXTURE_CUBE_MAP_ARB
;
71 * Determine which MSAA layout should be used by the MSAA surface being
72 * created, based on the chip generation and the surface type.
74 static enum intel_msaa_layout
75 compute_msaa_layout(struct intel_context
*intel
, gl_format format
, GLenum target
)
77 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
79 return INTEL_MSAA_LAYOUT_IMS
;
81 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
82 switch (_mesa_get_format_base_format(format
)) {
83 case GL_DEPTH_COMPONENT
:
84 case GL_STENCIL_INDEX
:
85 case GL_DEPTH_STENCIL
:
86 return INTEL_MSAA_LAYOUT_IMS
;
88 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
90 * This field must be set to 0 for all SINT MSRTs when all RT channels
93 * In practice this means that we have to disable MCS for all signed
94 * integer MSAA buffers. The alternative, to disable MCS only when one
95 * of the render target channels is disabled, is impractical because it
96 * would require converting between CMS and UMS MSAA layouts on the fly,
99 if (_mesa_get_format_datatype(format
) == GL_INT
) {
100 /* TODO: is this workaround needed for future chipsets? */
101 assert(intel
->gen
== 7);
102 return INTEL_MSAA_LAYOUT_UMS
;
104 /* For now, if we're going to be texturing from this surface,
105 * force UMS, so that the shader doesn't have to do different things
106 * based on whether there's a multisample control surface needing sampled first.
107 * We can't just blindly read the MCS surface in all cases because:
109 * From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
111 * If this field is disabled and the sampling engine <ld_mcs> message
112 * is issued on this surface, the MCS surface may be accessed. Software
113 * must ensure that the surface is defined to avoid GTT errors.
115 if (target
== GL_TEXTURE_2D_MULTISAMPLE
||
116 target
== GL_TEXTURE_2D_MULTISAMPLE_ARRAY
) {
117 return INTEL_MSAA_LAYOUT_UMS
;
119 return INTEL_MSAA_LAYOUT_CMS
;
127 * @param for_bo Indicates that the caller is
128 * intel_miptree_create_for_bo(). If true, then do not create
131 struct intel_mipmap_tree
*
132 intel_miptree_create_layout(struct intel_context
*intel
,
143 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
145 DBG("%s target %s format %s level %d..%d <-- %p\n", __FUNCTION__
,
146 _mesa_lookup_enum_by_nr(target
),
147 _mesa_get_format_name(format
),
148 first_level
, last_level
, mt
);
150 mt
->target
= target_to_target(target
);
152 mt
->first_level
= first_level
;
153 mt
->last_level
= last_level
;
154 mt
->logical_width0
= width0
;
155 mt
->logical_height0
= height0
;
156 mt
->logical_depth0
= depth0
;
158 /* The cpp is bytes per (1, blockheight)-sized block for compressed
159 * textures. This is why you'll see divides by blockheight all over
162 _mesa_get_format_block_size(format
, &bw
, &bh
);
163 assert(_mesa_get_format_bytes(mt
->format
) % bw
== 0);
164 mt
->cpp
= _mesa_get_format_bytes(mt
->format
) / bw
;
166 mt
->num_samples
= num_samples
;
167 mt
->compressed
= _mesa_is_format_compressed(format
);
168 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
171 if (num_samples
> 1) {
172 /* Adjust width/height/depth for MSAA */
173 mt
->msaa_layout
= compute_msaa_layout(intel
, format
, mt
->target
);
174 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
175 /* In the Sandy Bridge PRM, volume 4, part 1, page 31, it says:
177 * "Any of the other messages (sample*, LOD, load4) used with a
178 * (4x) multisampled surface will in-effect sample a surface with
179 * double the height and width as that indicated in the surface
180 * state. Each pixel position on the original-sized surface is
181 * replaced with a 2x2 of samples with the following arrangement:
186 * Thus, when sampling from a multisampled texture, it behaves as
187 * though the layout in memory for (x,y,sample) is:
189 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
190 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
192 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
193 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
195 * However, the actual layout of multisampled data in memory is:
197 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
198 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
200 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
201 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
203 * This pattern repeats for each 2x2 pixel block.
205 * As a result, when calculating the size of our 4-sample buffer for
206 * an odd width or height, we have to align before scaling up because
207 * sample 3 is in that bottom right 2x2 block.
209 switch (num_samples
) {
211 width0
= ALIGN(width0
, 2) * 2;
212 height0
= ALIGN(height0
, 2) * 2;
215 width0
= ALIGN(width0
, 2) * 4;
216 height0
= ALIGN(height0
, 2) * 2;
219 /* num_samples should already have been quantized to 0, 1, 4, or
225 /* Non-interleaved */
226 depth0
*= num_samples
;
230 /* array_spacing_lod0 is only used for non-IMS MSAA surfaces. TODO: can we
233 switch (mt
->msaa_layout
) {
234 case INTEL_MSAA_LAYOUT_NONE
:
235 case INTEL_MSAA_LAYOUT_IMS
:
236 mt
->array_spacing_lod0
= false;
238 case INTEL_MSAA_LAYOUT_UMS
:
239 case INTEL_MSAA_LAYOUT_CMS
:
240 mt
->array_spacing_lod0
= true;
244 if (target
== GL_TEXTURE_CUBE_MAP
) {
249 mt
->physical_width0
= width0
;
250 mt
->physical_height0
= height0
;
251 mt
->physical_depth0
= depth0
;
254 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
255 (intel
->must_use_separate_stencil
||
256 (intel
->has_separate_stencil
&&
257 intel
->vtbl
.is_hiz_depth_format(intel
, format
)))) {
258 mt
->stencil_mt
= intel_miptree_create(intel
,
268 INTEL_MIPTREE_TILING_ANY
);
269 if (!mt
->stencil_mt
) {
270 intel_miptree_release(&mt
);
274 /* Fix up the Z miptree format for how we're splitting out separate
275 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
277 if (mt
->format
== MESA_FORMAT_S8_Z24
) {
278 mt
->format
= MESA_FORMAT_X8_Z24
;
279 } else if (mt
->format
== MESA_FORMAT_Z32_FLOAT_X24S8
) {
280 mt
->format
= MESA_FORMAT_Z32_FLOAT
;
283 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
284 _mesa_get_format_name(mt
->format
));
288 intel_get_texture_alignment_unit(intel
, mt
->format
,
289 &mt
->align_w
, &mt
->align_h
);
294 i945_miptree_layout(mt
);
296 i915_miptree_layout(mt
);
298 brw_miptree_layout(intel
, mt
);
305 * \brief Helper function for intel_miptree_create().
308 intel_miptree_choose_tiling(struct intel_context
*intel
,
311 uint32_t num_samples
,
312 enum intel_miptree_tiling_mode requested
,
313 struct intel_mipmap_tree
*mt
)
316 if (format
== MESA_FORMAT_S8
) {
317 /* The stencil buffer is W tiled. However, we request from the kernel a
318 * non-tiled buffer because the GTT is incapable of W fencing.
320 return I915_TILING_NONE
;
323 /* Some usages may want only one type of tiling, like depth miptrees (Y
324 * tiled), or temporary BOs for uploading data once (linear).
327 case INTEL_MIPTREE_TILING_ANY
:
329 case INTEL_MIPTREE_TILING_Y
:
330 return I915_TILING_Y
;
331 case INTEL_MIPTREE_TILING_NONE
:
332 return I915_TILING_NONE
;
335 if (num_samples
> 1) {
336 /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
339 * [DevSNB+]: For multi-sample render targets, this field must be
340 * 1. MSRTs can only be tiled.
342 * Our usual reason for preferring X tiling (fast blits using the
343 * blitting engine) doesn't apply to MSAA, since we'll generally be
344 * downsampling or upsampling when blitting between the MSAA buffer
345 * and another buffer, and the blitting engine doesn't support that.
346 * So use Y tiling, since it makes better use of the cache.
348 return I915_TILING_Y
;
351 GLenum base_format
= _mesa_get_format_base_format(format
);
352 if (intel
->gen
>= 4 &&
353 (base_format
== GL_DEPTH_COMPONENT
||
354 base_format
== GL_DEPTH_STENCIL_EXT
))
355 return I915_TILING_Y
;
357 int minimum_pitch
= mt
->total_width
* mt
->cpp
;
359 /* If the width is much smaller than a tile, don't bother tiling. */
360 if (minimum_pitch
< 64)
361 return I915_TILING_NONE
;
363 if (ALIGN(minimum_pitch
, 512) >= 32768) {
364 perf_debug("%dx%d miptree too large to blit, falling back to untiled",
365 mt
->total_width
, mt
->total_height
);
366 return I915_TILING_NONE
;
369 /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
371 return I915_TILING_X
;
373 return I915_TILING_Y
| I915_TILING_X
;
376 struct intel_mipmap_tree
*
377 intel_miptree_create(struct intel_context
*intel
,
385 bool expect_accelerated_upload
,
387 enum intel_miptree_tiling_mode requested_tiling
)
389 struct intel_mipmap_tree
*mt
;
390 gl_format tex_format
= format
;
391 gl_format etc_format
= MESA_FORMAT_NONE
;
392 GLuint total_width
, total_height
;
394 if (!intel
->is_baytrail
) {
396 case MESA_FORMAT_ETC1_RGB8
:
397 format
= MESA_FORMAT_RGBX8888_REV
;
399 case MESA_FORMAT_ETC2_RGB8
:
400 format
= MESA_FORMAT_RGBX8888_REV
;
402 case MESA_FORMAT_ETC2_SRGB8
:
403 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
404 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
405 format
= MESA_FORMAT_SARGB8
;
407 case MESA_FORMAT_ETC2_RGBA8_EAC
:
408 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
409 format
= MESA_FORMAT_RGBA8888_REV
;
411 case MESA_FORMAT_ETC2_R11_EAC
:
412 format
= MESA_FORMAT_R16
;
414 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
415 format
= MESA_FORMAT_SIGNED_R16
;
417 case MESA_FORMAT_ETC2_RG11_EAC
:
418 format
= MESA_FORMAT_GR1616
;
420 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
421 format
= MESA_FORMAT_SIGNED_GR1616
;
424 /* Non ETC1 / ETC2 format */
429 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
431 mt
= intel_miptree_create_layout(intel
, target
, format
,
432 first_level
, last_level
, width0
,
436 * pitch == 0 || height == 0 indicates the null texture
438 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
439 intel_miptree_release(&mt
);
443 total_width
= mt
->total_width
;
444 total_height
= mt
->total_height
;
446 if (format
== MESA_FORMAT_S8
) {
447 /* Align to size of W tile, 64x64. */
448 total_width
= ALIGN(total_width
, 64);
449 total_height
= ALIGN(total_height
, 64);
452 uint32_t tiling
= intel_miptree_choose_tiling(intel
, format
, width0
,
453 num_samples
, requested_tiling
,
455 bool y_or_x
= tiling
== (I915_TILING_Y
| I915_TILING_X
);
457 mt
->etc_format
= etc_format
;
458 mt
->region
= intel_region_alloc(intel
->intelScreen
,
459 y_or_x
? I915_TILING_Y
: tiling
,
463 expect_accelerated_upload
);
465 /* If the region is too large to fit in the aperture, we need to use the
466 * BLT engine to support it. The BLT paths can't currently handle Y-tiling,
467 * so we need to fall back to X.
469 if (y_or_x
&& mt
->region
->bo
->size
>= intel
->max_gtt_map_object_size
) {
470 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
471 mt
->total_width
, mt
->total_height
);
472 intel_region_release(&mt
->region
);
474 mt
->region
= intel_region_alloc(intel
->intelScreen
,
479 expect_accelerated_upload
);
485 intel_miptree_release(&mt
);
492 struct intel_mipmap_tree
*
493 intel_miptree_create_for_bo(struct intel_context
*intel
,
502 struct intel_mipmap_tree
*mt
;
504 struct intel_region
*region
= calloc(1, sizeof(*region
));
508 /* Nothing will be able to use this miptree with the BO if the offset isn't
511 if (tiling
!= I915_TILING_NONE
)
512 assert(offset
% 4096 == 0);
514 /* miptrees can't handle negative pitch. If you need flipping of images,
515 * that's outside of the scope of the mt.
519 mt
= intel_miptree_create_layout(intel
, GL_TEXTURE_2D
, format
,
522 true, 0 /* num_samples */);
526 region
->cpp
= mt
->cpp
;
527 region
->width
= width
;
528 region
->height
= height
;
529 region
->pitch
= pitch
;
530 region
->refcount
= 1;
531 drm_intel_bo_reference(bo
);
533 region
->tiling
= tiling
;
543 * For a singlesample DRI2 buffer, this simply wraps the given region with a miptree.
545 * For a multisample DRI2 buffer, this wraps the given region with
546 * a singlesample miptree, then creates a multisample miptree into which the
547 * singlesample miptree is embedded as a child.
549 struct intel_mipmap_tree
*
550 intel_miptree_create_for_dri2_buffer(struct intel_context
*intel
,
551 unsigned dri_attachment
,
553 uint32_t num_samples
,
554 struct intel_region
*region
)
556 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
557 struct intel_mipmap_tree
*multisample_mt
= NULL
;
559 /* Only the front and back buffers, which are color buffers, are shared
562 assert(dri_attachment
== __DRI_BUFFER_BACK_LEFT
||
563 dri_attachment
== __DRI_BUFFER_FRONT_LEFT
||
564 dri_attachment
== __DRI_BUFFER_FAKE_FRONT_LEFT
);
565 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
566 _mesa_get_format_base_format(format
) == GL_RGBA
);
568 singlesample_mt
= intel_miptree_create_for_bo(intel
,
576 if (!singlesample_mt
)
578 singlesample_mt
->region
->name
= region
->name
;
580 if (num_samples
== 0)
581 return singlesample_mt
;
583 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
588 if (!multisample_mt
) {
589 intel_miptree_release(&singlesample_mt
);
593 multisample_mt
->singlesample_mt
= singlesample_mt
;
594 multisample_mt
->need_downsample
= false;
596 if (intel
->is_front_buffer_rendering
&&
597 (dri_attachment
== __DRI_BUFFER_FRONT_LEFT
||
598 dri_attachment
== __DRI_BUFFER_FAKE_FRONT_LEFT
)) {
599 intel_miptree_upsample(intel
, multisample_mt
);
602 return multisample_mt
;
605 struct intel_mipmap_tree
*
606 intel_miptree_create_for_renderbuffer(struct intel_context
*intel
,
610 uint32_t num_samples
)
612 struct intel_mipmap_tree
*mt
;
616 mt
= intel_miptree_create(intel
, GL_TEXTURE_2D
, format
, 0, 0,
617 width
, height
, depth
, true, num_samples
,
618 INTEL_MIPTREE_TILING_ANY
);
622 if (intel
->vtbl
.is_hiz_depth_format(intel
, format
)) {
623 ok
= intel_miptree_alloc_hiz(intel
, mt
);
628 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
629 ok
= intel_miptree_alloc_mcs(intel
, mt
, num_samples
);
637 intel_miptree_release(&mt
);
642 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
643 struct intel_mipmap_tree
*src
)
648 intel_miptree_release(dst
);
652 DBG("%s %p refcount now %d\n", __FUNCTION__
, src
, src
->refcount
);
660 intel_miptree_release(struct intel_mipmap_tree
**mt
)
665 DBG("%s %p refcount will be %d\n", __FUNCTION__
, *mt
, (*mt
)->refcount
- 1);
666 if (--(*mt
)->refcount
<= 0) {
669 DBG("%s deleting %p\n", __FUNCTION__
, *mt
);
671 intel_region_release(&((*mt
)->region
));
672 intel_miptree_release(&(*mt
)->stencil_mt
);
673 intel_miptree_release(&(*mt
)->hiz_mt
);
675 intel_miptree_release(&(*mt
)->mcs_mt
);
677 intel_miptree_release(&(*mt
)->singlesample_mt
);
678 intel_resolve_map_clear(&(*mt
)->hiz_map
);
680 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
681 free((*mt
)->level
[i
].slice
);
690 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
691 int *width
, int *height
, int *depth
)
693 switch (image
->TexObject
->Target
) {
694 case GL_TEXTURE_1D_ARRAY
:
695 *width
= image
->Width
;
697 *depth
= image
->Height
;
700 *width
= image
->Width
;
701 *height
= image
->Height
;
702 *depth
= image
->Depth
;
708 * Can the image be pulled into a unified mipmap tree? This mirrors
709 * the completeness test in a lot of ways.
711 * Not sure whether I want to pass gl_texture_image here.
714 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
715 struct gl_texture_image
*image
)
717 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
718 GLuint level
= intelImage
->base
.Base
.Level
;
719 int width
, height
, depth
;
721 /* glTexImage* choose the texture object based on the target passed in, and
722 * objects can't change targets over their lifetimes, so this should be
725 assert(target_to_target(image
->TexObject
->Target
) == mt
->target
);
727 gl_format mt_format
= mt
->format
;
728 if (mt
->format
== MESA_FORMAT_X8_Z24
&& mt
->stencil_mt
)
729 mt_format
= MESA_FORMAT_S8_Z24
;
730 if (mt
->format
== MESA_FORMAT_Z32_FLOAT
&& mt
->stencil_mt
)
731 mt_format
= MESA_FORMAT_Z32_FLOAT_X24S8
;
732 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
733 mt_format
= mt
->etc_format
;
735 if (image
->TexFormat
!= mt_format
)
738 intel_miptree_get_dimensions_for_image(image
, &width
, &height
, &depth
);
740 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
743 /* Test image dimensions against the base level image adjusted for
744 * minification. This will also catch images not present in the
745 * tree, changed targets, etc.
747 if (mt
->target
== GL_TEXTURE_2D_MULTISAMPLE
||
748 mt
->target
== GL_TEXTURE_2D_MULTISAMPLE_ARRAY
) {
749 /* nonzero level here is always bogus */
752 if (width
!= mt
->logical_width0
||
753 height
!= mt
->logical_height0
||
754 depth
!= mt
->logical_depth0
) {
759 /* all normal textures, renderbuffers, etc */
760 if (width
!= mt
->level
[level
].width
||
761 height
!= mt
->level
[level
].height
||
762 depth
!= mt
->level
[level
].depth
) {
767 if (image
->NumSamples
!= mt
->num_samples
)
775 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
778 GLuint w
, GLuint h
, GLuint d
)
780 mt
->level
[level
].width
= w
;
781 mt
->level
[level
].height
= h
;
782 mt
->level
[level
].depth
= d
;
783 mt
->level
[level
].level_x
= x
;
784 mt
->level
[level
].level_y
= y
;
786 DBG("%s level %d size: %d,%d,%d offset %d,%d\n", __FUNCTION__
,
787 level
, w
, h
, d
, x
, y
);
789 assert(mt
->level
[level
].slice
== NULL
);
791 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
792 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
793 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
798 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
799 GLuint level
, GLuint img
,
802 if (img
== 0 && level
== 0)
803 assert(x
== 0 && y
== 0);
805 assert(img
< mt
->level
[level
].depth
);
807 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
808 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
810 DBG("%s level %d img %d pos %d,%d\n",
811 __FUNCTION__
, level
, img
,
812 mt
->level
[level
].slice
[img
].x_offset
,
813 mt
->level
[level
].slice
[img
].y_offset
);
817 intel_miptree_get_image_offset(struct intel_mipmap_tree
*mt
,
818 GLuint level
, GLuint slice
,
819 GLuint
*x
, GLuint
*y
)
821 assert(slice
< mt
->level
[level
].depth
);
823 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
824 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
828 * Rendering with tiled buffers requires that the base address of the buffer
829 * be aligned to a page boundary. For renderbuffers, and sometimes with
830 * textures, we may want the surface to point at a texture image level that
831 * isn't at a page boundary.
833 * This function returns an appropriately-aligned base offset
834 * according to the tiling restrictions, plus any required x/y offset
838 intel_miptree_get_tile_offsets(struct intel_mipmap_tree
*mt
,
839 GLuint level
, GLuint slice
,
843 struct intel_region
*region
= mt
->region
;
845 uint32_t mask_x
, mask_y
;
847 intel_region_get_tile_masks(region
, &mask_x
, &mask_y
, false);
848 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
850 *tile_x
= x
& mask_x
;
851 *tile_y
= y
& mask_y
;
853 return intel_region_get_aligned_offset(region
, x
& ~mask_x
, y
& ~mask_y
,
858 intel_miptree_copy_slice_sw(struct intel_context
*intel
,
859 struct intel_mipmap_tree
*dst_mt
,
860 struct intel_mipmap_tree
*src_mt
,
867 int src_stride
, dst_stride
;
868 int cpp
= dst_mt
->cpp
;
870 intel_miptree_map(intel
, src_mt
,
874 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
877 intel_miptree_map(intel
, dst_mt
,
881 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
885 DBG("sw blit %s mt %p %p/%d -> %s mt %p %p/%d (%dx%d)\n",
886 _mesa_get_format_name(src_mt
->format
),
887 src_mt
, src
, src_stride
,
888 _mesa_get_format_name(dst_mt
->format
),
889 dst_mt
, dst
, dst_stride
,
892 int row_size
= cpp
* width
;
893 if (src_stride
== row_size
&&
894 dst_stride
== row_size
) {
895 memcpy(dst
, src
, row_size
* height
);
897 for (int i
= 0; i
< height
; i
++) {
898 memcpy(dst
, src
, row_size
);
904 intel_miptree_unmap(intel
, dst_mt
, level
, slice
);
905 intel_miptree_unmap(intel
, src_mt
, level
, slice
);
907 /* Don't forget to copy the stencil data over, too. We could have skipped
908 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
909 * shuffling the two data sources in/out of temporary storage instead of
910 * the direct mapping we get this way.
912 if (dst_mt
->stencil_mt
) {
913 assert(src_mt
->stencil_mt
);
914 intel_miptree_copy_slice_sw(intel
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
915 level
, slice
, width
, height
);
920 intel_miptree_copy_slice(struct intel_context
*intel
,
921 struct intel_mipmap_tree
*dst_mt
,
922 struct intel_mipmap_tree
*src_mt
,
928 gl_format format
= src_mt
->format
;
929 uint32_t width
= src_mt
->level
[level
].width
;
930 uint32_t height
= src_mt
->level
[level
].height
;
938 assert(depth
< src_mt
->level
[level
].depth
);
939 assert(src_mt
->format
== dst_mt
->format
);
941 if (dst_mt
->compressed
) {
942 height
= ALIGN(height
, dst_mt
->align_h
) / dst_mt
->align_h
;
943 width
= ALIGN(width
, dst_mt
->align_w
);
946 /* If it's a packed depth/stencil buffer with separate stencil, the blit
947 * below won't apply since we can't do the depth's Y tiling or the
948 * stencil's W tiling in the blitter.
950 if (src_mt
->stencil_mt
) {
951 intel_miptree_copy_slice_sw(intel
,
958 uint32_t dst_x
, dst_y
, src_x
, src_y
;
959 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
960 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
962 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
963 _mesa_get_format_name(src_mt
->format
),
964 src_mt
, src_x
, src_y
, src_mt
->region
->pitch
,
965 _mesa_get_format_name(dst_mt
->format
),
966 dst_mt
, dst_x
, dst_y
, dst_mt
->region
->pitch
,
969 if (!intel_miptree_blit(intel
,
970 src_mt
, level
, slice
, 0, 0, false,
971 dst_mt
, level
, slice
, 0, 0, false,
972 width
, height
, GL_COPY
)) {
973 perf_debug("miptree validate blit for %s failed\n",
974 _mesa_get_format_name(format
));
976 intel_miptree_copy_slice_sw(intel
, dst_mt
, src_mt
, level
, slice
,
982 * Copies the image's current data to the given miptree, and associates that
983 * miptree with the image.
985 * If \c invalidate is true, then the actual image data does not need to be
986 * copied, but the image still needs to be associated to the new miptree (this
987 * is set to true if we're about to clear the image).
990 intel_miptree_copy_teximage(struct intel_context
*intel
,
991 struct intel_texture_image
*intelImage
,
992 struct intel_mipmap_tree
*dst_mt
,
995 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
996 struct intel_texture_object
*intel_obj
=
997 intel_texture_object(intelImage
->base
.Base
.TexObject
);
998 int level
= intelImage
->base
.Base
.Level
;
999 int face
= intelImage
->base
.Base
.Face
;
1000 GLuint depth
= intelImage
->base
.Base
.Depth
;
1003 for (int slice
= 0; slice
< depth
; slice
++) {
1004 intel_miptree_copy_slice(intel
, dst_mt
, src_mt
, level
, face
, slice
);
1008 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1009 intel_obj
->needs_validate
= true;
1013 intel_miptree_alloc_mcs(struct intel_context
*intel
,
1014 struct intel_mipmap_tree
*mt
,
1017 assert(intel
->gen
>= 7); /* MCS only used on Gen7+ */
1021 assert(mt
->mcs_mt
== NULL
);
1023 /* Choose the correct format for the MCS buffer. All that really matters
1024 * is that we allocate the right buffer size, since we'll always be
1025 * accessing this miptree using MCS-specific hardware mechanisms, which
1026 * infer the correct format based on num_samples.
1029 switch (num_samples
) {
1031 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1034 format
= MESA_FORMAT_R8
;
1037 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1038 * for each sample, plus 8 padding bits).
1040 format
= MESA_FORMAT_R_UINT32
;
1043 assert(!"Unrecognized sample count in intel_miptree_alloc_mcs");
1047 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1049 * "The MCS surface must be stored as Tile Y."
1051 mt
->mcs_mt
= intel_miptree_create(intel
,
1057 mt
->logical_height0
,
1060 0 /* num_samples */,
1061 INTEL_MIPTREE_TILING_Y
);
1063 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1065 * When MCS buffer is enabled and bound to MSRT, it is required that it
1066 * is cleared prior to any rendering.
1068 * Since we don't use the MCS buffer for any purpose other than rendering,
1069 * it makes sense to just clear it immediately upon allocation.
1071 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1073 void *data
= intel_miptree_map_raw(intel
, mt
->mcs_mt
);
1074 memset(data
, 0xff, mt
->mcs_mt
->region
->bo
->size
);
1075 intel_miptree_unmap_raw(intel
, mt
->mcs_mt
);
1082 * Helper for intel_miptree_alloc_hiz() that sets
1083 * \c mt->level[level].slice[layer].has_hiz. Return true if and only if
1084 * \c has_hiz was set.
1087 intel_miptree_slice_enable_hiz(struct intel_context
*intel
,
1088 struct intel_mipmap_tree
*mt
,
1094 if (intel
->is_haswell
) {
1095 /* Disable HiZ for some slices to work around a hardware bug.
1097 * Haswell hardware fails to respect
1098 * 3DSTATE_DEPTH_BUFFER.Depth_Coordinate_Offset_X/Y when during HiZ
1099 * ambiguate operations. The failure is inconsistent and affected by
1100 * other GPU contexts. Running a heavy GPU workload in a separate
1101 * process causes the failure rate to drop to nearly 0.
1103 * To workaround the bug, we enable HiZ only when we can guarantee that
1104 * the Depth Coordinate Offset fields will be set to 0. The function
1105 * brw_get_depthstencil_tile_masks() is used to calculate the fields,
1106 * and the function is sometimes called in such a way that the presence
1107 * of an attached stencil buffer changes the fuction's return value.
1109 * The largest tile size considered by brw_get_depthstencil_tile_masks()
1110 * is that of the stencil buffer. Therefore, if this hiz slice's
1111 * corresponding depth slice has an offset that is aligned to the
1112 * stencil buffer tile size, 64x64 pixels, then
1113 * 3DSTATE_DEPTH_BUFFER.Depth_Coordinate_Offset_X/Y is set to 0.
1115 uint32_t depth_x_offset
= mt
->level
[level
].slice
[layer
].x_offset
;
1116 uint32_t depth_y_offset
= mt
->level
[level
].slice
[layer
].y_offset
;
1117 if ((depth_x_offset
& 63) || (depth_y_offset
& 63)) {
1122 mt
->level
[level
].slice
[layer
].has_hiz
= true;
1129 intel_miptree_alloc_hiz(struct intel_context
*intel
,
1130 struct intel_mipmap_tree
*mt
)
1132 assert(mt
->hiz_mt
== NULL
);
1133 mt
->hiz_mt
= intel_miptree_create(intel
,
1139 mt
->logical_height0
,
1143 INTEL_MIPTREE_TILING_ANY
);
1148 /* Mark that all slices need a HiZ resolve. */
1149 struct intel_resolve_map
*head
= &mt
->hiz_map
;
1150 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1151 for (int layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1152 if (!intel_miptree_slice_enable_hiz(intel
, mt
, level
, layer
))
1155 head
->next
= malloc(sizeof(*head
->next
));
1156 head
->next
->prev
= head
;
1157 head
->next
->next
= NULL
;
1160 head
->level
= level
;
1161 head
->layer
= layer
;
1162 head
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1170 * Does the miptree slice have hiz enabled?
1173 intel_miptree_slice_has_hiz(struct intel_mipmap_tree
*mt
,
1177 intel_miptree_check_level_layer(mt
, level
, layer
);
1178 return mt
->level
[level
].slice
[layer
].has_hiz
;
1182 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1186 if (!intel_miptree_slice_has_hiz(mt
, level
, layer
))
1189 intel_resolve_map_set(&mt
->hiz_map
,
1190 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
1195 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1199 if (!intel_miptree_slice_has_hiz(mt
, level
, layer
))
1202 intel_resolve_map_set(&mt
->hiz_map
,
1203 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
1207 intel_miptree_slice_resolve(struct intel_context
*intel
,
1208 struct intel_mipmap_tree
*mt
,
1211 enum gen6_hiz_op need
)
1213 intel_miptree_check_level_layer(mt
, level
, layer
);
1215 struct intel_resolve_map
*item
=
1216 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
1218 if (!item
|| item
->need
!= need
)
1221 intel_hiz_exec(intel
, mt
, level
, layer
, need
);
1222 intel_resolve_map_remove(item
);
1227 intel_miptree_slice_resolve_hiz(struct intel_context
*intel
,
1228 struct intel_mipmap_tree
*mt
,
1232 return intel_miptree_slice_resolve(intel
, mt
, level
, layer
,
1233 GEN6_HIZ_OP_HIZ_RESOLVE
);
1237 intel_miptree_slice_resolve_depth(struct intel_context
*intel
,
1238 struct intel_mipmap_tree
*mt
,
1242 return intel_miptree_slice_resolve(intel
, mt
, level
, layer
,
1243 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1247 intel_miptree_all_slices_resolve(struct intel_context
*intel
,
1248 struct intel_mipmap_tree
*mt
,
1249 enum gen6_hiz_op need
)
1251 bool did_resolve
= false;
1252 struct intel_resolve_map
*i
, *next
;
1254 for (i
= mt
->hiz_map
.next
; i
; i
= next
) {
1256 if (i
->need
!= need
)
1259 intel_hiz_exec(intel
, mt
, i
->level
, i
->layer
, need
);
1260 intel_resolve_map_remove(i
);
1268 intel_miptree_all_slices_resolve_hiz(struct intel_context
*intel
,
1269 struct intel_mipmap_tree
*mt
)
1271 return intel_miptree_all_slices_resolve(intel
, mt
,
1272 GEN6_HIZ_OP_HIZ_RESOLVE
);
1276 intel_miptree_all_slices_resolve_depth(struct intel_context
*intel
,
1277 struct intel_mipmap_tree
*mt
)
1279 return intel_miptree_all_slices_resolve(intel
, mt
,
1280 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1284 * \brief Get pointer offset into stencil buffer.
1286 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1287 * must decode the tile's layout in software.
1290 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1292 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1294 * Even though the returned offset is always positive, the return type is
1296 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1297 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1300 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
1302 uint32_t tile_size
= 4096;
1303 uint32_t tile_width
= 64;
1304 uint32_t tile_height
= 64;
1305 uint32_t row_size
= 64 * stride
;
1307 uint32_t tile_x
= x
/ tile_width
;
1308 uint32_t tile_y
= y
/ tile_height
;
1310 /* The byte's address relative to the tile's base addres. */
1311 uint32_t byte_x
= x
% tile_width
;
1312 uint32_t byte_y
= y
% tile_height
;
1314 uintptr_t u
= tile_y
* row_size
1315 + tile_x
* tile_size
1316 + 512 * (byte_x
/ 8)
1318 + 32 * ((byte_y
/ 4) % 2)
1319 + 16 * ((byte_x
/ 4) % 2)
1320 + 8 * ((byte_y
/ 2) % 2)
1321 + 4 * ((byte_x
/ 2) % 2)
1326 /* adjust for bit6 swizzling */
1327 if (((byte_x
/ 8) % 2) == 1) {
1328 if (((byte_y
/ 8) % 2) == 0) {
1340 intel_miptree_updownsample(struct intel_context
*intel
,
1341 struct intel_mipmap_tree
*src
,
1342 struct intel_mipmap_tree
*dst
,
1352 brw_blorp_blit_miptrees(intel
,
1353 src
, 0 /* level */, 0 /* layer */,
1354 dst
, 0 /* level */, 0 /* layer */,
1359 false, false /*mirror x, y*/);
1361 if (src
->stencil_mt
) {
1362 brw_blorp_blit_miptrees(intel
,
1363 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
1364 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
1369 false, false /*mirror x, y*/);
1375 assert_is_flat(struct intel_mipmap_tree
*mt
)
1377 assert(mt
->target
== GL_TEXTURE_2D
);
1378 assert(mt
->first_level
== 0);
1379 assert(mt
->last_level
== 0);
1383 * \brief Downsample from mt to mt->singlesample_mt.
1385 * If the miptree needs no downsample, then skip.
1388 intel_miptree_downsample(struct intel_context
*intel
,
1389 struct intel_mipmap_tree
*mt
)
1391 /* Only flat, renderbuffer-like miptrees are supported. */
1394 if (!mt
->need_downsample
)
1396 intel_miptree_updownsample(intel
,
1397 mt
, mt
->singlesample_mt
,
1399 mt
->logical_height0
);
1400 mt
->need_downsample
= false;
1404 * \brief Upsample from mt->singlesample_mt to mt.
1406 * The upsample is done unconditionally.
1409 intel_miptree_upsample(struct intel_context
*intel
,
1410 struct intel_mipmap_tree
*mt
)
1412 /* Only flat, renderbuffer-like miptrees are supported. */
1414 assert(!mt
->need_downsample
);
1416 intel_miptree_updownsample(intel
,
1417 mt
->singlesample_mt
, mt
,
1419 mt
->logical_height0
);
1423 intel_miptree_map_raw(struct intel_context
*intel
, struct intel_mipmap_tree
*mt
)
1425 drm_intel_bo
*bo
= mt
->region
->bo
;
1427 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
1428 if (drm_intel_bo_busy(bo
)) {
1429 perf_debug("Mapping a busy BO, causing a stall on the GPU.\n");
1433 intel_flush(&intel
->ctx
);
1435 if (mt
->region
->tiling
!= I915_TILING_NONE
)
1436 drm_intel_gem_bo_map_gtt(bo
);
1438 drm_intel_bo_map(bo
, true);
1444 intel_miptree_unmap_raw(struct intel_context
*intel
,
1445 struct intel_mipmap_tree
*mt
)
1447 drm_intel_bo_unmap(mt
->region
->bo
);
1451 intel_miptree_map_gtt(struct intel_context
*intel
,
1452 struct intel_mipmap_tree
*mt
,
1453 struct intel_miptree_map
*map
,
1454 unsigned int level
, unsigned int slice
)
1456 unsigned int bw
, bh
;
1458 unsigned int image_x
, image_y
;
1462 /* For compressed formats, the stride is the number of bytes per
1463 * row of blocks. intel_miptree_get_image_offset() already does
1466 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
1467 assert(y
% bh
== 0);
1470 base
= intel_miptree_map_raw(intel
, mt
) + mt
->offset
;
1475 /* Note that in the case of cube maps, the caller must have passed the
1476 * slice number referencing the face.
1478 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1482 map
->stride
= mt
->region
->pitch
;
1483 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
1486 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1487 map
->x
, map
->y
, map
->w
, map
->h
,
1488 mt
, _mesa_get_format_name(mt
->format
),
1489 x
, y
, map
->ptr
, map
->stride
);
1493 intel_miptree_unmap_gtt(struct intel_context
*intel
,
1494 struct intel_mipmap_tree
*mt
,
1495 struct intel_miptree_map
*map
,
1499 intel_miptree_unmap_raw(intel
, mt
);
1503 intel_miptree_map_blit(struct intel_context
*intel
,
1504 struct intel_mipmap_tree
*mt
,
1505 struct intel_miptree_map
*map
,
1506 unsigned int level
, unsigned int slice
)
1508 map
->mt
= intel_miptree_create(intel
, GL_TEXTURE_2D
, mt
->format
,
1512 INTEL_MIPTREE_TILING_NONE
);
1514 fprintf(stderr
, "Failed to allocate blit temporary\n");
1517 map
->stride
= map
->mt
->region
->pitch
;
1519 if (!intel_miptree_blit(intel
,
1521 map
->x
, map
->y
, false,
1524 map
->w
, map
->h
, GL_COPY
)) {
1525 fprintf(stderr
, "Failed to blit\n");
1529 intel_batchbuffer_flush(intel
);
1530 map
->ptr
= intel_miptree_map_raw(intel
, map
->mt
);
1532 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1533 map
->x
, map
->y
, map
->w
, map
->h
,
1534 mt
, _mesa_get_format_name(mt
->format
),
1535 level
, slice
, map
->ptr
, map
->stride
);
1540 intel_miptree_release(&map
->mt
);
1546 intel_miptree_unmap_blit(struct intel_context
*intel
,
1547 struct intel_mipmap_tree
*mt
,
1548 struct intel_miptree_map
*map
,
1552 struct gl_context
*ctx
= &intel
->ctx
;
1554 intel_miptree_unmap_raw(intel
, map
->mt
);
1556 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1557 bool ok
= intel_miptree_blit(intel
,
1561 map
->x
, map
->y
, false,
1562 map
->w
, map
->h
, GL_COPY
);
1563 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
1566 intel_miptree_release(&map
->mt
);
1570 intel_miptree_map_s8(struct intel_context
*intel
,
1571 struct intel_mipmap_tree
*mt
,
1572 struct intel_miptree_map
*map
,
1573 unsigned int level
, unsigned int slice
)
1575 map
->stride
= map
->w
;
1576 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
1580 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1581 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1582 * invalidate is set, since we'll be writing the whole rectangle from our
1583 * temporary buffer back out.
1585 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
1586 uint8_t *untiled_s8_map
= map
->ptr
;
1587 uint8_t *tiled_s8_map
= intel_miptree_map_raw(intel
, mt
);
1588 unsigned int image_x
, image_y
;
1590 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1592 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1593 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1594 ptrdiff_t offset
= intel_offset_S8(mt
->region
->pitch
,
1595 x
+ image_x
+ map
->x
,
1596 y
+ image_y
+ map
->y
,
1597 intel
->has_swizzling
);
1598 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
1602 intel_miptree_unmap_raw(intel
, mt
);
1604 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __FUNCTION__
,
1605 map
->x
, map
->y
, map
->w
, map
->h
,
1606 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
1608 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
1609 map
->x
, map
->y
, map
->w
, map
->h
,
1610 mt
, map
->ptr
, map
->stride
);
1615 intel_miptree_unmap_s8(struct intel_context
*intel
,
1616 struct intel_mipmap_tree
*mt
,
1617 struct intel_miptree_map
*map
,
1621 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1622 unsigned int image_x
, image_y
;
1623 uint8_t *untiled_s8_map
= map
->ptr
;
1624 uint8_t *tiled_s8_map
= intel_miptree_map_raw(intel
, mt
);
1626 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1628 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1629 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1630 ptrdiff_t offset
= intel_offset_S8(mt
->region
->pitch
,
1633 intel
->has_swizzling
);
1634 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
1638 intel_miptree_unmap_raw(intel
, mt
);
1645 intel_miptree_map_etc(struct intel_context
*intel
,
1646 struct intel_mipmap_tree
*mt
,
1647 struct intel_miptree_map
*map
,
1651 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
1652 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
1653 assert(mt
->format
== MESA_FORMAT_RGBX8888_REV
);
1656 assert(map
->mode
& GL_MAP_WRITE_BIT
);
1657 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
1659 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
1660 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
1661 map
->w
, map
->h
, 1));
1662 map
->ptr
= map
->buffer
;
1666 intel_miptree_unmap_etc(struct intel_context
*intel
,
1667 struct intel_mipmap_tree
*mt
,
1668 struct intel_miptree_map
*map
,
1674 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1679 uint8_t *dst
= intel_miptree_map_raw(intel
, mt
)
1680 + image_y
* mt
->region
->pitch
1681 + image_x
* mt
->region
->cpp
;
1683 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
1684 _mesa_etc1_unpack_rgba8888(dst
, mt
->region
->pitch
,
1685 map
->ptr
, map
->stride
,
1688 _mesa_unpack_etc2_format(dst
, mt
->region
->pitch
,
1689 map
->ptr
, map
->stride
,
1690 map
->w
, map
->h
, mt
->etc_format
);
1692 intel_miptree_unmap_raw(intel
, mt
);
1697 * Mapping function for packed depth/stencil miptrees backed by real separate
1698 * miptrees for depth and stencil.
1700 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
1701 * separate from the depth buffer. Yet at the GL API level, we have to expose
1702 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
1703 * be able to map that memory for texture storage and glReadPixels-type
1704 * operations. We give Mesa core that access by mallocing a temporary and
1705 * copying the data between the actual backing store and the temporary.
1708 intel_miptree_map_depthstencil(struct intel_context
*intel
,
1709 struct intel_mipmap_tree
*mt
,
1710 struct intel_miptree_map
*map
,
1711 unsigned int level
, unsigned int slice
)
1713 struct intel_mipmap_tree
*z_mt
= mt
;
1714 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
1715 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z32_FLOAT
;
1716 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
1718 map
->stride
= map
->w
* packed_bpp
;
1719 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
1723 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1724 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1725 * invalidate is set, since we'll be writing the whole rectangle from our
1726 * temporary buffer back out.
1728 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
1729 uint32_t *packed_map
= map
->ptr
;
1730 uint8_t *s_map
= intel_miptree_map_raw(intel
, s_mt
);
1731 uint32_t *z_map
= intel_miptree_map_raw(intel
, z_mt
);
1732 unsigned int s_image_x
, s_image_y
;
1733 unsigned int z_image_x
, z_image_y
;
1735 intel_miptree_get_image_offset(s_mt
, level
, slice
,
1736 &s_image_x
, &s_image_y
);
1737 intel_miptree_get_image_offset(z_mt
, level
, slice
,
1738 &z_image_x
, &z_image_y
);
1740 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1741 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1742 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
1743 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->region
->pitch
,
1746 intel
->has_swizzling
);
1747 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
1748 (z_mt
->region
->pitch
/ 4) +
1749 (map_x
+ z_image_x
));
1750 uint8_t s
= s_map
[s_offset
];
1751 uint32_t z
= z_map
[z_offset
];
1753 if (map_z32f_x24s8
) {
1754 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
1755 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
1757 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
1762 intel_miptree_unmap_raw(intel
, s_mt
);
1763 intel_miptree_unmap_raw(intel
, z_mt
);
1765 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
1767 map
->x
, map
->y
, map
->w
, map
->h
,
1768 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
1769 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
1770 map
->ptr
, map
->stride
);
1772 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
1773 map
->x
, map
->y
, map
->w
, map
->h
,
1774 mt
, map
->ptr
, map
->stride
);
1779 intel_miptree_unmap_depthstencil(struct intel_context
*intel
,
1780 struct intel_mipmap_tree
*mt
,
1781 struct intel_miptree_map
*map
,
1785 struct intel_mipmap_tree
*z_mt
= mt
;
1786 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
1787 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z32_FLOAT
;
1789 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1790 uint32_t *packed_map
= map
->ptr
;
1791 uint8_t *s_map
= intel_miptree_map_raw(intel
, s_mt
);
1792 uint32_t *z_map
= intel_miptree_map_raw(intel
, z_mt
);
1793 unsigned int s_image_x
, s_image_y
;
1794 unsigned int z_image_x
, z_image_y
;
1796 intel_miptree_get_image_offset(s_mt
, level
, slice
,
1797 &s_image_x
, &s_image_y
);
1798 intel_miptree_get_image_offset(z_mt
, level
, slice
,
1799 &z_image_x
, &z_image_y
);
1801 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1802 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1803 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->region
->pitch
,
1804 x
+ s_image_x
+ map
->x
,
1805 y
+ s_image_y
+ map
->y
,
1806 intel
->has_swizzling
);
1807 ptrdiff_t z_offset
= ((y
+ z_image_y
) *
1808 (z_mt
->region
->pitch
/ 4) +
1811 if (map_z32f_x24s8
) {
1812 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
1813 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
1815 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
1816 s_map
[s_offset
] = packed
>> 24;
1817 z_map
[z_offset
] = packed
;
1822 intel_miptree_unmap_raw(intel
, s_mt
);
1823 intel_miptree_unmap_raw(intel
, z_mt
);
1825 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
1827 map
->x
, map
->y
, map
->w
, map
->h
,
1828 z_mt
, _mesa_get_format_name(z_mt
->format
),
1829 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
1830 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
1831 map
->ptr
, map
->stride
);
1838 * Create and attach a map to the miptree at (level, slice). Return the
1841 static struct intel_miptree_map
*
1842 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
1851 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
1856 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
1857 mt
->level
[level
].slice
[slice
].map
= map
;
1869 * Release the map at (level, slice).
1872 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
1876 struct intel_miptree_map
**map
;
1878 map
= &mt
->level
[level
].slice
[slice
].map
;
1884 intel_miptree_map_singlesample(struct intel_context
*intel
,
1885 struct intel_mipmap_tree
*mt
,
1896 struct intel_miptree_map
*map
;
1898 assert(mt
->num_samples
<= 1);
1900 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
1907 intel_miptree_slice_resolve_depth(intel
, mt
, level
, slice
);
1908 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1909 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
1912 if (mt
->format
== MESA_FORMAT_S8
) {
1913 intel_miptree_map_s8(intel
, mt
, map
, level
, slice
);
1914 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
1915 !(mode
& BRW_MAP_DIRECT_BIT
)) {
1916 intel_miptree_map_etc(intel
, mt
, map
, level
, slice
);
1917 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
1918 intel_miptree_map_depthstencil(intel
, mt
, map
, level
, slice
);
1920 /* See intel_miptree_blit() for details on the 32k pitch limit. */
1921 else if (intel
->has_llc
&&
1922 !(mode
& GL_MAP_WRITE_BIT
) &&
1924 (mt
->region
->tiling
== I915_TILING_X
||
1925 (intel
->gen
>= 6 && mt
->region
->tiling
== I915_TILING_Y
)) &&
1926 mt
->region
->pitch
< 32768) {
1927 intel_miptree_map_blit(intel
, mt
, map
, level
, slice
);
1928 } else if (mt
->region
->tiling
!= I915_TILING_NONE
&&
1929 mt
->region
->bo
->size
>= intel
->max_gtt_map_object_size
) {
1930 assert(mt
->region
->pitch
< 32768);
1931 intel_miptree_map_blit(intel
, mt
, map
, level
, slice
);
1933 intel_miptree_map_gtt(intel
, mt
, map
, level
, slice
);
1936 *out_ptr
= map
->ptr
;
1937 *out_stride
= map
->stride
;
1939 if (map
->ptr
== NULL
)
1940 intel_miptree_release_map(mt
, level
, slice
);
1944 intel_miptree_unmap_singlesample(struct intel_context
*intel
,
1945 struct intel_mipmap_tree
*mt
,
1949 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
1951 assert(mt
->num_samples
<= 1);
1956 DBG("%s: mt %p (%s) level %d slice %d\n", __FUNCTION__
,
1957 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
1959 if (mt
->format
== MESA_FORMAT_S8
) {
1960 intel_miptree_unmap_s8(intel
, mt
, map
, level
, slice
);
1961 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
1962 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
1963 intel_miptree_unmap_etc(intel
, mt
, map
, level
, slice
);
1964 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
1965 intel_miptree_unmap_depthstencil(intel
, mt
, map
, level
, slice
);
1966 } else if (map
->mt
) {
1967 intel_miptree_unmap_blit(intel
, mt
, map
, level
, slice
);
1969 intel_miptree_unmap_gtt(intel
, mt
, map
, level
, slice
);
1972 intel_miptree_release_map(mt
, level
, slice
);
1976 intel_miptree_map_multisample(struct intel_context
*intel
,
1977 struct intel_mipmap_tree
*mt
,
1988 struct intel_miptree_map
*map
;
1990 assert(mt
->num_samples
> 1);
1992 /* Only flat, renderbuffer-like miptrees are supported. */
1993 if (mt
->target
!= GL_TEXTURE_2D
||
1994 mt
->first_level
!= 0 ||
1995 mt
->last_level
!= 0) {
1996 _mesa_problem(&intel
->ctx
, "attempt to map a multisample miptree for "
1997 "which (target, first_level, last_level != "
1998 "(GL_TEXTURE_2D, 0, 0)");
2002 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2006 if (!mt
->singlesample_mt
) {
2007 mt
->singlesample_mt
=
2008 intel_miptree_create_for_renderbuffer(intel
,
2011 mt
->logical_height0
,
2013 if (!mt
->singlesample_mt
)
2016 map
->singlesample_mt_is_tmp
= true;
2017 mt
->need_downsample
= true;
2020 intel_miptree_downsample(intel
, mt
);
2021 intel_miptree_map_singlesample(intel
, mt
->singlesample_mt
,
2025 out_ptr
, out_stride
);
2029 intel_miptree_release_map(mt
, level
, slice
);
2035 intel_miptree_unmap_multisample(struct intel_context
*intel
,
2036 struct intel_mipmap_tree
*mt
,
2040 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2042 assert(mt
->num_samples
> 1);
2047 intel_miptree_unmap_singlesample(intel
, mt
->singlesample_mt
, level
, slice
);
2049 mt
->need_downsample
= false;
2050 if (map
->mode
& GL_MAP_WRITE_BIT
)
2051 intel_miptree_upsample(intel
, mt
);
2053 if (map
->singlesample_mt_is_tmp
)
2054 intel_miptree_release(&mt
->singlesample_mt
);
2056 intel_miptree_release_map(mt
, level
, slice
);
2060 intel_miptree_map(struct intel_context
*intel
,
2061 struct intel_mipmap_tree
*mt
,
2072 if (mt
->num_samples
<= 1)
2073 intel_miptree_map_singlesample(intel
, mt
,
2077 out_ptr
, out_stride
);
2079 intel_miptree_map_multisample(intel
, mt
,
2083 out_ptr
, out_stride
);
2087 intel_miptree_unmap(struct intel_context
*intel
,
2088 struct intel_mipmap_tree
*mt
,
2092 if (mt
->num_samples
<= 1)
2093 intel_miptree_unmap_singlesample(intel
, mt
, level
, slice
);
2095 intel_miptree_unmap_multisample(intel
, mt
, level
, slice
);