i965: Add separate stencil/HiZ setup for MESA_FORMAT_Z32_FLOAT_X24S8.
[mesa.git] / src / mesa / drivers / dri / intel / intel_mipmap_tree.c
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2 *
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
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16 * of the Software.
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27
28 #include "intel_batchbuffer.h"
29 #include "intel_context.h"
30 #include "intel_mipmap_tree.h"
31 #include "intel_regions.h"
32 #include "intel_resolve_map.h"
33 #include "intel_span.h"
34 #include "intel_tex_layout.h"
35 #include "intel_tex.h"
36 #include "intel_blit.h"
37
38 #include "main/enums.h"
39 #include "main/formats.h"
40 #include "main/image.h"
41 #include "main/teximage.h"
42
43 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
44
45 static GLenum
46 target_to_target(GLenum target)
47 {
48 switch (target) {
49 case GL_TEXTURE_CUBE_MAP_POSITIVE_X_ARB:
50 case GL_TEXTURE_CUBE_MAP_NEGATIVE_X_ARB:
51 case GL_TEXTURE_CUBE_MAP_POSITIVE_Y_ARB:
52 case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y_ARB:
53 case GL_TEXTURE_CUBE_MAP_POSITIVE_Z_ARB:
54 case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z_ARB:
55 return GL_TEXTURE_CUBE_MAP_ARB;
56 default:
57 return target;
58 }
59 }
60
61 static struct intel_mipmap_tree *
62 intel_miptree_create_internal(struct intel_context *intel,
63 GLenum target,
64 gl_format format,
65 GLuint first_level,
66 GLuint last_level,
67 GLuint width0,
68 GLuint height0,
69 GLuint depth0)
70 {
71 struct intel_mipmap_tree *mt = calloc(sizeof(*mt), 1);
72 int compress_byte = 0;
73
74 DBG("%s target %s format %s level %d..%d <-- %p\n", __FUNCTION__,
75 _mesa_lookup_enum_by_nr(target),
76 _mesa_get_format_name(format),
77 first_level, last_level, mt);
78
79 if (_mesa_is_format_compressed(format))
80 compress_byte = intel_compressed_num_bytes(format);
81
82 mt->target = target_to_target(target);
83 mt->format = format;
84 mt->first_level = first_level;
85 mt->last_level = last_level;
86 mt->width0 = width0;
87 mt->height0 = height0;
88 mt->cpp = compress_byte ? compress_byte : _mesa_get_format_bytes(mt->format);
89 mt->compressed = compress_byte ? 1 : 0;
90 mt->refcount = 1;
91
92 if (target == GL_TEXTURE_CUBE_MAP) {
93 assert(depth0 == 1);
94 mt->depth0 = 6;
95 } else {
96 mt->depth0 = depth0;
97 }
98
99 if (format == MESA_FORMAT_S8) {
100 /* The stencil buffer has quirky pitch requirements. From Vol 2a,
101 * 11.5.6.2.1 3DSTATE_STENCIL_BUFFER, field "Surface Pitch":
102 * The pitch must be set to 2x the value computed based on width, as
103 * the stencil buffer is stored with two rows interleaved.
104 */
105 assert(intel->has_separate_stencil);
106 mt->cpp = 2;
107 }
108
109 if (_mesa_is_depthstencil_format(_mesa_get_format_base_format(format)) &&
110 (intel->must_use_separate_stencil ||
111 (intel->has_separate_stencil &&
112 intel->vtbl.is_hiz_depth_format(intel, format)))) {
113 mt->stencil_mt = intel_miptree_create(intel,
114 mt->target,
115 MESA_FORMAT_S8,
116 mt->first_level,
117 mt->last_level,
118 mt->width0,
119 mt->height0,
120 mt->depth0,
121 true);
122 if (!mt->stencil_mt) {
123 intel_miptree_release(&mt);
124 return NULL;
125 }
126
127 /* Fix up the Z miptree format for how we're splitting out separate
128 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
129 */
130 if (mt->format == MESA_FORMAT_S8_Z24) {
131 mt->format = MESA_FORMAT_X8_Z24;
132 } else if (mt->format == MESA_FORMAT_Z32_FLOAT_X24S8) {
133 mt->format = MESA_FORMAT_Z32_FLOAT;
134 mt->cpp = 4;
135 } else {
136 _mesa_problem(NULL, "Unknown format %s in separate stencil mt\n",
137 _mesa_get_format_name(mt->format));
138 }
139 }
140
141 intel_get_texture_alignment_unit(intel, mt->format,
142 &mt->align_w, &mt->align_h);
143
144 #ifdef I915
145 (void) intel;
146 if (intel->is_945)
147 i945_miptree_layout(mt);
148 else
149 i915_miptree_layout(mt);
150 #else
151 brw_miptree_layout(intel, mt);
152 #endif
153
154 return mt;
155 }
156
157
158 struct intel_mipmap_tree *
159 intel_miptree_create(struct intel_context *intel,
160 GLenum target,
161 gl_format format,
162 GLuint first_level,
163 GLuint last_level,
164 GLuint width0,
165 GLuint height0,
166 GLuint depth0,
167 bool expect_accelerated_upload)
168 {
169 struct intel_mipmap_tree *mt;
170 uint32_t tiling = I915_TILING_NONE;
171 GLenum base_format = _mesa_get_format_base_format(format);
172
173 if (intel->use_texture_tiling && !_mesa_is_format_compressed(format)) {
174 if (intel->gen >= 4 &&
175 (base_format == GL_DEPTH_COMPONENT ||
176 base_format == GL_DEPTH_STENCIL_EXT))
177 tiling = I915_TILING_Y;
178 else if (width0 >= 64)
179 tiling = I915_TILING_X;
180 }
181
182 if (format == MESA_FORMAT_S8) {
183 /* The stencil buffer is W tiled. However, we request from the kernel a
184 * non-tiled buffer because the GTT is incapable of W fencing.
185 *
186 * The stencil buffer has quirky pitch requirements. From Vol 2a,
187 * 11.5.6.2.1 3DSTATE_STENCIL_BUFFER, field "Surface Pitch":
188 * The pitch must be set to 2x the value computed based on width, as
189 * the stencil buffer is stored with two rows interleaved.
190 * To accomplish this, we resort to the nasty hack of doubling the drm
191 * region's cpp and halving its height.
192 *
193 * If we neglect to double the pitch, then render corruption occurs.
194 */
195 tiling = I915_TILING_NONE;
196 width0 = ALIGN(width0, 64);
197 height0 = ALIGN((height0 + 1) / 2, 64);
198 }
199
200 mt = intel_miptree_create_internal(intel, target, format,
201 first_level, last_level, width0,
202 height0, depth0);
203 /*
204 * pitch == 0 || height == 0 indicates the null texture
205 */
206 if (!mt || !mt->total_width || !mt->total_height) {
207 free(mt);
208 return NULL;
209 }
210
211 mt->region = intel_region_alloc(intel->intelScreen,
212 tiling,
213 mt->cpp,
214 mt->total_width,
215 mt->total_height,
216 expect_accelerated_upload);
217
218 if (!mt->region) {
219 free(mt);
220 return NULL;
221 }
222
223 return mt;
224 }
225
226
227 struct intel_mipmap_tree *
228 intel_miptree_create_for_region(struct intel_context *intel,
229 GLenum target,
230 gl_format format,
231 struct intel_region *region)
232 {
233 struct intel_mipmap_tree *mt;
234
235 mt = intel_miptree_create_internal(intel, target, format,
236 0, 0,
237 region->width, region->height, 1);
238 if (!mt)
239 return mt;
240
241 intel_region_reference(&mt->region, region);
242
243 return mt;
244 }
245
246 struct intel_mipmap_tree*
247 intel_miptree_create_for_renderbuffer(struct intel_context *intel,
248 gl_format format,
249 uint32_t width,
250 uint32_t height)
251 {
252 struct intel_mipmap_tree *mt;
253
254 mt = intel_miptree_create(intel, GL_TEXTURE_2D, format, 0, 0,
255 width, height, 1, true);
256
257 return mt;
258 }
259
260 void
261 intel_miptree_reference(struct intel_mipmap_tree **dst,
262 struct intel_mipmap_tree *src)
263 {
264 if (*dst == src)
265 return;
266
267 intel_miptree_release(dst);
268
269 if (src) {
270 src->refcount++;
271 DBG("%s %p refcount now %d\n", __FUNCTION__, src, src->refcount);
272 }
273
274 *dst = src;
275 }
276
277
278 void
279 intel_miptree_release(struct intel_mipmap_tree **mt)
280 {
281 if (!*mt)
282 return;
283
284 DBG("%s %p refcount will be %d\n", __FUNCTION__, *mt, (*mt)->refcount - 1);
285 if (--(*mt)->refcount <= 0) {
286 GLuint i;
287
288 DBG("%s deleting %p\n", __FUNCTION__, *mt);
289
290 intel_region_release(&((*mt)->region));
291 intel_miptree_release(&(*mt)->stencil_mt);
292 intel_miptree_release(&(*mt)->hiz_mt);
293 intel_resolve_map_clear(&(*mt)->hiz_map);
294
295 for (i = 0; i < MAX_TEXTURE_LEVELS; i++) {
296 free((*mt)->level[i].slice);
297 }
298
299 free(*mt);
300 }
301 *mt = NULL;
302 }
303
304 void
305 intel_miptree_get_dimensions_for_image(struct gl_texture_image *image,
306 int *width, int *height, int *depth)
307 {
308 switch (image->TexObject->Target) {
309 case GL_TEXTURE_1D_ARRAY:
310 *width = image->Width;
311 *height = 1;
312 *depth = image->Height;
313 break;
314 default:
315 *width = image->Width;
316 *height = image->Height;
317 *depth = image->Depth;
318 break;
319 }
320 }
321
322 /**
323 * Can the image be pulled into a unified mipmap tree? This mirrors
324 * the completeness test in a lot of ways.
325 *
326 * Not sure whether I want to pass gl_texture_image here.
327 */
328 bool
329 intel_miptree_match_image(struct intel_mipmap_tree *mt,
330 struct gl_texture_image *image)
331 {
332 struct intel_texture_image *intelImage = intel_texture_image(image);
333 GLuint level = intelImage->base.Base.Level;
334 int width, height, depth;
335
336 if (image->TexFormat != mt->format &&
337 !(image->TexFormat == MESA_FORMAT_S8_Z24 &&
338 mt->format == MESA_FORMAT_X8_Z24 &&
339 mt->stencil_mt)) {
340 return false;
341 }
342
343 intel_miptree_get_dimensions_for_image(image, &width, &height, &depth);
344
345 /* Test image dimensions against the base level image adjusted for
346 * minification. This will also catch images not present in the
347 * tree, changed targets, etc.
348 */
349 if (width != mt->level[level].width ||
350 height != mt->level[level].height ||
351 depth != mt->level[level].depth)
352 return false;
353
354 return true;
355 }
356
357
358 void
359 intel_miptree_set_level_info(struct intel_mipmap_tree *mt,
360 GLuint level,
361 GLuint x, GLuint y,
362 GLuint w, GLuint h, GLuint d)
363 {
364 mt->level[level].width = w;
365 mt->level[level].height = h;
366 mt->level[level].depth = d;
367 mt->level[level].level_x = x;
368 mt->level[level].level_y = y;
369
370 DBG("%s level %d size: %d,%d,%d offset %d,%d\n", __FUNCTION__,
371 level, w, h, d, x, y);
372
373 assert(mt->level[level].slice == NULL);
374
375 mt->level[level].slice = calloc(d, sizeof(*mt->level[0].slice));
376 mt->level[level].slice[0].x_offset = mt->level[level].level_x;
377 mt->level[level].slice[0].y_offset = mt->level[level].level_y;
378 }
379
380
381 void
382 intel_miptree_set_image_offset(struct intel_mipmap_tree *mt,
383 GLuint level, GLuint img,
384 GLuint x, GLuint y)
385 {
386 if (img == 0 && level == 0)
387 assert(x == 0 && y == 0);
388
389 assert(img < mt->level[level].depth);
390
391 mt->level[level].slice[img].x_offset = mt->level[level].level_x + x;
392 mt->level[level].slice[img].y_offset = mt->level[level].level_y + y;
393
394 DBG("%s level %d img %d pos %d,%d\n",
395 __FUNCTION__, level, img,
396 mt->level[level].slice[img].x_offset,
397 mt->level[level].slice[img].y_offset);
398 }
399
400
401 /**
402 * For cube map textures, either the \c face parameter can be used, of course,
403 * or the cube face can be interpreted as a depth layer and the \c layer
404 * parameter used.
405 */
406 void
407 intel_miptree_get_image_offset(struct intel_mipmap_tree *mt,
408 GLuint level, GLuint face, GLuint layer,
409 GLuint *x, GLuint *y)
410 {
411 int slice;
412
413 if (face > 0) {
414 assert(mt->target == GL_TEXTURE_CUBE_MAP);
415 assert(face < 6);
416 assert(layer == 0);
417 slice = face;
418 } else {
419 /* This branch may be taken even if the texture target is a cube map. In
420 * that case, the caller chose to interpret each cube face as a layer.
421 */
422 assert(face == 0);
423 slice = layer;
424 }
425
426 *x = mt->level[level].slice[slice].x_offset;
427 *y = mt->level[level].slice[slice].y_offset;
428 }
429
430 static void
431 intel_miptree_copy_slice(struct intel_context *intel,
432 struct intel_mipmap_tree *dst_mt,
433 struct intel_mipmap_tree *src_mt,
434 int level,
435 int face,
436 int depth)
437
438 {
439 gl_format format = src_mt->format;
440 uint32_t width = src_mt->level[level].width;
441 uint32_t height = src_mt->level[level].height;
442
443 assert(depth < src_mt->level[level].depth);
444
445 if (dst_mt->compressed) {
446 height = ALIGN(height, dst_mt->align_h) / dst_mt->align_h;
447 width = ALIGN(width, dst_mt->align_w);
448 }
449
450 uint32_t dst_x, dst_y, src_x, src_y;
451 intel_miptree_get_image_offset(dst_mt, level, face, depth,
452 &dst_x, &dst_y);
453 intel_miptree_get_image_offset(src_mt, level, face, depth,
454 &src_x, &src_y);
455
456 DBG("validate blit mt %p %d,%d/%d -> mt %p %d,%d/%d (%dx%d)\n",
457 src_mt, src_x, src_y, src_mt->region->pitch * src_mt->region->cpp,
458 dst_mt, dst_x, dst_y, dst_mt->region->pitch * dst_mt->region->cpp,
459 width, height);
460
461 if (!intelEmitCopyBlit(intel,
462 dst_mt->region->cpp,
463 src_mt->region->pitch, src_mt->region->bo,
464 0, src_mt->region->tiling,
465 dst_mt->region->pitch, dst_mt->region->bo,
466 0, dst_mt->region->tiling,
467 src_x, src_y,
468 dst_x, dst_y,
469 width, height,
470 GL_COPY)) {
471
472 fallback_debug("miptree validate blit for %s failed\n",
473 _mesa_get_format_name(format));
474 void *dst = intel_region_map(intel, dst_mt->region, GL_MAP_WRITE_BIT);
475 void *src = intel_region_map(intel, src_mt->region, GL_MAP_READ_BIT);
476
477 _mesa_copy_rect(dst,
478 dst_mt->cpp,
479 dst_mt->region->pitch,
480 dst_x, dst_y,
481 width, height,
482 src, src_mt->region->pitch,
483 src_x, src_y);
484
485 intel_region_unmap(intel, dst_mt->region);
486 intel_region_unmap(intel, src_mt->region);
487 }
488
489 if (src_mt->stencil_mt) {
490 intel_miptree_copy_slice(intel,
491 dst_mt->stencil_mt, src_mt->stencil_mt,
492 level, face, depth);
493 }
494 }
495
496 /**
497 * Copies the image's current data to the given miptree, and associates that
498 * miptree with the image.
499 */
500 void
501 intel_miptree_copy_teximage(struct intel_context *intel,
502 struct intel_texture_image *intelImage,
503 struct intel_mipmap_tree *dst_mt)
504 {
505 struct intel_mipmap_tree *src_mt = intelImage->mt;
506 int level = intelImage->base.Base.Level;
507 int face = intelImage->base.Base.Face;
508 GLuint depth = intelImage->base.Base.Depth;
509
510 for (int slice = 0; slice < depth; slice++) {
511 intel_miptree_copy_slice(intel, dst_mt, src_mt, level, face, slice);
512 }
513
514 intel_miptree_reference(&intelImage->mt, dst_mt);
515 }
516
517 bool
518 intel_miptree_alloc_hiz(struct intel_context *intel,
519 struct intel_mipmap_tree *mt)
520 {
521 assert(mt->hiz_mt == NULL);
522 mt->hiz_mt = intel_miptree_create(intel,
523 mt->target,
524 MESA_FORMAT_X8_Z24,
525 mt->first_level,
526 mt->last_level,
527 mt->width0,
528 mt->height0,
529 mt->depth0,
530 true);
531
532 if (!mt->hiz_mt)
533 return false;
534
535 /* Mark that all slices need a HiZ resolve. */
536 struct intel_resolve_map *head = &mt->hiz_map;
537 for (int level = mt->first_level; level <= mt->last_level; ++level) {
538 for (int layer = 0; layer < mt->level[level].depth; ++layer) {
539 head->next = malloc(sizeof(*head->next));
540 head->next->prev = head;
541 head->next->next = NULL;
542 head = head->next;
543
544 head->level = level;
545 head->layer = layer;
546 head->need = INTEL_NEED_HIZ_RESOLVE;
547 }
548 }
549
550 return true;
551 }
552
553 void
554 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree *mt,
555 uint32_t level,
556 uint32_t layer)
557 {
558 intel_miptree_check_level_layer(mt, level, layer);
559
560 if (!mt->hiz_mt)
561 return;
562
563 intel_resolve_map_set(&mt->hiz_map,
564 level, layer, INTEL_NEED_HIZ_RESOLVE);
565 }
566
567
568 void
569 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree *mt,
570 uint32_t level,
571 uint32_t layer)
572 {
573 intel_miptree_check_level_layer(mt, level, layer);
574
575 if (!mt->hiz_mt)
576 return;
577
578 intel_resolve_map_set(&mt->hiz_map,
579 level, layer, INTEL_NEED_DEPTH_RESOLVE);
580 }
581
582 typedef void (*resolve_func_t)(struct intel_context *intel,
583 struct intel_mipmap_tree *mt,
584 uint32_t level,
585 uint32_t layer);
586
587 static bool
588 intel_miptree_slice_resolve(struct intel_context *intel,
589 struct intel_mipmap_tree *mt,
590 uint32_t level,
591 uint32_t layer,
592 enum intel_need_resolve need,
593 resolve_func_t func)
594 {
595 intel_miptree_check_level_layer(mt, level, layer);
596
597 struct intel_resolve_map *item =
598 intel_resolve_map_get(&mt->hiz_map, level, layer);
599
600 if (!item || item->need != need)
601 return false;
602
603 func(intel, mt, level, layer);
604 intel_resolve_map_remove(item);
605 return true;
606 }
607
608 bool
609 intel_miptree_slice_resolve_hiz(struct intel_context *intel,
610 struct intel_mipmap_tree *mt,
611 uint32_t level,
612 uint32_t layer)
613 {
614 return intel_miptree_slice_resolve(intel, mt, level, layer,
615 INTEL_NEED_HIZ_RESOLVE,
616 intel->vtbl.resolve_hiz_slice);
617 }
618
619 bool
620 intel_miptree_slice_resolve_depth(struct intel_context *intel,
621 struct intel_mipmap_tree *mt,
622 uint32_t level,
623 uint32_t layer)
624 {
625 return intel_miptree_slice_resolve(intel, mt, level, layer,
626 INTEL_NEED_DEPTH_RESOLVE,
627 intel->vtbl.resolve_depth_slice);
628 }
629
630 static bool
631 intel_miptree_all_slices_resolve(struct intel_context *intel,
632 struct intel_mipmap_tree *mt,
633 enum intel_need_resolve need,
634 resolve_func_t func)
635 {
636 bool did_resolve = false;
637 struct intel_resolve_map *i;
638
639 for (i = mt->hiz_map.next; i; i = i->next) {
640 if (i->need != need)
641 continue;
642 func(intel, mt, i->level, i->layer);
643 intel_resolve_map_remove(i);
644 did_resolve = true;
645 }
646
647 return did_resolve;
648 }
649
650 bool
651 intel_miptree_all_slices_resolve_hiz(struct intel_context *intel,
652 struct intel_mipmap_tree *mt)
653 {
654 return intel_miptree_all_slices_resolve(intel, mt,
655 INTEL_NEED_HIZ_RESOLVE,
656 intel->vtbl.resolve_hiz_slice);
657 }
658
659 bool
660 intel_miptree_all_slices_resolve_depth(struct intel_context *intel,
661 struct intel_mipmap_tree *mt)
662 {
663 return intel_miptree_all_slices_resolve(intel, mt,
664 INTEL_NEED_DEPTH_RESOLVE,
665 intel->vtbl.resolve_depth_slice);
666 }
667
668 static void
669 intel_miptree_map_gtt(struct intel_context *intel,
670 struct intel_mipmap_tree *mt,
671 struct intel_miptree_map *map,
672 unsigned int level, unsigned int slice)
673 {
674 unsigned int bw, bh;
675 void *base;
676 unsigned int image_x, image_y;
677 int x = map->x;
678 int y = map->y;
679
680 /* For compressed formats, the stride is the number of bytes per
681 * row of blocks. intel_miptree_get_image_offset() already does
682 * the divide.
683 */
684 _mesa_get_format_block_size(mt->format, &bw, &bh);
685 assert(y % bh == 0);
686 y /= bh;
687
688 base = intel_region_map(intel, mt->region, map->mode);
689 /* Note that in the case of cube maps, the caller must have passed the slice
690 * number referencing the face.
691 */
692 intel_miptree_get_image_offset(mt, level, 0, slice, &image_x, &image_y);
693 x += image_x;
694 y += image_y;
695
696 map->stride = mt->region->pitch * mt->cpp;
697 map->ptr = base + y * map->stride + x * mt->cpp;
698
699 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__,
700 map->x, map->y, map->w, map->h,
701 mt, _mesa_get_format_name(mt->format),
702 x, y, map->ptr, map->stride);
703 }
704
705 static void
706 intel_miptree_unmap_gtt(struct intel_context *intel,
707 struct intel_mipmap_tree *mt,
708 struct intel_miptree_map *map,
709 unsigned int level,
710 unsigned int slice)
711 {
712 intel_region_unmap(intel, mt->region);
713 }
714
715 static void
716 intel_miptree_map_blit(struct intel_context *intel,
717 struct intel_mipmap_tree *mt,
718 struct intel_miptree_map *map,
719 unsigned int level, unsigned int slice)
720 {
721 unsigned int image_x, image_y;
722 int x = map->x;
723 int y = map->y;
724 int ret;
725
726 /* The blitter requires the pitch to be aligned to 4. */
727 map->stride = ALIGN(map->w * mt->region->cpp, 4);
728
729 map->bo = drm_intel_bo_alloc(intel->bufmgr, "intel_miptree_map_blit() temp",
730 map->stride * map->h, 4096);
731 if (!map->bo) {
732 fprintf(stderr, "Failed to allocate blit temporary\n");
733 goto fail;
734 }
735
736 intel_miptree_get_image_offset(mt, level, 0, slice, &image_x, &image_y);
737 x += image_x;
738 y += image_y;
739
740 if (!intelEmitCopyBlit(intel,
741 mt->region->cpp,
742 mt->region->pitch, mt->region->bo,
743 0, mt->region->tiling,
744 map->stride / mt->region->cpp, map->bo,
745 0, I915_TILING_NONE,
746 x, y,
747 0, 0,
748 map->w, map->h,
749 GL_COPY)) {
750 fprintf(stderr, "Failed to blit\n");
751 goto fail;
752 }
753
754 intel_batchbuffer_flush(intel);
755 ret = drm_intel_bo_map(map->bo, (map->mode & GL_MAP_WRITE_BIT) != 0);
756 if (ret) {
757 fprintf(stderr, "Failed to map blit temporary\n");
758 goto fail;
759 }
760
761 map->ptr = map->bo->virtual;
762
763 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__,
764 map->x, map->y, map->w, map->h,
765 mt, _mesa_get_format_name(mt->format),
766 x, y, map->ptr, map->stride);
767
768 return;
769
770 fail:
771 drm_intel_bo_unreference(map->bo);
772 map->ptr = NULL;
773 map->stride = 0;
774 }
775
776 static void
777 intel_miptree_unmap_blit(struct intel_context *intel,
778 struct intel_mipmap_tree *mt,
779 struct intel_miptree_map *map,
780 unsigned int level,
781 unsigned int slice)
782 {
783 assert(!(map->mode & GL_MAP_WRITE_BIT));
784
785 drm_intel_bo_unmap(map->bo);
786 drm_intel_bo_unreference(map->bo);
787 }
788
789 static void
790 intel_miptree_map_s8(struct intel_context *intel,
791 struct intel_mipmap_tree *mt,
792 struct intel_miptree_map *map,
793 unsigned int level, unsigned int slice)
794 {
795 map->stride = map->w;
796 map->buffer = map->ptr = malloc(map->stride * map->h);
797 if (!map->buffer)
798 return;
799
800 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
801 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
802 * invalidate is set, since we'll be writing the whole rectangle from our
803 * temporary buffer back out.
804 */
805 if (!(map->mode & GL_MAP_INVALIDATE_RANGE_BIT)) {
806 uint8_t *untiled_s8_map = map->ptr;
807 uint8_t *tiled_s8_map = intel_region_map(intel, mt->region,
808 GL_MAP_READ_BIT);
809 unsigned int image_x, image_y;
810
811 intel_miptree_get_image_offset(mt, level, 0, slice, &image_x, &image_y);
812
813 for (uint32_t y = 0; y < map->h; y++) {
814 for (uint32_t x = 0; x < map->w; x++) {
815 ptrdiff_t offset = intel_offset_S8(mt->region->pitch,
816 x + image_x + map->x,
817 y + image_y + map->y);
818 untiled_s8_map[y * map->w + x] = tiled_s8_map[offset];
819 }
820 }
821
822 intel_region_unmap(intel, mt->region);
823
824 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __FUNCTION__,
825 map->x, map->y, map->w, map->h,
826 mt, map->x + image_x, map->y + image_y, map->ptr, map->stride);
827 } else {
828 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__,
829 map->x, map->y, map->w, map->h,
830 mt, map->ptr, map->stride);
831 }
832 }
833
834 static void
835 intel_miptree_unmap_s8(struct intel_context *intel,
836 struct intel_mipmap_tree *mt,
837 struct intel_miptree_map *map,
838 unsigned int level,
839 unsigned int slice)
840 {
841 if (map->mode & GL_MAP_WRITE_BIT) {
842 unsigned int image_x, image_y;
843 uint8_t *untiled_s8_map = map->ptr;
844 uint8_t *tiled_s8_map = intel_region_map(intel, mt->region, map->mode);
845
846 intel_miptree_get_image_offset(mt, level, 0, slice, &image_x, &image_y);
847
848 for (uint32_t y = 0; y < map->h; y++) {
849 for (uint32_t x = 0; x < map->w; x++) {
850 ptrdiff_t offset = intel_offset_S8(mt->region->pitch,
851 x + map->x,
852 y + map->y);
853 tiled_s8_map[offset] = untiled_s8_map[y * map->w + x];
854 }
855 }
856
857 intel_region_unmap(intel, mt->region);
858 }
859
860 free(map->buffer);
861 }
862
863 /**
864 * Mapping function for packed depth/stencil miptrees backed by real separate
865 * miptrees for depth and stencil.
866 *
867 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
868 * separate from the depth buffer. Yet at the GL API level, we have to expose
869 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
870 * be able to map that memory for texture storage and glReadPixels-type
871 * operations. We give Mesa core that access by mallocing a temporary and
872 * copying the data between the actual backing store and the temporary.
873 */
874 static void
875 intel_miptree_map_depthstencil(struct intel_context *intel,
876 struct intel_mipmap_tree *mt,
877 struct intel_miptree_map *map,
878 unsigned int level, unsigned int slice)
879 {
880 struct intel_mipmap_tree *z_mt = mt;
881 struct intel_mipmap_tree *s_mt = mt->stencil_mt;
882 bool map_z32f_x24s8 = mt->format == MESA_FORMAT_Z32_FLOAT;
883 int packed_bpp = map_z32f_x24s8 ? 8 : 4;
884
885 map->stride = map->w * packed_bpp;
886 map->buffer = map->ptr = malloc(map->stride * map->h);
887 if (!map->buffer)
888 return;
889
890 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
891 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
892 * invalidate is set, since we'll be writing the whole rectangle from our
893 * temporary buffer back out.
894 */
895 if (!(map->mode & GL_MAP_INVALIDATE_RANGE_BIT)) {
896 uint32_t *packed_map = map->ptr;
897 uint8_t *s_map = intel_region_map(intel, s_mt->region, GL_MAP_READ_BIT);
898 uint32_t *z_map = intel_region_map(intel, z_mt->region, GL_MAP_READ_BIT);
899 unsigned int s_image_x, s_image_y;
900 unsigned int z_image_x, z_image_y;
901
902 intel_miptree_get_image_offset(s_mt, level, 0, slice,
903 &s_image_x, &s_image_y);
904 intel_miptree_get_image_offset(z_mt, level, 0, slice,
905 &z_image_x, &z_image_y);
906
907 for (uint32_t y = 0; y < map->h; y++) {
908 for (uint32_t x = 0; x < map->w; x++) {
909 int map_x = map->x + x, map_y = map->y + y;
910 ptrdiff_t s_offset = intel_offset_S8(s_mt->region->pitch,
911 map_x + s_image_x,
912 map_y + s_image_y);
913 ptrdiff_t z_offset = ((map_y + z_image_y) * z_mt->region->pitch +
914 (map_x + z_image_x));
915 uint8_t s = s_map[s_offset];
916 uint32_t z = z_map[z_offset];
917
918 if (map_z32f_x24s8) {
919 packed_map[(y * map->w + x) * 2 + 0] = z;
920 packed_map[(y * map->w + x) * 2 + 1] = s;
921 } else {
922 packed_map[y * map->w + x] = (s << 24) | (z & 0x00ffffff);
923 }
924 }
925 }
926
927 intel_region_unmap(intel, s_mt->region);
928 intel_region_unmap(intel, z_mt->region);
929
930 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
931 __FUNCTION__,
932 map->x, map->y, map->w, map->h,
933 z_mt, map->x + z_image_x, map->y + z_image_y,
934 s_mt, map->x + s_image_x, map->y + s_image_y,
935 map->ptr, map->stride);
936 } else {
937 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__,
938 map->x, map->y, map->w, map->h,
939 mt, map->ptr, map->stride);
940 }
941 }
942
943 static void
944 intel_miptree_unmap_depthstencil(struct intel_context *intel,
945 struct intel_mipmap_tree *mt,
946 struct intel_miptree_map *map,
947 unsigned int level,
948 unsigned int slice)
949 {
950 struct intel_mipmap_tree *z_mt = mt;
951 struct intel_mipmap_tree *s_mt = mt->stencil_mt;
952 bool map_z32f_x24s8 = mt->format == MESA_FORMAT_Z32_FLOAT;
953
954 if (map->mode & GL_MAP_WRITE_BIT) {
955 uint32_t *packed_map = map->ptr;
956 uint8_t *s_map = intel_region_map(intel, s_mt->region, map->mode);
957 uint32_t *z_map = intel_region_map(intel, z_mt->region, map->mode);
958 unsigned int s_image_x, s_image_y;
959 unsigned int z_image_x, z_image_y;
960
961 intel_miptree_get_image_offset(s_mt, level, 0, slice,
962 &s_image_x, &s_image_y);
963 intel_miptree_get_image_offset(z_mt, level, 0, slice,
964 &z_image_x, &z_image_y);
965
966 for (uint32_t y = 0; y < map->h; y++) {
967 for (uint32_t x = 0; x < map->w; x++) {
968 ptrdiff_t s_offset = intel_offset_S8(s_mt->region->pitch,
969 x + s_image_x + map->x,
970 y + s_image_y + map->y);
971 ptrdiff_t z_offset = ((y + z_image_y) * z_mt->region->pitch +
972 (x + z_image_x));
973
974 if (map_z32f_x24s8) {
975 z_map[z_offset] = packed_map[(y * map->w + x) * 2 + 0];
976 s_map[s_offset] = packed_map[(y * map->w + x) * 2 + 1];
977 } else {
978 uint32_t packed = packed_map[y * map->w + x];
979 s_map[s_offset] = packed >> 24;
980 z_map[z_offset] = packed;
981 }
982 }
983 }
984
985 intel_region_unmap(intel, s_mt->region);
986 intel_region_unmap(intel, z_mt->region);
987
988 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
989 __FUNCTION__,
990 map->x, map->y, map->w, map->h,
991 z_mt, _mesa_get_format_name(z_mt->format),
992 map->x + z_image_x, map->y + z_image_y,
993 s_mt, map->x + s_image_x, map->y + s_image_y,
994 map->ptr, map->stride);
995 }
996
997 free(map->buffer);
998 }
999
1000 void
1001 intel_miptree_map(struct intel_context *intel,
1002 struct intel_mipmap_tree *mt,
1003 unsigned int level,
1004 unsigned int slice,
1005 unsigned int x,
1006 unsigned int y,
1007 unsigned int w,
1008 unsigned int h,
1009 GLbitfield mode,
1010 void **out_ptr,
1011 int *out_stride)
1012 {
1013 struct intel_miptree_map *map;
1014
1015 map = calloc(1, sizeof(struct intel_miptree_map));
1016 if (!map){
1017 *out_ptr = NULL;
1018 *out_stride = 0;
1019 return;
1020 }
1021
1022 assert(!mt->level[level].slice[slice].map);
1023 mt->level[level].slice[slice].map = map;
1024 map->mode = mode;
1025 map->x = x;
1026 map->y = y;
1027 map->w = w;
1028 map->h = h;
1029
1030 intel_miptree_slice_resolve_depth(intel, mt, level, slice);
1031 if (map->mode & GL_MAP_WRITE_BIT) {
1032 intel_miptree_slice_set_needs_hiz_resolve(mt, level, slice);
1033 }
1034
1035 if (mt->format == MESA_FORMAT_S8) {
1036 intel_miptree_map_s8(intel, mt, map, level, slice);
1037 } else if (mt->stencil_mt) {
1038 intel_miptree_map_depthstencil(intel, mt, map, level, slice);
1039 } else if (intel->gen >= 6 &&
1040 !(mode & GL_MAP_WRITE_BIT) &&
1041 !mt->compressed &&
1042 mt->region->tiling == I915_TILING_X) {
1043 intel_miptree_map_blit(intel, mt, map, level, slice);
1044 } else {
1045 intel_miptree_map_gtt(intel, mt, map, level, slice);
1046 }
1047
1048 *out_ptr = map->ptr;
1049 *out_stride = map->stride;
1050 }
1051
1052 void
1053 intel_miptree_unmap(struct intel_context *intel,
1054 struct intel_mipmap_tree *mt,
1055 unsigned int level,
1056 unsigned int slice)
1057 {
1058 struct intel_miptree_map *map = mt->level[level].slice[slice].map;
1059
1060 if (!map)
1061 return;
1062
1063 DBG("%s: mt %p (%s) level %d slice %d\n", __FUNCTION__,
1064 mt, _mesa_get_format_name(mt->format), level, slice);
1065
1066 if (mt->format == MESA_FORMAT_S8) {
1067 intel_miptree_unmap_s8(intel, mt, map, level, slice);
1068 } else if (mt->stencil_mt) {
1069 intel_miptree_unmap_depthstencil(intel, mt, map, level, slice);
1070 } else if (map->bo) {
1071 intel_miptree_unmap_blit(intel, mt, map, level, slice);
1072 } else {
1073 intel_miptree_unmap_gtt(intel, mt, map, level, slice);
1074 }
1075
1076 mt->level[level].slice[slice].map = NULL;
1077 free(map);
1078 }