1 /**************************************************************************
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include <GL/internal/dri_interface.h>
31 #include "intel_batchbuffer.h"
32 #include "intel_context.h"
33 #include "intel_mipmap_tree.h"
34 #include "intel_regions.h"
35 #include "intel_resolve_map.h"
36 #include "intel_span.h"
37 #include "intel_tex_layout.h"
38 #include "intel_tex.h"
39 #include "intel_blit.h"
42 #include "brw_blorp.h"
45 #include "main/enums.h"
46 #include "main/formats.h"
47 #include "main/glformats.h"
48 #include "main/texcompress_etc.h"
49 #include "main/teximage.h"
51 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
54 target_to_target(GLenum target
)
57 case GL_TEXTURE_CUBE_MAP_POSITIVE_X_ARB
:
58 case GL_TEXTURE_CUBE_MAP_NEGATIVE_X_ARB
:
59 case GL_TEXTURE_CUBE_MAP_POSITIVE_Y_ARB
:
60 case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y_ARB
:
61 case GL_TEXTURE_CUBE_MAP_POSITIVE_Z_ARB
:
62 case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z_ARB
:
63 return GL_TEXTURE_CUBE_MAP_ARB
;
71 * Determine which MSAA layout should be used by the MSAA surface being
72 * created, based on the chip generation and the surface type.
74 static enum intel_msaa_layout
75 compute_msaa_layout(struct intel_context
*intel
, gl_format format
)
77 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
79 return INTEL_MSAA_LAYOUT_IMS
;
81 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
82 switch (_mesa_get_format_base_format(format
)) {
83 case GL_DEPTH_COMPONENT
:
84 case GL_STENCIL_INDEX
:
85 case GL_DEPTH_STENCIL
:
86 return INTEL_MSAA_LAYOUT_IMS
;
88 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
90 * This field must be set to 0 for all SINT MSRTs when all RT channels
93 * In practice this means that we have to disable MCS for all signed
94 * integer MSAA buffers. The alternative, to disable MCS only when one
95 * of the render target channels is disabled, is impractical because it
96 * would require converting between CMS and UMS MSAA layouts on the fly,
99 if (_mesa_get_format_datatype(format
) == GL_INT
) {
100 /* TODO: is this workaround needed for future chipsets? */
101 assert(intel
->gen
== 7);
102 return INTEL_MSAA_LAYOUT_UMS
;
104 return INTEL_MSAA_LAYOUT_CMS
;
111 * @param for_region Indicates that the caller is
112 * intel_miptree_create_for_region(). If true, then do not create
115 static struct intel_mipmap_tree
*
116 intel_miptree_create_internal(struct intel_context
*intel
,
127 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
128 int compress_byte
= 0;
130 DBG("%s target %s format %s level %d..%d <-- %p\n", __FUNCTION__
,
131 _mesa_lookup_enum_by_nr(target
),
132 _mesa_get_format_name(format
),
133 first_level
, last_level
, mt
);
135 if (_mesa_is_format_compressed(format
))
136 compress_byte
= intel_compressed_num_bytes(format
);
138 mt
->target
= target_to_target(target
);
140 mt
->first_level
= first_level
;
141 mt
->last_level
= last_level
;
142 mt
->logical_width0
= width0
;
143 mt
->logical_height0
= height0
;
144 mt
->logical_depth0
= depth0
;
145 mt
->cpp
= compress_byte
? compress_byte
: _mesa_get_format_bytes(mt
->format
);
146 mt
->num_samples
= num_samples
;
147 mt
->compressed
= compress_byte
? 1 : 0;
148 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
151 if (num_samples
> 1) {
152 /* Adjust width/height/depth for MSAA */
153 mt
->msaa_layout
= compute_msaa_layout(intel
, format
);
154 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
155 /* In the Sandy Bridge PRM, volume 4, part 1, page 31, it says:
157 * "Any of the other messages (sample*, LOD, load4) used with a
158 * (4x) multisampled surface will in-effect sample a surface with
159 * double the height and width as that indicated in the surface
160 * state. Each pixel position on the original-sized surface is
161 * replaced with a 2x2 of samples with the following arrangement:
166 * Thus, when sampling from a multisampled texture, it behaves as
167 * though the layout in memory for (x,y,sample) is:
169 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
170 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
172 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
173 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
175 * However, the actual layout of multisampled data in memory is:
177 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
178 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
180 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
181 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
183 * This pattern repeats for each 2x2 pixel block.
185 * As a result, when calculating the size of our 4-sample buffer for
186 * an odd width or height, we have to align before scaling up because
187 * sample 3 is in that bottom right 2x2 block.
189 switch (num_samples
) {
191 width0
= ALIGN(width0
, 2) * 2;
192 height0
= ALIGN(height0
, 2) * 2;
195 width0
= ALIGN(width0
, 2) * 4;
196 height0
= ALIGN(height0
, 2) * 2;
199 /* num_samples should already have been quantized to 0, 1, 4, or
205 /* Non-interleaved */
206 depth0
*= num_samples
;
210 /* array_spacing_lod0 is only used for non-IMS MSAA surfaces. TODO: can we
213 switch (mt
->msaa_layout
) {
214 case INTEL_MSAA_LAYOUT_NONE
:
215 case INTEL_MSAA_LAYOUT_IMS
:
216 mt
->array_spacing_lod0
= false;
218 case INTEL_MSAA_LAYOUT_UMS
:
219 case INTEL_MSAA_LAYOUT_CMS
:
220 mt
->array_spacing_lod0
= true;
224 if (target
== GL_TEXTURE_CUBE_MAP
) {
229 mt
->physical_width0
= width0
;
230 mt
->physical_height0
= height0
;
231 mt
->physical_depth0
= depth0
;
234 _mesa_is_depthstencil_format(_mesa_get_format_base_format(format
)) &&
235 (intel
->must_use_separate_stencil
||
236 (intel
->has_separate_stencil
&&
237 intel
->vtbl
.is_hiz_depth_format(intel
, format
)))) {
238 mt
->stencil_mt
= intel_miptree_create(intel
,
248 false /* force_y_tiling */);
249 if (!mt
->stencil_mt
) {
250 intel_miptree_release(&mt
);
254 /* Fix up the Z miptree format for how we're splitting out separate
255 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
257 if (mt
->format
== MESA_FORMAT_S8_Z24
) {
258 mt
->format
= MESA_FORMAT_X8_Z24
;
259 } else if (mt
->format
== MESA_FORMAT_Z32_FLOAT_X24S8
) {
260 mt
->format
= MESA_FORMAT_Z32_FLOAT
;
263 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
264 _mesa_get_format_name(mt
->format
));
268 intel_get_texture_alignment_unit(intel
, mt
->format
,
269 &mt
->align_w
, &mt
->align_h
);
274 i945_miptree_layout(mt
);
276 i915_miptree_layout(mt
);
278 brw_miptree_layout(intel
, mt
);
285 struct intel_mipmap_tree
*
286 intel_miptree_create(struct intel_context
*intel
,
294 bool expect_accelerated_upload
,
298 struct intel_mipmap_tree
*mt
;
299 uint32_t tiling
= I915_TILING_NONE
;
301 gl_format tex_format
= format
;
302 gl_format etc_format
= MESA_FORMAT_NONE
;
303 GLuint total_width
, total_height
;
306 case MESA_FORMAT_ETC1_RGB8
:
307 format
= MESA_FORMAT_RGBX8888_REV
;
309 case MESA_FORMAT_ETC2_RGB8
:
310 format
= MESA_FORMAT_RGBX8888_REV
;
312 case MESA_FORMAT_ETC2_SRGB8
:
313 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
314 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
315 format
= MESA_FORMAT_SARGB8
;
317 case MESA_FORMAT_ETC2_RGBA8_EAC
:
318 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
319 format
= MESA_FORMAT_RGBA8888_REV
;
321 case MESA_FORMAT_ETC2_R11_EAC
:
322 format
= MESA_FORMAT_R16
;
324 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
325 format
= MESA_FORMAT_SIGNED_R16
;
327 case MESA_FORMAT_ETC2_RG11_EAC
:
328 format
= MESA_FORMAT_RG1616
;
330 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
331 format
= MESA_FORMAT_SIGNED_GR1616
;
334 /* Non ETC1 / ETC2 format */
338 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
339 base_format
= _mesa_get_format_base_format(format
);
341 if (num_samples
> 1) {
342 /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
345 * [DevSNB+]: For multi-sample render targets, this field must be
346 * 1. MSRTs can only be tiled.
348 * Our usual reason for preferring X tiling (fast blits using the
349 * blitting engine) doesn't apply to MSAA, since we'll generally be
350 * downsampling or upsampling when blitting between the MSAA buffer
351 * and another buffer, and the blitting engine doesn't support that.
352 * So use Y tiling, since it makes better use of the cache.
354 force_y_tiling
= true;
357 if (intel
->use_texture_tiling
&& !_mesa_is_format_compressed(format
)) {
358 if (intel
->gen
>= 4 &&
359 (base_format
== GL_DEPTH_COMPONENT
||
360 base_format
== GL_DEPTH_STENCIL_EXT
))
361 tiling
= I915_TILING_Y
;
362 else if (force_y_tiling
) {
363 tiling
= I915_TILING_Y
;
364 } else if (width0
>= 64)
365 tiling
= I915_TILING_X
;
368 mt
= intel_miptree_create_internal(intel
, target
, format
,
369 first_level
, last_level
, width0
,
373 * pitch == 0 || height == 0 indicates the null texture
375 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
376 intel_miptree_release(&mt
);
380 total_width
= mt
->total_width
;
381 total_height
= mt
->total_height
;
383 if (format
== MESA_FORMAT_S8
) {
384 /* The stencil buffer is W tiled. However, we request from the kernel a
385 * non-tiled buffer because the GTT is incapable of W fencing. So round
386 * up the width and height to match the size of W tiles (64x64).
388 tiling
= I915_TILING_NONE
;
389 total_width
= ALIGN(total_width
, 64);
390 total_height
= ALIGN(total_height
, 64);
393 mt
->wraps_etc
= (etc_format
!= MESA_FORMAT_NONE
) ? true : false;
394 mt
->etc_format
= etc_format
;
395 mt
->region
= intel_region_alloc(intel
->intelScreen
,
400 expect_accelerated_upload
);
404 intel_miptree_release(&mt
);
412 struct intel_mipmap_tree
*
413 intel_miptree_create_for_region(struct intel_context
*intel
,
416 struct intel_region
*region
)
418 struct intel_mipmap_tree
*mt
;
420 mt
= intel_miptree_create_internal(intel
, target
, format
,
422 region
->width
, region
->height
, 1,
423 true, 0 /* num_samples */);
427 intel_region_reference(&mt
->region
, region
);
434 * For a singlesample DRI2 buffer, this simply wraps the given region with a miptree.
436 * For a multisample DRI2 buffer, this wraps the given region with
437 * a singlesample miptree, then creates a multisample miptree into which the
438 * singlesample miptree is embedded as a child.
440 struct intel_mipmap_tree
*
441 intel_miptree_create_for_dri2_buffer(struct intel_context
*intel
,
442 unsigned dri_attachment
,
444 uint32_t num_samples
,
445 struct intel_region
*region
)
447 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
448 struct intel_mipmap_tree
*multisample_mt
= NULL
;
449 GLenum base_format
= _mesa_get_format_base_format(format
);
451 /* Only the front and back buffers, which are color buffers, are shared
454 assert(dri_attachment
== __DRI_BUFFER_BACK_LEFT
||
455 dri_attachment
== __DRI_BUFFER_FRONT_LEFT
||
456 dri_attachment
== __DRI_BUFFER_FAKE_FRONT_LEFT
);
457 assert(base_format
== GL_RGB
|| base_format
== GL_RGBA
);
459 singlesample_mt
= intel_miptree_create_for_region(intel
, GL_TEXTURE_2D
,
461 if (!singlesample_mt
)
464 if (num_samples
== 0)
465 return singlesample_mt
;
467 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
472 if (!multisample_mt
) {
473 intel_miptree_release(&singlesample_mt
);
477 multisample_mt
->singlesample_mt
= singlesample_mt
;
478 multisample_mt
->need_downsample
= false;
480 if (intel
->is_front_buffer_rendering
&&
481 (dri_attachment
== __DRI_BUFFER_FRONT_LEFT
||
482 dri_attachment
== __DRI_BUFFER_FAKE_FRONT_LEFT
)) {
483 intel_miptree_upsample(intel
, multisample_mt
);
486 return multisample_mt
;
489 struct intel_mipmap_tree
*
490 intel_miptree_create_for_renderbuffer(struct intel_context
*intel
,
494 uint32_t num_samples
)
496 struct intel_mipmap_tree
*mt
;
500 mt
= intel_miptree_create(intel
, GL_TEXTURE_2D
, format
, 0, 0,
501 width
, height
, depth
, true, num_samples
,
502 false /* force_y_tiling */);
506 if (intel
->vtbl
.is_hiz_depth_format(intel
, format
)) {
507 ok
= intel_miptree_alloc_hiz(intel
, mt
, num_samples
);
512 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
513 ok
= intel_miptree_alloc_mcs(intel
, mt
, num_samples
);
521 intel_miptree_release(&mt
);
526 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
527 struct intel_mipmap_tree
*src
)
532 intel_miptree_release(dst
);
536 DBG("%s %p refcount now %d\n", __FUNCTION__
, src
, src
->refcount
);
544 intel_miptree_release(struct intel_mipmap_tree
**mt
)
549 DBG("%s %p refcount will be %d\n", __FUNCTION__
, *mt
, (*mt
)->refcount
- 1);
550 if (--(*mt
)->refcount
<= 0) {
553 DBG("%s deleting %p\n", __FUNCTION__
, *mt
);
555 intel_region_release(&((*mt
)->region
));
556 intel_miptree_release(&(*mt
)->stencil_mt
);
557 intel_miptree_release(&(*mt
)->hiz_mt
);
558 intel_miptree_release(&(*mt
)->mcs_mt
);
559 intel_miptree_release(&(*mt
)->singlesample_mt
);
560 intel_resolve_map_clear(&(*mt
)->hiz_map
);
562 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
563 free((*mt
)->level
[i
].slice
);
572 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
573 int *width
, int *height
, int *depth
)
575 switch (image
->TexObject
->Target
) {
576 case GL_TEXTURE_1D_ARRAY
:
577 *width
= image
->Width
;
579 *depth
= image
->Height
;
582 *width
= image
->Width
;
583 *height
= image
->Height
;
584 *depth
= image
->Depth
;
590 * Can the image be pulled into a unified mipmap tree? This mirrors
591 * the completeness test in a lot of ways.
593 * Not sure whether I want to pass gl_texture_image here.
596 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
597 struct gl_texture_image
*image
)
599 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
600 GLuint level
= intelImage
->base
.Base
.Level
;
601 int width
, height
, depth
;
603 /* glTexImage* choose the texture object based on the target passed in, and
604 * objects can't change targets over their lifetimes, so this should be
607 assert(target_to_target(image
->TexObject
->Target
) == mt
->target
);
609 gl_format mt_format
= mt
->format
;
610 if (mt
->format
== MESA_FORMAT_X8_Z24
&& mt
->stencil_mt
)
611 mt_format
= MESA_FORMAT_S8_Z24
;
612 if (mt
->format
== MESA_FORMAT_Z32_FLOAT
&& mt
->stencil_mt
)
613 mt_format
= MESA_FORMAT_Z32_FLOAT_X24S8
;
614 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
615 mt_format
= mt
->etc_format
;
617 if (image
->TexFormat
!= mt_format
)
620 intel_miptree_get_dimensions_for_image(image
, &width
, &height
, &depth
);
622 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
625 /* Test image dimensions against the base level image adjusted for
626 * minification. This will also catch images not present in the
627 * tree, changed targets, etc.
629 if (width
!= mt
->level
[level
].width
||
630 height
!= mt
->level
[level
].height
||
631 depth
!= mt
->level
[level
].depth
)
639 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
642 GLuint w
, GLuint h
, GLuint d
)
644 mt
->level
[level
].width
= w
;
645 mt
->level
[level
].height
= h
;
646 mt
->level
[level
].depth
= d
;
647 mt
->level
[level
].level_x
= x
;
648 mt
->level
[level
].level_y
= y
;
650 DBG("%s level %d size: %d,%d,%d offset %d,%d\n", __FUNCTION__
,
651 level
, w
, h
, d
, x
, y
);
653 assert(mt
->level
[level
].slice
== NULL
);
655 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
656 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
657 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
662 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
663 GLuint level
, GLuint img
,
666 if (img
== 0 && level
== 0)
667 assert(x
== 0 && y
== 0);
669 assert(img
< mt
->level
[level
].depth
);
671 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
672 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
674 DBG("%s level %d img %d pos %d,%d\n",
675 __FUNCTION__
, level
, img
,
676 mt
->level
[level
].slice
[img
].x_offset
,
677 mt
->level
[level
].slice
[img
].y_offset
);
681 intel_miptree_get_image_offset(struct intel_mipmap_tree
*mt
,
682 GLuint level
, GLuint slice
,
683 GLuint
*x
, GLuint
*y
)
685 assert(slice
< mt
->level
[level
].depth
);
687 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
688 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
692 intel_miptree_copy_slice(struct intel_context
*intel
,
693 struct intel_mipmap_tree
*dst_mt
,
694 struct intel_mipmap_tree
*src_mt
,
700 gl_format format
= src_mt
->format
;
701 uint32_t width
= src_mt
->level
[level
].width
;
702 uint32_t height
= src_mt
->level
[level
].height
;
710 assert(depth
< src_mt
->level
[level
].depth
);
712 if (dst_mt
->compressed
) {
713 height
= ALIGN(height
, dst_mt
->align_h
) / dst_mt
->align_h
;
714 width
= ALIGN(width
, dst_mt
->align_w
);
717 uint32_t dst_x
, dst_y
, src_x
, src_y
;
718 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
719 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
721 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
722 _mesa_get_format_name(src_mt
->format
),
723 src_mt
, src_x
, src_y
, src_mt
->region
->pitch
,
724 _mesa_get_format_name(dst_mt
->format
),
725 dst_mt
, dst_x
, dst_y
, dst_mt
->region
->pitch
,
728 if (!intelEmitCopyBlit(intel
,
730 src_mt
->region
->pitch
, src_mt
->region
->bo
,
731 0, src_mt
->region
->tiling
,
732 dst_mt
->region
->pitch
, dst_mt
->region
->bo
,
733 0, dst_mt
->region
->tiling
,
739 fallback_debug("miptree validate blit for %s failed\n",
740 _mesa_get_format_name(format
));
741 void *dst
= intel_region_map(intel
, dst_mt
->region
, GL_MAP_WRITE_BIT
);
742 void *src
= intel_region_map(intel
, src_mt
->region
, GL_MAP_READ_BIT
);
746 dst_mt
->region
->pitch
,
749 src
, src_mt
->region
->pitch
,
752 intel_region_unmap(intel
, dst_mt
->region
);
753 intel_region_unmap(intel
, src_mt
->region
);
756 if (src_mt
->stencil_mt
) {
757 intel_miptree_copy_slice(intel
,
758 dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
764 * Copies the image's current data to the given miptree, and associates that
765 * miptree with the image.
768 intel_miptree_copy_teximage(struct intel_context
*intel
,
769 struct intel_texture_image
*intelImage
,
770 struct intel_mipmap_tree
*dst_mt
)
772 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
773 struct intel_texture_object
*intel_obj
=
774 intel_texture_object(intelImage
->base
.Base
.TexObject
);
775 int level
= intelImage
->base
.Base
.Level
;
776 int face
= intelImage
->base
.Base
.Face
;
777 GLuint depth
= intelImage
->base
.Base
.Depth
;
779 for (int slice
= 0; slice
< depth
; slice
++) {
780 intel_miptree_copy_slice(intel
, dst_mt
, src_mt
, level
, face
, slice
);
783 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
784 intel_obj
->needs_validate
= true;
788 intel_miptree_alloc_mcs(struct intel_context
*intel
,
789 struct intel_mipmap_tree
*mt
,
792 assert(mt
->mcs_mt
== NULL
);
793 assert(intel
->gen
>= 7); /* MCS only used on Gen7+ */
795 /* Choose the correct format for the MCS buffer. All that really matters
796 * is that we allocate the right buffer size, since we'll always be
797 * accessing this miptree using MCS-specific hardware mechanisms, which
798 * infer the correct format based on num_samples.
801 switch (num_samples
) {
803 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
806 format
= MESA_FORMAT_R8
;
809 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
810 * for each sample, plus 8 padding bits).
812 format
= MESA_FORMAT_R_UINT32
;
815 assert(!"Unrecognized sample count in intel_miptree_alloc_mcs");
819 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
821 * "The MCS surface must be stored as Tile Y."
823 mt
->mcs_mt
= intel_miptree_create(intel
,
833 true /* force_y_tiling */);
835 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
837 * When MCS buffer is enabled and bound to MSRT, it is required that it
838 * is cleared prior to any rendering.
840 * Since we don't use the MCS buffer for any purpose other than rendering,
841 * it makes sense to just clear it immediately upon allocation.
843 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
845 void *data
= intel_region_map(intel
, mt
->mcs_mt
->region
, 0);
846 memset(data
, 0xff, mt
->mcs_mt
->region
->bo
->size
);
847 intel_region_unmap(intel
, mt
->mcs_mt
->region
);
853 intel_miptree_alloc_hiz(struct intel_context
*intel
,
854 struct intel_mipmap_tree
*mt
,
857 assert(mt
->hiz_mt
== NULL
);
858 mt
->hiz_mt
= intel_miptree_create(intel
,
868 false /* force_y_tiling */);
873 /* Mark that all slices need a HiZ resolve. */
874 struct intel_resolve_map
*head
= &mt
->hiz_map
;
875 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
876 for (int layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
877 head
->next
= malloc(sizeof(*head
->next
));
878 head
->next
->prev
= head
;
879 head
->next
->next
= NULL
;
884 head
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
892 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
896 intel_miptree_check_level_layer(mt
, level
, layer
);
901 intel_resolve_map_set(&mt
->hiz_map
,
902 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
907 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
911 intel_miptree_check_level_layer(mt
, level
, layer
);
916 intel_resolve_map_set(&mt
->hiz_map
,
917 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
921 intel_miptree_slice_resolve(struct intel_context
*intel
,
922 struct intel_mipmap_tree
*mt
,
925 enum gen6_hiz_op need
)
927 intel_miptree_check_level_layer(mt
, level
, layer
);
929 struct intel_resolve_map
*item
=
930 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
932 if (!item
|| item
->need
!= need
)
935 intel_hiz_exec(intel
, mt
, level
, layer
, need
);
936 intel_resolve_map_remove(item
);
941 intel_miptree_slice_resolve_hiz(struct intel_context
*intel
,
942 struct intel_mipmap_tree
*mt
,
946 return intel_miptree_slice_resolve(intel
, mt
, level
, layer
,
947 GEN6_HIZ_OP_HIZ_RESOLVE
);
951 intel_miptree_slice_resolve_depth(struct intel_context
*intel
,
952 struct intel_mipmap_tree
*mt
,
956 return intel_miptree_slice_resolve(intel
, mt
, level
, layer
,
957 GEN6_HIZ_OP_DEPTH_RESOLVE
);
961 intel_miptree_all_slices_resolve(struct intel_context
*intel
,
962 struct intel_mipmap_tree
*mt
,
963 enum gen6_hiz_op need
)
965 bool did_resolve
= false;
966 struct intel_resolve_map
*i
, *next
;
968 for (i
= mt
->hiz_map
.next
; i
; i
= next
) {
973 intel_hiz_exec(intel
, mt
, i
->level
, i
->layer
, need
);
974 intel_resolve_map_remove(i
);
982 intel_miptree_all_slices_resolve_hiz(struct intel_context
*intel
,
983 struct intel_mipmap_tree
*mt
)
985 return intel_miptree_all_slices_resolve(intel
, mt
,
986 GEN6_HIZ_OP_HIZ_RESOLVE
);
990 intel_miptree_all_slices_resolve_depth(struct intel_context
*intel
,
991 struct intel_mipmap_tree
*mt
)
993 return intel_miptree_all_slices_resolve(intel
, mt
,
994 GEN6_HIZ_OP_DEPTH_RESOLVE
);
998 intel_miptree_updownsample(struct intel_context
*intel
,
999 struct intel_mipmap_tree
*src
,
1000 struct intel_mipmap_tree
*dst
,
1010 intel_miptree_slice_resolve_depth(intel
, src
, 0, 0);
1011 intel_miptree_slice_resolve_depth(intel
, dst
, 0, 0);
1013 brw_blorp_blit_miptrees(intel
,
1014 src
, 0 /* level */, 0 /* layer */,
1015 dst
, 0 /* level */, 0 /* layer */,
1019 false, false /*mirror x, y*/);
1021 if (src
->stencil_mt
) {
1022 brw_blorp_blit_miptrees(intel
,
1023 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
1024 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
1028 false, false /*mirror x, y*/);
1034 assert_is_flat(struct intel_mipmap_tree
*mt
)
1036 assert(mt
->target
== GL_TEXTURE_2D
);
1037 assert(mt
->first_level
== 0);
1038 assert(mt
->last_level
== 0);
1042 * \brief Downsample from mt to mt->singlesample_mt.
1044 * If the miptree needs no downsample, then skip.
1047 intel_miptree_downsample(struct intel_context
*intel
,
1048 struct intel_mipmap_tree
*mt
)
1050 /* Only flat, renderbuffer-like miptrees are supported. */
1053 if (!mt
->need_downsample
)
1055 intel_miptree_updownsample(intel
,
1056 mt
, mt
->singlesample_mt
,
1058 mt
->logical_height0
);
1059 mt
->need_downsample
= false;
1061 /* Strictly speaking, after a downsample on a depth miptree, a hiz
1062 * resolve is needed on the singlesample miptree. However, since the
1063 * singlesample miptree is never rendered to, the hiz resolve will never
1064 * occur. Therefore we do not mark the needed hiz resolve after
1070 * \brief Upsample from mt->singlesample_mt to mt.
1072 * The upsample is done unconditionally.
1075 intel_miptree_upsample(struct intel_context
*intel
,
1076 struct intel_mipmap_tree
*mt
)
1078 /* Only flat, renderbuffer-like miptrees are supported. */
1080 assert(!mt
->need_downsample
);
1082 intel_miptree_updownsample(intel
,
1083 mt
->singlesample_mt
, mt
,
1085 mt
->logical_height0
);
1086 intel_miptree_slice_set_needs_hiz_resolve(mt
, 0, 0);
1090 intel_miptree_map_gtt(struct intel_context
*intel
,
1091 struct intel_mipmap_tree
*mt
,
1092 struct intel_miptree_map
*map
,
1093 unsigned int level
, unsigned int slice
)
1095 unsigned int bw
, bh
;
1097 unsigned int image_x
, image_y
;
1101 /* For compressed formats, the stride is the number of bytes per
1102 * row of blocks. intel_miptree_get_image_offset() already does
1105 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
1106 assert(y
% bh
== 0);
1109 base
= intel_region_map(intel
, mt
->region
, map
->mode
);
1114 /* Note that in the case of cube maps, the caller must have passed the
1115 * slice number referencing the face.
1117 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1121 map
->stride
= mt
->region
->pitch
;
1122 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
1125 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1126 map
->x
, map
->y
, map
->w
, map
->h
,
1127 mt
, _mesa_get_format_name(mt
->format
),
1128 x
, y
, map
->ptr
, map
->stride
);
1132 intel_miptree_unmap_gtt(struct intel_context
*intel
,
1133 struct intel_mipmap_tree
*mt
,
1134 struct intel_miptree_map
*map
,
1138 intel_region_unmap(intel
, mt
->region
);
1142 intel_miptree_map_blit(struct intel_context
*intel
,
1143 struct intel_mipmap_tree
*mt
,
1144 struct intel_miptree_map
*map
,
1145 unsigned int level
, unsigned int slice
)
1147 unsigned int image_x
, image_y
;
1152 /* The blitter requires the pitch to be aligned to 4. */
1153 map
->stride
= ALIGN(map
->w
* mt
->region
->cpp
, 4);
1155 map
->bo
= drm_intel_bo_alloc(intel
->bufmgr
, "intel_miptree_map_blit() temp",
1156 map
->stride
* map
->h
, 4096);
1158 fprintf(stderr
, "Failed to allocate blit temporary\n");
1162 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1166 if (!intelEmitCopyBlit(intel
,
1168 mt
->region
->pitch
, mt
->region
->bo
,
1169 0, mt
->region
->tiling
,
1170 map
->stride
, map
->bo
,
1171 0, I915_TILING_NONE
,
1176 fprintf(stderr
, "Failed to blit\n");
1180 intel_batchbuffer_flush(intel
);
1181 ret
= drm_intel_bo_map(map
->bo
, (map
->mode
& GL_MAP_WRITE_BIT
) != 0);
1183 fprintf(stderr
, "Failed to map blit temporary\n");
1187 map
->ptr
= map
->bo
->virtual;
1189 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1190 map
->x
, map
->y
, map
->w
, map
->h
,
1191 mt
, _mesa_get_format_name(mt
->format
),
1192 x
, y
, map
->ptr
, map
->stride
);
1197 drm_intel_bo_unreference(map
->bo
);
1203 intel_miptree_unmap_blit(struct intel_context
*intel
,
1204 struct intel_mipmap_tree
*mt
,
1205 struct intel_miptree_map
*map
,
1209 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
1211 drm_intel_bo_unmap(map
->bo
);
1212 drm_intel_bo_unreference(map
->bo
);
1216 intel_miptree_map_s8(struct intel_context
*intel
,
1217 struct intel_mipmap_tree
*mt
,
1218 struct intel_miptree_map
*map
,
1219 unsigned int level
, unsigned int slice
)
1221 map
->stride
= map
->w
;
1222 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
1226 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1227 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1228 * invalidate is set, since we'll be writing the whole rectangle from our
1229 * temporary buffer back out.
1231 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
1232 uint8_t *untiled_s8_map
= map
->ptr
;
1233 uint8_t *tiled_s8_map
= intel_region_map(intel
, mt
->region
,
1235 unsigned int image_x
, image_y
;
1237 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1239 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1240 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1241 ptrdiff_t offset
= intel_offset_S8(mt
->region
->pitch
,
1242 x
+ image_x
+ map
->x
,
1243 y
+ image_y
+ map
->y
,
1244 intel
->has_swizzling
);
1245 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
1249 intel_region_unmap(intel
, mt
->region
);
1251 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __FUNCTION__
,
1252 map
->x
, map
->y
, map
->w
, map
->h
,
1253 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
1255 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
1256 map
->x
, map
->y
, map
->w
, map
->h
,
1257 mt
, map
->ptr
, map
->stride
);
1262 intel_miptree_unmap_s8(struct intel_context
*intel
,
1263 struct intel_mipmap_tree
*mt
,
1264 struct intel_miptree_map
*map
,
1268 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1269 unsigned int image_x
, image_y
;
1270 uint8_t *untiled_s8_map
= map
->ptr
;
1271 uint8_t *tiled_s8_map
= intel_region_map(intel
, mt
->region
, map
->mode
);
1273 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1275 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1276 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1277 ptrdiff_t offset
= intel_offset_S8(mt
->region
->pitch
,
1280 intel
->has_swizzling
);
1281 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
1285 intel_region_unmap(intel
, mt
->region
);
1292 intel_miptree_map_etc(struct intel_context
*intel
,
1293 struct intel_mipmap_tree
*mt
,
1294 struct intel_miptree_map
*map
,
1298 /* For justification see intel_mipmap_tree:wraps_etc.
1300 assert(mt
->wraps_etc
);
1302 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
1303 assert(mt
->format
== MESA_FORMAT_RGBX8888_REV
);
1306 assert(map
->mode
& GL_MAP_WRITE_BIT
);
1307 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
1309 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
1310 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
1311 map
->w
, map
->h
, 1));
1312 map
->ptr
= map
->buffer
;
1316 intel_miptree_unmap_etc(struct intel_context
*intel
,
1317 struct intel_mipmap_tree
*mt
,
1318 struct intel_miptree_map
*map
,
1324 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1329 uint8_t *dst
= intel_region_map(intel
, mt
->region
, map
->mode
)
1330 + image_y
* mt
->region
->pitch
1331 + image_x
* mt
->region
->cpp
;
1333 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
1334 _mesa_etc1_unpack_rgba8888(dst
, mt
->region
->pitch
,
1335 map
->ptr
, map
->stride
,
1338 _mesa_unpack_etc2_format(dst
, mt
->region
->pitch
,
1339 map
->ptr
, map
->stride
,
1340 map
->w
, map
->h
, mt
->etc_format
);
1342 intel_region_unmap(intel
, mt
->region
);
1347 * Mapping function for packed depth/stencil miptrees backed by real separate
1348 * miptrees for depth and stencil.
1350 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
1351 * separate from the depth buffer. Yet at the GL API level, we have to expose
1352 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
1353 * be able to map that memory for texture storage and glReadPixels-type
1354 * operations. We give Mesa core that access by mallocing a temporary and
1355 * copying the data between the actual backing store and the temporary.
1358 intel_miptree_map_depthstencil(struct intel_context
*intel
,
1359 struct intel_mipmap_tree
*mt
,
1360 struct intel_miptree_map
*map
,
1361 unsigned int level
, unsigned int slice
)
1363 struct intel_mipmap_tree
*z_mt
= mt
;
1364 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
1365 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z32_FLOAT
;
1366 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
1368 map
->stride
= map
->w
* packed_bpp
;
1369 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
1373 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1374 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1375 * invalidate is set, since we'll be writing the whole rectangle from our
1376 * temporary buffer back out.
1378 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
1379 uint32_t *packed_map
= map
->ptr
;
1380 uint8_t *s_map
= intel_region_map(intel
, s_mt
->region
, GL_MAP_READ_BIT
);
1381 uint32_t *z_map
= intel_region_map(intel
, z_mt
->region
, GL_MAP_READ_BIT
);
1382 unsigned int s_image_x
, s_image_y
;
1383 unsigned int z_image_x
, z_image_y
;
1385 intel_miptree_get_image_offset(s_mt
, level
, slice
,
1386 &s_image_x
, &s_image_y
);
1387 intel_miptree_get_image_offset(z_mt
, level
, slice
,
1388 &z_image_x
, &z_image_y
);
1390 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1391 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1392 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
1393 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->region
->pitch
,
1396 intel
->has_swizzling
);
1397 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
1398 (z_mt
->region
->pitch
/ 4) +
1399 (map_x
+ z_image_x
));
1400 uint8_t s
= s_map
[s_offset
];
1401 uint32_t z
= z_map
[z_offset
];
1403 if (map_z32f_x24s8
) {
1404 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
1405 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
1407 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
1412 intel_region_unmap(intel
, s_mt
->region
);
1413 intel_region_unmap(intel
, z_mt
->region
);
1415 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
1417 map
->x
, map
->y
, map
->w
, map
->h
,
1418 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
1419 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
1420 map
->ptr
, map
->stride
);
1422 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
1423 map
->x
, map
->y
, map
->w
, map
->h
,
1424 mt
, map
->ptr
, map
->stride
);
1429 intel_miptree_unmap_depthstencil(struct intel_context
*intel
,
1430 struct intel_mipmap_tree
*mt
,
1431 struct intel_miptree_map
*map
,
1435 struct intel_mipmap_tree
*z_mt
= mt
;
1436 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
1437 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z32_FLOAT
;
1439 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1440 uint32_t *packed_map
= map
->ptr
;
1441 uint8_t *s_map
= intel_region_map(intel
, s_mt
->region
, map
->mode
);
1442 uint32_t *z_map
= intel_region_map(intel
, z_mt
->region
, map
->mode
);
1443 unsigned int s_image_x
, s_image_y
;
1444 unsigned int z_image_x
, z_image_y
;
1446 intel_miptree_get_image_offset(s_mt
, level
, slice
,
1447 &s_image_x
, &s_image_y
);
1448 intel_miptree_get_image_offset(z_mt
, level
, slice
,
1449 &z_image_x
, &z_image_y
);
1451 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1452 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1453 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->region
->pitch
,
1454 x
+ s_image_x
+ map
->x
,
1455 y
+ s_image_y
+ map
->y
,
1456 intel
->has_swizzling
);
1457 ptrdiff_t z_offset
= ((y
+ z_image_y
) *
1458 (z_mt
->region
->pitch
/ 4) +
1461 if (map_z32f_x24s8
) {
1462 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
1463 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
1465 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
1466 s_map
[s_offset
] = packed
>> 24;
1467 z_map
[z_offset
] = packed
;
1472 intel_region_unmap(intel
, s_mt
->region
);
1473 intel_region_unmap(intel
, z_mt
->region
);
1475 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
1477 map
->x
, map
->y
, map
->w
, map
->h
,
1478 z_mt
, _mesa_get_format_name(z_mt
->format
),
1479 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
1480 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
1481 map
->ptr
, map
->stride
);
1488 * Create and attach a map to the miptree at (level, slice). Return the
1491 static struct intel_miptree_map
*
1492 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
1501 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
1506 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
1507 mt
->level
[level
].slice
[slice
].map
= map
;
1519 * Release the map at (level, slice).
1522 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
1526 struct intel_miptree_map
**map
;
1528 map
= &mt
->level
[level
].slice
[slice
].map
;
1534 intel_miptree_map_singlesample(struct intel_context
*intel
,
1535 struct intel_mipmap_tree
*mt
,
1546 struct intel_miptree_map
*map
;
1548 assert(mt
->num_samples
<= 1);
1550 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
1557 intel_miptree_slice_resolve_depth(intel
, mt
, level
, slice
);
1558 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1559 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
1562 if (mt
->format
== MESA_FORMAT_S8
) {
1563 intel_miptree_map_s8(intel
, mt
, map
, level
, slice
);
1564 } else if (mt
->wraps_etc
) {
1565 intel_miptree_map_etc(intel
, mt
, map
, level
, slice
);
1566 } else if (mt
->stencil_mt
) {
1567 intel_miptree_map_depthstencil(intel
, mt
, map
, level
, slice
);
1568 } else if (intel
->has_llc
&&
1569 !(mode
& GL_MAP_WRITE_BIT
) &&
1571 mt
->region
->tiling
== I915_TILING_X
) {
1572 intel_miptree_map_blit(intel
, mt
, map
, level
, slice
);
1574 intel_miptree_map_gtt(intel
, mt
, map
, level
, slice
);
1577 *out_ptr
= map
->ptr
;
1578 *out_stride
= map
->stride
;
1580 if (map
->ptr
== NULL
)
1581 intel_miptree_release_map(mt
, level
, slice
);
1585 intel_miptree_unmap_singlesample(struct intel_context
*intel
,
1586 struct intel_mipmap_tree
*mt
,
1590 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
1592 assert(mt
->num_samples
<= 1);
1597 DBG("%s: mt %p (%s) level %d slice %d\n", __FUNCTION__
,
1598 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
1600 if (mt
->format
== MESA_FORMAT_S8
) {
1601 intel_miptree_unmap_s8(intel
, mt
, map
, level
, slice
);
1602 } else if (mt
->wraps_etc
) {
1603 intel_miptree_unmap_etc(intel
, mt
, map
, level
, slice
);
1604 } else if (mt
->stencil_mt
) {
1605 intel_miptree_unmap_depthstencil(intel
, mt
, map
, level
, slice
);
1606 } else if (map
->bo
) {
1607 intel_miptree_unmap_blit(intel
, mt
, map
, level
, slice
);
1609 intel_miptree_unmap_gtt(intel
, mt
, map
, level
, slice
);
1612 intel_miptree_release_map(mt
, level
, slice
);
1616 intel_miptree_map_multisample(struct intel_context
*intel
,
1617 struct intel_mipmap_tree
*mt
,
1628 struct intel_miptree_map
*map
;
1630 assert(mt
->num_samples
> 1);
1632 /* Only flat, renderbuffer-like miptrees are supported. */
1633 if (mt
->target
!= GL_TEXTURE_2D
||
1634 mt
->first_level
!= 0 ||
1635 mt
->last_level
!= 0) {
1636 _mesa_problem(&intel
->ctx
, "attempt to map a multisample miptree for "
1637 "which (target, first_level, last_level != "
1638 "(GL_TEXTURE_2D, 0, 0)");
1642 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
1646 if (!mt
->singlesample_mt
) {
1647 mt
->singlesample_mt
=
1648 intel_miptree_create_for_renderbuffer(intel
,
1651 mt
->logical_height0
,
1653 if (!mt
->singlesample_mt
)
1656 map
->singlesample_mt_is_tmp
= true;
1657 mt
->need_downsample
= true;
1660 intel_miptree_downsample(intel
, mt
);
1661 intel_miptree_map_singlesample(intel
, mt
->singlesample_mt
,
1665 out_ptr
, out_stride
);
1669 intel_miptree_release_map(mt
, level
, slice
);
1675 intel_miptree_unmap_multisample(struct intel_context
*intel
,
1676 struct intel_mipmap_tree
*mt
,
1680 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
1682 assert(mt
->num_samples
> 1);
1687 intel_miptree_unmap_singlesample(intel
, mt
->singlesample_mt
, level
, slice
);
1689 mt
->need_downsample
= false;
1690 if (map
->mode
& GL_MAP_WRITE_BIT
)
1691 intel_miptree_upsample(intel
, mt
);
1693 if (map
->singlesample_mt_is_tmp
)
1694 intel_miptree_release(&mt
->singlesample_mt
);
1696 intel_miptree_release_map(mt
, level
, slice
);
1700 intel_miptree_map(struct intel_context
*intel
,
1701 struct intel_mipmap_tree
*mt
,
1712 if (mt
->num_samples
<= 1)
1713 intel_miptree_map_singlesample(intel
, mt
,
1717 out_ptr
, out_stride
);
1719 intel_miptree_map_multisample(intel
, mt
,
1723 out_ptr
, out_stride
);
1727 intel_miptree_unmap(struct intel_context
*intel
,
1728 struct intel_mipmap_tree
*mt
,
1732 if (mt
->num_samples
<= 1)
1733 intel_miptree_unmap_singlesample(intel
, mt
, level
, slice
);
1735 intel_miptree_unmap_multisample(intel
, mt
, level
, slice
);