1 /**************************************************************************
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include <GL/internal/dri_interface.h>
31 #include "intel_batchbuffer.h"
32 #include "intel_context.h"
33 #include "intel_mipmap_tree.h"
34 #include "intel_regions.h"
35 #include "intel_resolve_map.h"
36 #include "intel_span.h"
37 #include "intel_tex_layout.h"
38 #include "intel_tex.h"
39 #include "intel_blit.h"
42 #include "brw_blorp.h"
45 #include "main/enums.h"
46 #include "main/formats.h"
47 #include "main/glformats.h"
48 #include "main/texcompress_etc.h"
49 #include "main/teximage.h"
51 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
54 target_to_target(GLenum target
)
57 case GL_TEXTURE_CUBE_MAP_POSITIVE_X_ARB
:
58 case GL_TEXTURE_CUBE_MAP_NEGATIVE_X_ARB
:
59 case GL_TEXTURE_CUBE_MAP_POSITIVE_Y_ARB
:
60 case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y_ARB
:
61 case GL_TEXTURE_CUBE_MAP_POSITIVE_Z_ARB
:
62 case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z_ARB
:
63 return GL_TEXTURE_CUBE_MAP_ARB
;
70 * @param for_region Indicates that the caller is
71 * intel_miptree_create_for_region(). If true, then do not create
74 static struct intel_mipmap_tree
*
75 intel_miptree_create_internal(struct intel_context
*intel
,
85 enum intel_msaa_layout msaa_layout
)
87 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
88 int compress_byte
= 0;
90 DBG("%s target %s format %s level %d..%d <-- %p\n", __FUNCTION__
,
91 _mesa_lookup_enum_by_nr(target
),
92 _mesa_get_format_name(format
),
93 first_level
, last_level
, mt
);
95 if (_mesa_is_format_compressed(format
))
96 compress_byte
= intel_compressed_num_bytes(format
);
98 mt
->target
= target_to_target(target
);
100 mt
->first_level
= first_level
;
101 mt
->last_level
= last_level
;
103 mt
->height0
= height0
;
104 mt
->cpp
= compress_byte
? compress_byte
: _mesa_get_format_bytes(mt
->format
);
105 mt
->num_samples
= num_samples
;
106 mt
->compressed
= compress_byte
? 1 : 0;
107 mt
->msaa_layout
= msaa_layout
;
110 /* array_spacing_lod0 is only used for non-IMS MSAA surfaces. TODO: can we
113 switch (msaa_layout
) {
114 case INTEL_MSAA_LAYOUT_NONE
:
115 case INTEL_MSAA_LAYOUT_IMS
:
116 mt
->array_spacing_lod0
= false;
118 case INTEL_MSAA_LAYOUT_UMS
:
119 case INTEL_MSAA_LAYOUT_CMS
:
120 mt
->array_spacing_lod0
= true;
124 if (target
== GL_TEXTURE_CUBE_MAP
) {
132 _mesa_is_depthstencil_format(_mesa_get_format_base_format(format
)) &&
133 (intel
->must_use_separate_stencil
||
134 (intel
->has_separate_stencil
&&
135 intel
->vtbl
.is_hiz_depth_format(intel
, format
)))) {
136 /* MSAA stencil surfaces always use IMS layout. */
137 enum intel_msaa_layout msaa_layout
=
138 num_samples
> 1 ? INTEL_MSAA_LAYOUT_IMS
: INTEL_MSAA_LAYOUT_NONE
;
139 mt
->stencil_mt
= intel_miptree_create(intel
,
150 if (!mt
->stencil_mt
) {
151 intel_miptree_release(&mt
);
155 /* Fix up the Z miptree format for how we're splitting out separate
156 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
158 if (mt
->format
== MESA_FORMAT_S8_Z24
) {
159 mt
->format
= MESA_FORMAT_X8_Z24
;
160 } else if (mt
->format
== MESA_FORMAT_Z32_FLOAT_X24S8
) {
161 mt
->format
= MESA_FORMAT_Z32_FLOAT
;
164 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
165 _mesa_get_format_name(mt
->format
));
169 intel_get_texture_alignment_unit(intel
, mt
->format
,
170 &mt
->align_w
, &mt
->align_h
);
175 i945_miptree_layout(mt
);
177 i915_miptree_layout(mt
);
179 brw_miptree_layout(intel
, mt
);
186 struct intel_mipmap_tree
*
187 intel_miptree_create(struct intel_context
*intel
,
195 bool expect_accelerated_upload
,
197 enum intel_msaa_layout msaa_layout
)
199 struct intel_mipmap_tree
*mt
;
200 uint32_t tiling
= I915_TILING_NONE
;
202 bool wraps_etc1
= false;
204 if (format
== MESA_FORMAT_ETC1_RGB8
) {
205 format
= MESA_FORMAT_RGBX8888_REV
;
209 base_format
= _mesa_get_format_base_format(format
);
211 if (intel
->use_texture_tiling
&& !_mesa_is_format_compressed(format
)) {
212 if (intel
->gen
>= 4 &&
213 (base_format
== GL_DEPTH_COMPONENT
||
214 base_format
== GL_DEPTH_STENCIL_EXT
))
215 tiling
= I915_TILING_Y
;
216 else if (msaa_layout
!= INTEL_MSAA_LAYOUT_NONE
) {
217 /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
220 * [DevSNB+]: For multi-sample render targets, this field must be
221 * 1. MSRTs can only be tiled.
223 * Our usual reason for preferring X tiling (fast blits using the
224 * blitting engine) doesn't apply to MSAA, since we'll generally be
225 * downsampling or upsampling when blitting between the MSAA buffer
226 * and another buffer, and the blitting engine doesn't support that.
227 * So use Y tiling, since it makes better use of the cache.
229 tiling
= I915_TILING_Y
;
230 } else if (width0
>= 64)
231 tiling
= I915_TILING_X
;
234 if (format
== MESA_FORMAT_S8
) {
235 /* The stencil buffer is W tiled. However, we request from the kernel a
236 * non-tiled buffer because the GTT is incapable of W fencing. So round
237 * up the width and height to match the size of W tiles (64x64).
239 tiling
= I915_TILING_NONE
;
240 width0
= ALIGN(width0
, 64);
241 height0
= ALIGN(height0
, 64);
244 mt
= intel_miptree_create_internal(intel
, target
, format
,
245 first_level
, last_level
, width0
,
247 false, num_samples
, msaa_layout
);
249 * pitch == 0 || height == 0 indicates the null texture
251 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
252 intel_miptree_release(&mt
);
256 mt
->wraps_etc1
= wraps_etc1
;
257 mt
->region
= intel_region_alloc(intel
->intelScreen
,
262 expect_accelerated_upload
);
266 intel_miptree_release(&mt
);
274 struct intel_mipmap_tree
*
275 intel_miptree_create_for_region(struct intel_context
*intel
,
278 struct intel_region
*region
)
280 struct intel_mipmap_tree
*mt
;
282 mt
= intel_miptree_create_internal(intel
, target
, format
,
284 region
->width
, region
->height
, 1,
285 true, 0 /* num_samples */,
286 INTEL_MSAA_LAYOUT_NONE
);
290 intel_region_reference(&mt
->region
, region
);
296 * Determine which MSAA layout should be used by the MSAA surface being
297 * created, based on the chip generation and the surface type.
299 static enum intel_msaa_layout
300 compute_msaa_layout(struct intel_context
*intel
, gl_format format
)
302 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
304 return INTEL_MSAA_LAYOUT_IMS
;
306 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
307 switch (_mesa_get_format_base_format(format
)) {
308 case GL_DEPTH_COMPONENT
:
309 case GL_STENCIL_INDEX
:
310 case GL_DEPTH_STENCIL
:
311 return INTEL_MSAA_LAYOUT_IMS
;
313 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
315 * This field must be set to 0 for all SINT MSRTs when all RT channels
318 * In practice this means that we have to disable MCS for all signed
319 * integer MSAA buffers. The alternative, to disable MCS only when one
320 * of the render target channels is disabled, is impractical because it
321 * would require converting between CMS and UMS MSAA layouts on the fly,
322 * which is expensive.
324 if (_mesa_get_format_datatype(format
) == GL_INT
) {
325 /* TODO: is this workaround needed for future chipsets? */
326 assert(intel
->gen
== 7);
327 return INTEL_MSAA_LAYOUT_UMS
;
329 return INTEL_MSAA_LAYOUT_CMS
;
335 * For a singlesample DRI2 buffer, this simply wraps the given region with a miptree.
337 * For a multisample DRI2 buffer, this wraps the given region with
338 * a singlesample miptree, then creates a multisample miptree into which the
339 * singlesample miptree is embedded as a child.
341 struct intel_mipmap_tree
*
342 intel_miptree_create_for_dri2_buffer(struct intel_context
*intel
,
343 unsigned dri_attachment
,
345 uint32_t num_samples
,
346 struct intel_region
*region
)
348 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
349 struct intel_mipmap_tree
*multisample_mt
= NULL
;
350 GLenum base_format
= _mesa_get_format_base_format(format
);
352 /* Only the front and back buffers, which are color buffers, are shared
355 assert(dri_attachment
== __DRI_BUFFER_BACK_LEFT
||
356 dri_attachment
== __DRI_BUFFER_FRONT_LEFT
||
357 dri_attachment
== __DRI_BUFFER_FAKE_FRONT_LEFT
);
358 assert(base_format
== GL_RGB
|| base_format
== GL_RGBA
);
360 singlesample_mt
= intel_miptree_create_for_region(intel
, GL_TEXTURE_2D
,
362 if (!singlesample_mt
)
365 if (num_samples
== 0)
366 return singlesample_mt
;
368 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
373 if (!multisample_mt
) {
374 intel_miptree_release(&singlesample_mt
);
378 multisample_mt
->singlesample_mt
= singlesample_mt
;
379 multisample_mt
->need_downsample
= false;
381 if (intel
->is_front_buffer_rendering
&&
382 (dri_attachment
== __DRI_BUFFER_FRONT_LEFT
||
383 dri_attachment
== __DRI_BUFFER_FAKE_FRONT_LEFT
)) {
384 intel_miptree_upsample(intel
, multisample_mt
);
387 return multisample_mt
;
390 struct intel_mipmap_tree
*
391 intel_miptree_create_for_renderbuffer(struct intel_context
*intel
,
395 uint32_t num_samples
)
397 struct intel_mipmap_tree
*mt
;
399 enum intel_msaa_layout msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
400 const uint32_t singlesample_width
= width
;
401 const uint32_t singlesample_height
= height
;
404 if (num_samples
> 1) {
405 /* Adjust width/height/depth for MSAA */
406 msaa_layout
= compute_msaa_layout(intel
, format
);
407 if (msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
408 /* In the Sandy Bridge PRM, volume 4, part 1, page 31, it says:
410 * "Any of the other messages (sample*, LOD, load4) used with a
411 * (4x) multisampled surface will in-effect sample a surface with
412 * double the height and width as that indicated in the surface
413 * state. Each pixel position on the original-sized surface is
414 * replaced with a 2x2 of samples with the following arrangement:
419 * Thus, when sampling from a multisampled texture, it behaves as
420 * though the layout in memory for (x,y,sample) is:
422 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
423 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
425 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
426 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
428 * However, the actual layout of multisampled data in memory is:
430 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
431 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
433 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
434 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
436 * This pattern repeats for each 2x2 pixel block.
438 * As a result, when calculating the size of our 4-sample buffer for
439 * an odd width or height, we have to align before scaling up because
440 * sample 3 is in that bottom right 2x2 block.
442 switch (num_samples
) {
444 width
= ALIGN(width
, 2) * 2;
445 height
= ALIGN(height
, 2) * 2;
448 width
= ALIGN(width
, 2) * 4;
449 height
= ALIGN(height
, 2) * 2;
452 /* num_samples should already have been quantized to 0, 1, 4, or
458 /* Non-interleaved */
463 mt
= intel_miptree_create(intel
, GL_TEXTURE_2D
, format
, 0, 0,
464 width
, height
, depth
, true, num_samples
,
469 if (intel
->vtbl
.is_hiz_depth_format(intel
, format
)) {
470 ok
= intel_miptree_alloc_hiz(intel
, mt
, num_samples
);
475 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
476 ok
= intel_miptree_alloc_mcs(intel
, mt
, num_samples
);
481 mt
->singlesample_width0
= singlesample_width
;
482 mt
->singlesample_height0
= singlesample_height
;
487 intel_miptree_release(&mt
);
492 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
493 struct intel_mipmap_tree
*src
)
498 intel_miptree_release(dst
);
502 DBG("%s %p refcount now %d\n", __FUNCTION__
, src
, src
->refcount
);
510 intel_miptree_release(struct intel_mipmap_tree
**mt
)
515 DBG("%s %p refcount will be %d\n", __FUNCTION__
, *mt
, (*mt
)->refcount
- 1);
516 if (--(*mt
)->refcount
<= 0) {
519 DBG("%s deleting %p\n", __FUNCTION__
, *mt
);
521 intel_region_release(&((*mt
)->region
));
522 intel_miptree_release(&(*mt
)->stencil_mt
);
523 intel_miptree_release(&(*mt
)->hiz_mt
);
524 intel_miptree_release(&(*mt
)->mcs_mt
);
525 intel_miptree_release(&(*mt
)->singlesample_mt
);
526 intel_resolve_map_clear(&(*mt
)->hiz_map
);
528 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
529 free((*mt
)->level
[i
].slice
);
538 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
539 int *width
, int *height
, int *depth
)
541 switch (image
->TexObject
->Target
) {
542 case GL_TEXTURE_1D_ARRAY
:
543 *width
= image
->Width
;
545 *depth
= image
->Height
;
548 *width
= image
->Width
;
549 *height
= image
->Height
;
550 *depth
= image
->Depth
;
556 * Can the image be pulled into a unified mipmap tree? This mirrors
557 * the completeness test in a lot of ways.
559 * Not sure whether I want to pass gl_texture_image here.
562 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
563 struct gl_texture_image
*image
)
565 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
566 GLuint level
= intelImage
->base
.Base
.Level
;
567 int width
, height
, depth
;
569 if (target_to_target(image
->TexObject
->Target
) != mt
->target
)
572 if (image
->TexFormat
!= mt
->format
&&
573 !(image
->TexFormat
== MESA_FORMAT_S8_Z24
&&
574 mt
->format
== MESA_FORMAT_X8_Z24
&&
579 intel_miptree_get_dimensions_for_image(image
, &width
, &height
, &depth
);
581 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
584 /* Test image dimensions against the base level image adjusted for
585 * minification. This will also catch images not present in the
586 * tree, changed targets, etc.
588 if (width
!= mt
->level
[level
].width
||
589 height
!= mt
->level
[level
].height
||
590 depth
!= mt
->level
[level
].depth
)
598 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
601 GLuint w
, GLuint h
, GLuint d
)
603 mt
->level
[level
].width
= w
;
604 mt
->level
[level
].height
= h
;
605 mt
->level
[level
].depth
= d
;
606 mt
->level
[level
].level_x
= x
;
607 mt
->level
[level
].level_y
= y
;
609 DBG("%s level %d size: %d,%d,%d offset %d,%d\n", __FUNCTION__
,
610 level
, w
, h
, d
, x
, y
);
612 assert(mt
->level
[level
].slice
== NULL
);
614 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
615 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
616 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
621 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
622 GLuint level
, GLuint img
,
625 if (img
== 0 && level
== 0)
626 assert(x
== 0 && y
== 0);
628 assert(img
< mt
->level
[level
].depth
);
630 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
631 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
633 DBG("%s level %d img %d pos %d,%d\n",
634 __FUNCTION__
, level
, img
,
635 mt
->level
[level
].slice
[img
].x_offset
,
636 mt
->level
[level
].slice
[img
].y_offset
);
641 * For cube map textures, either the \c face parameter can be used, of course,
642 * or the cube face can be interpreted as a depth layer and the \c layer
646 intel_miptree_get_image_offset(struct intel_mipmap_tree
*mt
,
647 GLuint level
, GLuint face
, GLuint layer
,
648 GLuint
*x
, GLuint
*y
)
653 assert(mt
->target
== GL_TEXTURE_CUBE_MAP
);
658 /* This branch may be taken even if the texture target is a cube map. In
659 * that case, the caller chose to interpret each cube face as a layer.
665 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
666 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
670 intel_miptree_copy_slice(struct intel_context
*intel
,
671 struct intel_mipmap_tree
*dst_mt
,
672 struct intel_mipmap_tree
*src_mt
,
678 gl_format format
= src_mt
->format
;
679 uint32_t width
= src_mt
->level
[level
].width
;
680 uint32_t height
= src_mt
->level
[level
].height
;
682 assert(depth
< src_mt
->level
[level
].depth
);
684 if (dst_mt
->compressed
) {
685 height
= ALIGN(height
, dst_mt
->align_h
) / dst_mt
->align_h
;
686 width
= ALIGN(width
, dst_mt
->align_w
);
689 uint32_t dst_x
, dst_y
, src_x
, src_y
;
690 intel_miptree_get_image_offset(dst_mt
, level
, face
, depth
,
692 intel_miptree_get_image_offset(src_mt
, level
, face
, depth
,
695 DBG("validate blit mt %p %d,%d/%d -> mt %p %d,%d/%d (%dx%d)\n",
696 src_mt
, src_x
, src_y
, src_mt
->region
->pitch
* src_mt
->region
->cpp
,
697 dst_mt
, dst_x
, dst_y
, dst_mt
->region
->pitch
* dst_mt
->region
->cpp
,
700 if (!intelEmitCopyBlit(intel
,
702 src_mt
->region
->pitch
, src_mt
->region
->bo
,
703 0, src_mt
->region
->tiling
,
704 dst_mt
->region
->pitch
, dst_mt
->region
->bo
,
705 0, dst_mt
->region
->tiling
,
711 fallback_debug("miptree validate blit for %s failed\n",
712 _mesa_get_format_name(format
));
713 void *dst
= intel_region_map(intel
, dst_mt
->region
, GL_MAP_WRITE_BIT
);
714 void *src
= intel_region_map(intel
, src_mt
->region
, GL_MAP_READ_BIT
);
718 dst_mt
->region
->pitch
,
721 src
, src_mt
->region
->pitch
,
724 intel_region_unmap(intel
, dst_mt
->region
);
725 intel_region_unmap(intel
, src_mt
->region
);
728 if (src_mt
->stencil_mt
) {
729 intel_miptree_copy_slice(intel
,
730 dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
736 * Copies the image's current data to the given miptree, and associates that
737 * miptree with the image.
740 intel_miptree_copy_teximage(struct intel_context
*intel
,
741 struct intel_texture_image
*intelImage
,
742 struct intel_mipmap_tree
*dst_mt
)
744 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
745 int level
= intelImage
->base
.Base
.Level
;
746 int face
= intelImage
->base
.Base
.Face
;
747 GLuint depth
= intelImage
->base
.Base
.Depth
;
749 for (int slice
= 0; slice
< depth
; slice
++) {
750 intel_miptree_copy_slice(intel
, dst_mt
, src_mt
, level
, face
, slice
);
753 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
757 intel_miptree_alloc_mcs(struct intel_context
*intel
,
758 struct intel_mipmap_tree
*mt
,
761 assert(mt
->mcs_mt
== NULL
);
762 assert(intel
->gen
>= 7); /* MCS only used on Gen7+ */
764 /* Choose the correct format for the MCS buffer. All that really matters
765 * is that we allocate the right buffer size, since we'll always be
766 * accessing this miptree using MCS-specific hardware mechanisms, which
767 * infer the correct format based on num_samples.
770 switch (num_samples
) {
772 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
775 format
= MESA_FORMAT_R8
;
778 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
779 * for each sample, plus 8 padding bits).
781 format
= MESA_FORMAT_R_UINT32
;
784 assert(!"Unrecognized sample count in intel_miptree_alloc_mcs");
788 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
790 * "The MCS surface must be stored as Tile Y."
792 * We set msaa_format to INTEL_MSAA_LAYOUT_CMS to force
793 * intel_miptree_create() to use Y tiling. msaa_format is otherwise
794 * ignored for the MCS miptree.
796 mt
->mcs_mt
= intel_miptree_create(intel
,
806 INTEL_MSAA_LAYOUT_CMS
);
808 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
810 * When MCS buffer is enabled and bound to MSRT, it is required that it
811 * is cleared prior to any rendering.
813 * Since we don't use the MCS buffer for any purpose other than rendering,
814 * it makes sense to just clear it immediately upon allocation.
816 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
818 void *data
= intel_region_map(intel
, mt
->mcs_mt
->region
, 0);
819 memset(data
, 0xff, mt
->mcs_mt
->region
->bo
->size
);
820 intel_region_unmap(intel
, mt
->mcs_mt
->region
);
826 intel_miptree_alloc_hiz(struct intel_context
*intel
,
827 struct intel_mipmap_tree
*mt
,
830 assert(mt
->hiz_mt
== NULL
);
831 /* MSAA HiZ surfaces always use IMS layout. */
832 mt
->hiz_mt
= intel_miptree_create(intel
,
842 INTEL_MSAA_LAYOUT_IMS
);
847 /* Mark that all slices need a HiZ resolve. */
848 struct intel_resolve_map
*head
= &mt
->hiz_map
;
849 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
850 for (int layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
851 head
->next
= malloc(sizeof(*head
->next
));
852 head
->next
->prev
= head
;
853 head
->next
->next
= NULL
;
858 head
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
866 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
870 intel_miptree_check_level_layer(mt
, level
, layer
);
875 intel_resolve_map_set(&mt
->hiz_map
,
876 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
881 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
885 intel_miptree_check_level_layer(mt
, level
, layer
);
890 intel_resolve_map_set(&mt
->hiz_map
,
891 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
895 intel_miptree_slice_resolve(struct intel_context
*intel
,
896 struct intel_mipmap_tree
*mt
,
899 enum gen6_hiz_op need
)
901 intel_miptree_check_level_layer(mt
, level
, layer
);
903 struct intel_resolve_map
*item
=
904 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
906 if (!item
|| item
->need
!= need
)
909 intel_hiz_exec(intel
, mt
, level
, layer
, need
);
910 intel_resolve_map_remove(item
);
915 intel_miptree_slice_resolve_hiz(struct intel_context
*intel
,
916 struct intel_mipmap_tree
*mt
,
920 return intel_miptree_slice_resolve(intel
, mt
, level
, layer
,
921 GEN6_HIZ_OP_HIZ_RESOLVE
);
925 intel_miptree_slice_resolve_depth(struct intel_context
*intel
,
926 struct intel_mipmap_tree
*mt
,
930 return intel_miptree_slice_resolve(intel
, mt
, level
, layer
,
931 GEN6_HIZ_OP_DEPTH_RESOLVE
);
935 intel_miptree_all_slices_resolve(struct intel_context
*intel
,
936 struct intel_mipmap_tree
*mt
,
937 enum gen6_hiz_op need
)
939 bool did_resolve
= false;
940 struct intel_resolve_map
*i
, *next
;
942 for (i
= mt
->hiz_map
.next
; i
; i
= next
) {
947 intel_hiz_exec(intel
, mt
, i
->level
, i
->layer
, need
);
948 intel_resolve_map_remove(i
);
956 intel_miptree_all_slices_resolve_hiz(struct intel_context
*intel
,
957 struct intel_mipmap_tree
*mt
)
959 return intel_miptree_all_slices_resolve(intel
, mt
,
960 GEN6_HIZ_OP_HIZ_RESOLVE
);
964 intel_miptree_all_slices_resolve_depth(struct intel_context
*intel
,
965 struct intel_mipmap_tree
*mt
)
967 return intel_miptree_all_slices_resolve(intel
, mt
,
968 GEN6_HIZ_OP_DEPTH_RESOLVE
);
972 intel_miptree_updownsample(struct intel_context
*intel
,
973 struct intel_mipmap_tree
*src
,
974 struct intel_mipmap_tree
*dst
,
984 intel_miptree_slice_resolve_depth(intel
, src
, 0, 0);
985 intel_miptree_slice_resolve_depth(intel
, dst
, 0, 0);
987 brw_blorp_blit_miptrees(intel
,
992 false, false /*mirror x, y*/);
994 if (src
->stencil_mt
) {
995 brw_blorp_blit_miptrees(intel
,
996 src
->stencil_mt
, dst
->stencil_mt
,
1000 false, false /*mirror x, y*/);
1006 assert_is_flat(struct intel_mipmap_tree
*mt
)
1008 assert(mt
->target
== GL_TEXTURE_2D
);
1009 assert(mt
->first_level
== 0);
1010 assert(mt
->last_level
== 0);
1014 * \brief Downsample from mt to mt->singlesample_mt.
1016 * If the miptree needs no downsample, then skip.
1019 intel_miptree_downsample(struct intel_context
*intel
,
1020 struct intel_mipmap_tree
*mt
)
1022 /* Only flat, renderbuffer-like miptrees are supported. */
1025 if (!mt
->need_downsample
)
1027 intel_miptree_updownsample(intel
,
1028 mt
, mt
->singlesample_mt
,
1029 mt
->singlesample_mt
->width0
,
1030 mt
->singlesample_mt
->height0
);
1031 mt
->need_downsample
= false;
1033 /* Strictly speaking, after a downsample on a depth miptree, a hiz
1034 * resolve is needed on the singlesample miptree. However, since the
1035 * singlesample miptree is never rendered to, the hiz resolve will never
1036 * occur. Therefore we do not mark the needed hiz resolve after
1042 * \brief Upsample from mt->singlesample_mt to mt.
1044 * The upsample is done unconditionally.
1047 intel_miptree_upsample(struct intel_context
*intel
,
1048 struct intel_mipmap_tree
*mt
)
1050 /* Only flat, renderbuffer-like miptrees are supported. */
1052 assert(!mt
->need_downsample
);
1054 intel_miptree_updownsample(intel
,
1055 mt
->singlesample_mt
, mt
,
1056 mt
->singlesample_mt
->width0
,
1057 mt
->singlesample_mt
->height0
);
1058 intel_miptree_slice_set_needs_hiz_resolve(mt
, 0, 0);
1062 intel_miptree_map_gtt(struct intel_context
*intel
,
1063 struct intel_mipmap_tree
*mt
,
1064 struct intel_miptree_map
*map
,
1065 unsigned int level
, unsigned int slice
)
1067 unsigned int bw
, bh
;
1069 unsigned int image_x
, image_y
;
1073 /* For compressed formats, the stride is the number of bytes per
1074 * row of blocks. intel_miptree_get_image_offset() already does
1077 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
1078 assert(y
% bh
== 0);
1081 base
= intel_region_map(intel
, mt
->region
, map
->mode
);
1086 /* Note that in the case of cube maps, the caller must have passed the
1087 * slice number referencing the face.
1089 intel_miptree_get_image_offset(mt
, level
, 0, slice
, &image_x
, &image_y
);
1093 map
->stride
= mt
->region
->pitch
* mt
->cpp
;
1094 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
1097 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1098 map
->x
, map
->y
, map
->w
, map
->h
,
1099 mt
, _mesa_get_format_name(mt
->format
),
1100 x
, y
, map
->ptr
, map
->stride
);
1104 intel_miptree_unmap_gtt(struct intel_context
*intel
,
1105 struct intel_mipmap_tree
*mt
,
1106 struct intel_miptree_map
*map
,
1110 intel_region_unmap(intel
, mt
->region
);
1114 intel_miptree_map_blit(struct intel_context
*intel
,
1115 struct intel_mipmap_tree
*mt
,
1116 struct intel_miptree_map
*map
,
1117 unsigned int level
, unsigned int slice
)
1119 unsigned int image_x
, image_y
;
1124 /* The blitter requires the pitch to be aligned to 4. */
1125 map
->stride
= ALIGN(map
->w
* mt
->region
->cpp
, 4);
1127 map
->bo
= drm_intel_bo_alloc(intel
->bufmgr
, "intel_miptree_map_blit() temp",
1128 map
->stride
* map
->h
, 4096);
1130 fprintf(stderr
, "Failed to allocate blit temporary\n");
1134 intel_miptree_get_image_offset(mt
, level
, 0, slice
, &image_x
, &image_y
);
1138 if (!intelEmitCopyBlit(intel
,
1140 mt
->region
->pitch
, mt
->region
->bo
,
1141 0, mt
->region
->tiling
,
1142 map
->stride
/ mt
->region
->cpp
, map
->bo
,
1143 0, I915_TILING_NONE
,
1148 fprintf(stderr
, "Failed to blit\n");
1152 intel_batchbuffer_flush(intel
);
1153 ret
= drm_intel_bo_map(map
->bo
, (map
->mode
& GL_MAP_WRITE_BIT
) != 0);
1155 fprintf(stderr
, "Failed to map blit temporary\n");
1159 map
->ptr
= map
->bo
->virtual;
1161 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1162 map
->x
, map
->y
, map
->w
, map
->h
,
1163 mt
, _mesa_get_format_name(mt
->format
),
1164 x
, y
, map
->ptr
, map
->stride
);
1169 drm_intel_bo_unreference(map
->bo
);
1175 intel_miptree_unmap_blit(struct intel_context
*intel
,
1176 struct intel_mipmap_tree
*mt
,
1177 struct intel_miptree_map
*map
,
1181 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
1183 drm_intel_bo_unmap(map
->bo
);
1184 drm_intel_bo_unreference(map
->bo
);
1188 intel_miptree_map_s8(struct intel_context
*intel
,
1189 struct intel_mipmap_tree
*mt
,
1190 struct intel_miptree_map
*map
,
1191 unsigned int level
, unsigned int slice
)
1193 map
->stride
= map
->w
;
1194 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
1198 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1199 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1200 * invalidate is set, since we'll be writing the whole rectangle from our
1201 * temporary buffer back out.
1203 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
1204 uint8_t *untiled_s8_map
= map
->ptr
;
1205 uint8_t *tiled_s8_map
= intel_region_map(intel
, mt
->region
,
1207 unsigned int image_x
, image_y
;
1209 intel_miptree_get_image_offset(mt
, level
, 0, slice
, &image_x
, &image_y
);
1211 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1212 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1213 ptrdiff_t offset
= intel_offset_S8(mt
->region
->pitch
,
1214 x
+ image_x
+ map
->x
,
1215 y
+ image_y
+ map
->y
,
1216 intel
->has_swizzling
);
1217 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
1221 intel_region_unmap(intel
, mt
->region
);
1223 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __FUNCTION__
,
1224 map
->x
, map
->y
, map
->w
, map
->h
,
1225 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
1227 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
1228 map
->x
, map
->y
, map
->w
, map
->h
,
1229 mt
, map
->ptr
, map
->stride
);
1234 intel_miptree_unmap_s8(struct intel_context
*intel
,
1235 struct intel_mipmap_tree
*mt
,
1236 struct intel_miptree_map
*map
,
1240 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1241 unsigned int image_x
, image_y
;
1242 uint8_t *untiled_s8_map
= map
->ptr
;
1243 uint8_t *tiled_s8_map
= intel_region_map(intel
, mt
->region
, map
->mode
);
1245 intel_miptree_get_image_offset(mt
, level
, 0, slice
, &image_x
, &image_y
);
1247 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1248 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1249 ptrdiff_t offset
= intel_offset_S8(mt
->region
->pitch
,
1252 intel
->has_swizzling
);
1253 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
1257 intel_region_unmap(intel
, mt
->region
);
1264 intel_miptree_map_etc1(struct intel_context
*intel
,
1265 struct intel_mipmap_tree
*mt
,
1266 struct intel_miptree_map
*map
,
1270 /* For justification of these invariants,
1271 * see intel_mipmap_tree:wraps_etc1.
1273 assert(mt
->wraps_etc1
);
1274 assert(mt
->format
== MESA_FORMAT_RGBX8888_REV
);
1276 /* From the GL_OES_compressed_ETC1_RGB8_texture spec:
1277 * INVALID_OPERATION is generated by CompressedTexSubImage2D,
1278 * TexSubImage2D, or CopyTexSubImage2D if the texture image <level>
1279 * bound to <target> has internal format ETC1_RGB8_OES.
1281 * This implies that intel_miptree_map_etc1() can only be called from
1282 * glCompressedTexImage2D, and hence the assertions below hold.
1284 assert(map
->mode
& GL_MAP_WRITE_BIT
);
1285 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
1286 assert(map
->x
== 0);
1287 assert(map
->y
== 0);
1289 /* Each ETC1 block contains 4x4 pixels in 8 bytes. */
1290 map
->stride
= 2 * map
->w
;
1291 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
1295 intel_miptree_unmap_etc1(struct intel_context
*intel
,
1296 struct intel_mipmap_tree
*mt
,
1297 struct intel_miptree_map
*map
,
1303 intel_miptree_get_image_offset(mt
, level
, 0, slice
, &image_x
, &image_y
);
1305 uint8_t *xbgr
= intel_region_map(intel
, mt
->region
, map
->mode
)
1306 + image_y
* mt
->region
->pitch
* mt
->region
->cpp
1307 + image_x
* mt
->region
->cpp
;
1309 _mesa_etc1_unpack_rgba8888(xbgr
, mt
->region
->pitch
* mt
->region
->cpp
,
1310 map
->ptr
, map
->stride
,
1313 intel_region_unmap(intel
, mt
->region
);
1318 * Mapping function for packed depth/stencil miptrees backed by real separate
1319 * miptrees for depth and stencil.
1321 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
1322 * separate from the depth buffer. Yet at the GL API level, we have to expose
1323 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
1324 * be able to map that memory for texture storage and glReadPixels-type
1325 * operations. We give Mesa core that access by mallocing a temporary and
1326 * copying the data between the actual backing store and the temporary.
1329 intel_miptree_map_depthstencil(struct intel_context
*intel
,
1330 struct intel_mipmap_tree
*mt
,
1331 struct intel_miptree_map
*map
,
1332 unsigned int level
, unsigned int slice
)
1334 struct intel_mipmap_tree
*z_mt
= mt
;
1335 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
1336 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z32_FLOAT
;
1337 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
1339 map
->stride
= map
->w
* packed_bpp
;
1340 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
1344 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1345 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1346 * invalidate is set, since we'll be writing the whole rectangle from our
1347 * temporary buffer back out.
1349 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
1350 uint32_t *packed_map
= map
->ptr
;
1351 uint8_t *s_map
= intel_region_map(intel
, s_mt
->region
, GL_MAP_READ_BIT
);
1352 uint32_t *z_map
= intel_region_map(intel
, z_mt
->region
, GL_MAP_READ_BIT
);
1353 unsigned int s_image_x
, s_image_y
;
1354 unsigned int z_image_x
, z_image_y
;
1356 intel_miptree_get_image_offset(s_mt
, level
, 0, slice
,
1357 &s_image_x
, &s_image_y
);
1358 intel_miptree_get_image_offset(z_mt
, level
, 0, slice
,
1359 &z_image_x
, &z_image_y
);
1361 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1362 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1363 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
1364 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->region
->pitch
,
1367 intel
->has_swizzling
);
1368 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) * z_mt
->region
->pitch
+
1369 (map_x
+ z_image_x
));
1370 uint8_t s
= s_map
[s_offset
];
1371 uint32_t z
= z_map
[z_offset
];
1373 if (map_z32f_x24s8
) {
1374 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
1375 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
1377 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
1382 intel_region_unmap(intel
, s_mt
->region
);
1383 intel_region_unmap(intel
, z_mt
->region
);
1385 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
1387 map
->x
, map
->y
, map
->w
, map
->h
,
1388 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
1389 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
1390 map
->ptr
, map
->stride
);
1392 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
1393 map
->x
, map
->y
, map
->w
, map
->h
,
1394 mt
, map
->ptr
, map
->stride
);
1399 intel_miptree_unmap_depthstencil(struct intel_context
*intel
,
1400 struct intel_mipmap_tree
*mt
,
1401 struct intel_miptree_map
*map
,
1405 struct intel_mipmap_tree
*z_mt
= mt
;
1406 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
1407 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z32_FLOAT
;
1409 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1410 uint32_t *packed_map
= map
->ptr
;
1411 uint8_t *s_map
= intel_region_map(intel
, s_mt
->region
, map
->mode
);
1412 uint32_t *z_map
= intel_region_map(intel
, z_mt
->region
, map
->mode
);
1413 unsigned int s_image_x
, s_image_y
;
1414 unsigned int z_image_x
, z_image_y
;
1416 intel_miptree_get_image_offset(s_mt
, level
, 0, slice
,
1417 &s_image_x
, &s_image_y
);
1418 intel_miptree_get_image_offset(z_mt
, level
, 0, slice
,
1419 &z_image_x
, &z_image_y
);
1421 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1422 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1423 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->region
->pitch
,
1424 x
+ s_image_x
+ map
->x
,
1425 y
+ s_image_y
+ map
->y
,
1426 intel
->has_swizzling
);
1427 ptrdiff_t z_offset
= ((y
+ z_image_y
) * z_mt
->region
->pitch
+
1430 if (map_z32f_x24s8
) {
1431 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
1432 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
1434 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
1435 s_map
[s_offset
] = packed
>> 24;
1436 z_map
[z_offset
] = packed
;
1441 intel_region_unmap(intel
, s_mt
->region
);
1442 intel_region_unmap(intel
, z_mt
->region
);
1444 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
1446 map
->x
, map
->y
, map
->w
, map
->h
,
1447 z_mt
, _mesa_get_format_name(z_mt
->format
),
1448 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
1449 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
1450 map
->ptr
, map
->stride
);
1457 * Create and attach a map to the miptree at (level, slice). Return the
1460 static struct intel_miptree_map
*
1461 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
1470 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
1475 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
1476 mt
->level
[level
].slice
[slice
].map
= map
;
1488 * Release the map at (level, slice).
1491 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
1495 struct intel_miptree_map
**map
;
1497 map
= &mt
->level
[level
].slice
[slice
].map
;
1503 intel_miptree_map_singlesample(struct intel_context
*intel
,
1504 struct intel_mipmap_tree
*mt
,
1515 struct intel_miptree_map
*map
;
1517 assert(mt
->num_samples
<= 1);
1519 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
1526 intel_miptree_slice_resolve_depth(intel
, mt
, level
, slice
);
1527 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1528 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
1531 if (mt
->format
== MESA_FORMAT_S8
) {
1532 intel_miptree_map_s8(intel
, mt
, map
, level
, slice
);
1533 } else if (mt
->wraps_etc1
) {
1534 intel_miptree_map_etc1(intel
, mt
, map
, level
, slice
);
1535 } else if (mt
->stencil_mt
) {
1536 intel_miptree_map_depthstencil(intel
, mt
, map
, level
, slice
);
1537 } else if (intel
->has_llc
&&
1538 !(mode
& GL_MAP_WRITE_BIT
) &&
1540 mt
->region
->tiling
== I915_TILING_X
) {
1541 intel_miptree_map_blit(intel
, mt
, map
, level
, slice
);
1543 intel_miptree_map_gtt(intel
, mt
, map
, level
, slice
);
1546 *out_ptr
= map
->ptr
;
1547 *out_stride
= map
->stride
;
1549 if (map
->ptr
== NULL
)
1550 intel_miptree_release_map(mt
, level
, slice
);
1554 intel_miptree_unmap_singlesample(struct intel_context
*intel
,
1555 struct intel_mipmap_tree
*mt
,
1559 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
1561 assert(mt
->num_samples
<= 1);
1566 DBG("%s: mt %p (%s) level %d slice %d\n", __FUNCTION__
,
1567 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
1569 if (mt
->format
== MESA_FORMAT_S8
) {
1570 intel_miptree_unmap_s8(intel
, mt
, map
, level
, slice
);
1571 } else if (mt
->wraps_etc1
) {
1572 intel_miptree_unmap_etc1(intel
, mt
, map
, level
, slice
);
1573 } else if (mt
->stencil_mt
) {
1574 intel_miptree_unmap_depthstencil(intel
, mt
, map
, level
, slice
);
1575 } else if (map
->bo
) {
1576 intel_miptree_unmap_blit(intel
, mt
, map
, level
, slice
);
1578 intel_miptree_unmap_gtt(intel
, mt
, map
, level
, slice
);
1581 intel_miptree_release_map(mt
, level
, slice
);
1585 intel_miptree_map_multisample(struct intel_context
*intel
,
1586 struct intel_mipmap_tree
*mt
,
1597 struct intel_miptree_map
*map
;
1599 assert(mt
->num_samples
> 1);
1601 /* Only flat, renderbuffer-like miptrees are supported. */
1602 if (mt
->target
!= GL_TEXTURE_2D
||
1603 mt
->first_level
!= 0 ||
1604 mt
->last_level
!= 0) {
1605 _mesa_problem(&intel
->ctx
, "attempt to map a multisample miptree for "
1606 "which (target, first_level, last_level != "
1607 "(GL_TEXTURE_2D, 0, 0)");
1611 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
1615 if (!mt
->singlesample_mt
) {
1616 mt
->singlesample_mt
=
1617 intel_miptree_create_for_renderbuffer(intel
,
1619 mt
->singlesample_width0
,
1620 mt
->singlesample_height0
,
1622 if (!mt
->singlesample_mt
)
1625 map
->singlesample_mt_is_tmp
= true;
1626 mt
->need_downsample
= true;
1629 if (mode
& GL_MAP_INVALIDATE_RANGE_BIT
)
1630 mt
->need_downsample
= false;
1632 intel_miptree_downsample(intel
, mt
);
1633 intel_miptree_map_singlesample(intel
, mt
->singlesample_mt
,
1637 out_ptr
, out_stride
);
1641 intel_miptree_release_map(mt
, level
, slice
);
1647 intel_miptree_unmap_multisample(struct intel_context
*intel
,
1648 struct intel_mipmap_tree
*mt
,
1652 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
1654 assert(mt
->num_samples
> 1);
1659 intel_miptree_unmap_singlesample(intel
, mt
->singlesample_mt
, level
, slice
);
1661 mt
->need_downsample
= false;
1662 if (map
->mode
& GL_MAP_WRITE_BIT
)
1663 intel_miptree_upsample(intel
, mt
);
1665 if (map
->singlesample_mt_is_tmp
)
1666 intel_miptree_release(&mt
->singlesample_mt
);
1668 intel_miptree_release_map(mt
, level
, slice
);
1672 intel_miptree_map(struct intel_context
*intel
,
1673 struct intel_mipmap_tree
*mt
,
1684 if (mt
->num_samples
<= 1)
1685 intel_miptree_map_singlesample(intel
, mt
,
1689 out_ptr
, out_stride
);
1691 intel_miptree_map_multisample(intel
, mt
,
1695 out_ptr
, out_stride
);
1699 intel_miptree_unmap(struct intel_context
*intel
,
1700 struct intel_mipmap_tree
*mt
,
1704 if (mt
->num_samples
<= 1)
1705 intel_miptree_unmap_singlesample(intel
, mt
, level
, slice
);
1707 intel_miptree_unmap_multisample(intel
, mt
, level
, slice
);