src/mesa/drivers/dri/intel/intel_mipmap_tree.h

   1 /**************************************************************************
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   3  * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
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  11  * permit persons to whom the Software is furnished to do so, subject to
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  16  * of the Software.
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  27
  28 #ifndef INTEL_MIPMAP_TREE_H
  29 #define INTEL_MIPMAP_TREE_H
  30
  31 #include <assert.h>
  32
  33 #include "intel_regions.h"
  34 #include "intel_resolve_map.h"
  35
  36 #ifdef __cplusplus
  37 extern "C" {
  38 #endif
  39
  40 /* A layer on top of the intel_regions code which adds:
  41  *
  42  * - Code to size and layout a region to hold a set of mipmaps.
  43  * - Query to determine if a new image fits in an existing tree.
  44  * - More refcounting
  45  *     - maybe able to remove refcounting from intel_region?
  46  * - ?
  47  *
  48  * The fixed mipmap layout of intel hardware where one offset
  49  * specifies the position of all images in a mipmap hierachy
  50  * complicates the implementation of GL texture image commands,
  51  * compared to hardware where each image is specified with an
  52  * independent offset.
  53  *
  54  * In an ideal world, each texture object would be associated with a
  55  * single bufmgr buffer or 2d intel_region, and all the images within
  56  * the texture object would slot into the tree as they arrive.  The
  57  * reality can be a little messier, as images can arrive from the user
  58  * with sizes that don't fit in the existing tree, or in an order
  59  * where the tree layout cannot be guessed immediately.
  60  *
  61  * This structure encodes an idealized mipmap tree.  The GL image
  62  * commands build these where possible, otherwise store the images in
  63  * temporary system buffers.
  64  */
  65
  66 struct intel_resolve_map;
  67 struct intel_texture_image;
  68
  69 struct intel_miptree_map {
  70    /** Bitfield of GL_MAP_READ_BIT, GL_MAP_WRITE_BIT, GL_MAP_INVALIDATE_BIT */
  71    GLbitfield mode;
  72    /** Region of interest for the map. */
  73    int x, y, w, h;
  74    /** Possibly malloced temporary buffer for the mapping. */
  75    void *buffer;
  76    /** Possible pointer to a BO temporary for the mapping. */
  77    drm_intel_bo *bo;
  78    /** Pointer to the start of (map_x, map_y) returned by the mapping. */
  79    void *ptr;
  80    /** Stride of the mapping. */
  81    int stride;
  82
  83    /**
  84     * intel_mipmap_tree::singlesample_mt is temporary storage that persists
  85     * only for the duration of the map.
  86     */
  87    bool singlesample_mt_is_tmp;
  88 };
  89
  90 /**
  91  * Describes the location of each texture image within a texture region.
  92  */
  93 struct intel_mipmap_level
  94 {
  95    /** Offset to this miptree level, used in computing x_offset. */
  96    GLuint level_x;
  97    /** Offset to this miptree level, used in computing y_offset. */
  98    GLuint level_y;
  99    GLuint width;
 100    GLuint height;
 101
 102    /**
 103     * \brief Number of 2D slices in this miplevel.
 104     *
 105     * The exact semantics of depth varies according to the texture target:
 106     *    - For GL_TEXTURE_CUBE_MAP, depth is 6.
 107     *    - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
 108     *      identical for all miplevels in the texture.
 109     *    - For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its
 110     *      value, like width and height, varies with miplevel.
 111     *    - For other texture types, depth is 1.
 112     */
 113    GLuint depth;
 114
 115    /**
 116     * \brief List of 2D images in this mipmap level.
 117     *
 118     * This may be a list of cube faces, array slices in 2D array texture, or
 119     * layers in a 3D texture. The list's length is \c depth.
 120     */
 121    struct intel_mipmap_slice {
 122       /**
 123        * \name Offset to slice
 124        * \{
 125        *
 126        * Hardware formats are so diverse that that there is no unified way to
 127        * compute the slice offsets, so we store them in this table.
 128        *
 129        * The (x, y) offset to slice \c s at level \c l relative the miptrees
 130        * base address is
 131        * \code
 132        *     x = mt->level[l].slice[s].x_offset
 133        *     y = mt->level[l].slice[s].y_offset
 134        */
 135       GLuint x_offset;
 136       GLuint y_offset;
 137       /** \} */
 138
 139       /**
 140        * Mapping information. Persistent for the duration of
 141        * intel_miptree_map/unmap on this slice.
 142        */
 143       struct intel_miptree_map *map;
 144    } *slice;
 145 };
 146
 147 /**
 148  * Enum for keeping track of the different MSAA layouts supported by Gen7.
 149  */
 150 enum intel_msaa_layout
 151 {
 152    /**
 153     * Ordinary surface with no MSAA.
 154     */
 155    INTEL_MSAA_LAYOUT_NONE,
 156
 157    /**
 158     * Interleaved Multisample Surface.  The additional samples are
 159     * accommodated by scaling up the width and the height of the surface so
 160     * that all the samples corresponding to a pixel are located at nearby
 161     * memory locations.
 162     */
 163    INTEL_MSAA_LAYOUT_IMS,
 164
 165    /**
 166     * Uncompressed Multisample Surface.  The surface is stored as a 2D array,
 167     * with array slice n containing all pixel data for sample n.
 168     */
 169    INTEL_MSAA_LAYOUT_UMS,
 170
 171    /**
 172     * Compressed Multisample Surface.  The surface is stored as in
 173     * INTEL_MSAA_LAYOUT_UMS, but there is an additional buffer called the MCS
 174     * (Multisample Control Surface) buffer.  Each pixel in the MCS buffer
 175     * indicates the mapping from sample number to array slice.  This allows
 176     * the common case (where all samples constituting a pixel have the same
 177     * color value) to be stored efficiently by just using a single array
 178     * slice.
 179     */
 180    INTEL_MSAA_LAYOUT_CMS,
 181 };
 182
 183 struct intel_mipmap_tree
 184 {
 185    /* Effectively the key:
 186     */
 187    GLenum target;
 188
 189    /**
 190     * Generally, this is just the same as the gl_texture_image->TexFormat or
 191     * gl_renderbuffer->Format.
 192     *
 193     * However, for textures and renderbuffers with packed depth/stencil formats
 194     * on hardware where we want or need to use separate stencil, there will be
 195     * two miptrees for storing the data.  If the depthstencil texture or rb is
 196     * MESA_FORMAT_Z32_FLOAT_X24S8, then mt->format will be
 197     * MESA_FORMAT_Z32_FLOAT, otherwise for MESA_FORMAT_S8_Z24 objects it will be
 198     * MESA_FORMAT_X8_Z24.
 199     *
 200     * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
 201     * formats if the hardware lacks support for ETC1/ETC2. See @ref wraps_etc.
 202     */
 203    gl_format format;
 204
 205    /** This variable stores the value of ETC compressed texture format */
 206    gl_format etc_format;
 207
 208    /**
 209     * The X offset of each image in the miptree must be aligned to this. See
 210     * the "Alignment Unit Size" section of the BSpec.
 211     */
 212    unsigned int align_w;
 213    unsigned int align_h; /**< \see align_w */
 214
 215    GLuint first_level;
 216    GLuint last_level;
 217
 218    GLuint width0, height0, depth0; /**< Level zero image dimensions */
 219    GLuint cpp;
 220    GLuint num_samples;
 221    bool compressed;
 222
 223    /**
 224     * If num_samples > 0, then singlesample_width0 is the value that width0
 225     * would have if instead a singlesample miptree were created. Note that,
 226     * for non-interleaved msaa layouts, the two values are the same.
 227     *
 228     * If num_samples == 0, then singlesample_width0 is undefined.
 229     */
 230    uint32_t singlesample_width0;
 231
 232    /** \see singlesample_width0 */
 233    uint32_t singlesample_height0;
 234
 235    /**
 236     * For 1D array, 2D array, cube, and 2D multisampled surfaces on Gen7: true
 237     * if the surface only contains LOD 0, and hence no space is for LOD's
 238     * other than 0 in between array slices.
 239     *
 240     * Corresponds to the surface_array_spacing bit in gen7_surface_state.
 241     */
 242    bool array_spacing_lod0;
 243
 244    /**
 245     * MSAA layout used by this buffer.
 246     */
 247    enum intel_msaa_layout msaa_layout;
 248
 249    /* Derived from the above:
 250     */
 251    GLuint total_width;
 252    GLuint total_height;
 253
 254    /* The 3DSTATE_CLEAR_PARAMS value associated with the last depth clear to
 255     * this depth mipmap tree, if any.
 256     */
 257    uint32_t depth_clear_value;
 258
 259    /* Includes image offset tables:
 260     */
 261    struct intel_mipmap_level level[MAX_TEXTURE_LEVELS];
 262
 263    /* The data is held here:
 264     */
 265    struct intel_region *region;
 266
 267    /* Offset into region bo where miptree starts:
 268     */
 269    uint32_t offset;
 270
 271    /**
 272     * \brief Singlesample miptree.
 273     *
 274     * This is used under two cases.
 275     *
 276     * --- Case 1: As persistent singlesample storage for multisample window
 277     *  system front and back buffers ---
 278     *
 279     * Suppose that the window system FBO was created with a multisample
 280     * config.  Let `back_irb` be the `intel_renderbuffer` for the FBO's back
 281     * buffer. Then `back_irb` contains two miptrees: a parent multisample
 282     * miptree (back_irb->mt) and a child singlesample miptree
 283     * (back_irb->mt->singlesample_mt).  The DRM buffer shared with DRI2
 284     * belongs to `back_irb->mt->singlesample_mt` and contains singlesample
 285     * data.  The singlesample miptree is created at the same time as and
 286     * persists for the lifetime of its parent multisample miptree.
 287     *
 288     * When access to the singlesample data is needed, such as at
 289     * eglSwapBuffers and glReadPixels, an automatic downsample occurs from
 290     * `back_rb->mt` to `back_rb->mt->singlesample_mt` when necessary.
 291     *
 292     * This description of the back buffer applies analogously to the front
 293     * buffer.
 294     *
 295     *
 296     * --- Case 2: As temporary singlesample storage for mapping multisample
 297     *  miptrees ---
 298     *
 299     * Suppose the intel_miptree_map is called on a multisample miptree, `mt`,
 300     * for which case 1 does not apply (that is, `mt` does not belong to
 301     * a front or back buffer).  Then `mt->singlesample_mt` is null at the
 302     * start of the call. intel_miptree_map will create a temporary
 303     * singlesample miptree, store it at `mt->singlesample_mt`, downsample from
 304     * `mt` to `mt->singlesample_mt` if necessary, then map
 305     * `mt->singlesample_mt`. The temporary miptree is later deleted during
 306     * intel_miptree_unmap.
 307     */
 308    struct intel_mipmap_tree *singlesample_mt;
 309
 310    /**
 311     * \brief A downsample is needed from this miptree to singlesample_mt.
 312     */
 313    bool need_downsample;
 314
 315    /**
 316     * \brief HiZ miptree
 317     *
 318     * This is non-null only if HiZ is enabled for this miptree.
 319     *
 320     * \see intel_miptree_alloc_hiz()
 321     */
 322    struct intel_mipmap_tree *hiz_mt;
 323
 324    /**
 325     * \brief Map of miptree slices to needed resolves.
 326     *
 327     * This is used only when the miptree has a child HiZ miptree.
 328     *
 329     * Let \c mt be a depth miptree with HiZ enabled. Then the resolve map is
 330     * \c mt->hiz_map. The resolve map of the child HiZ miptree, \c
 331     * mt->hiz_mt->hiz_map, is unused.
 332     */
 333    struct intel_resolve_map hiz_map;
 334
 335    /**
 336     * \brief Stencil miptree for depthstencil textures.
 337     *
 338     * This miptree is used for depthstencil textures and renderbuffers that
 339     * require separate stencil.  It always has the true copy of the stencil
 340     * bits, regardless of mt->format.
 341     *
 342     * \see intel_miptree_map_depthstencil()
 343     * \see intel_miptree_unmap_depthstencil()
 344     */
 345    struct intel_mipmap_tree *stencil_mt;
 346
 347    /**
 348     * \brief MCS miptree for multisampled textures.
 349     *
 350     * This miptree contains the "multisample control surface", which stores
 351     * the necessary information to implement compressed MSAA on Gen7+
 352     * (INTEL_MSAA_FORMAT_CMS).
 353     */
 354    struct intel_mipmap_tree *mcs_mt;
 355
 356    /**
 357     * \brief The miptree contains uncompressed data that was originally
 358     * ETC1/ETC2 data.
 359     *
 360     * On hardware that lacks support for ETC1/ETC2 textures, we do the following
 361     * on calls to glCompressedTexImage2D() with an ETC1/ETC2 texture format:
 362     *   1. Create a miptree whose format is a suitable uncompressed mesa format
 363     *      with the wraps_etc flag set.
 364     *   2. Translate the ETC1/ETC2 data into uncompressed mesa format.
 365     *   3. Store the uncompressed  data into the miptree and discard the ETC1/ETC2
 366     *      data.
 367     */
 368    bool wraps_etc;
 369
 370    /* These are also refcounted:
 371     */
 372    GLuint refcount;
 373 };
 374
 375
 376
 377 struct intel_mipmap_tree *intel_miptree_create(struct intel_context *intel,
 378                                                GLenum target,
 379                                                gl_format format,
 380                                                GLuint first_level,
 381                                                GLuint last_level,
 382                                                GLuint width0,
 383                                                GLuint height0,
 384                                                GLuint depth0,
 385                                                bool expect_accelerated_upload,
 386                                                GLuint num_samples,
 387                                                enum intel_msaa_layout msaa_layout,
 388                                                bool force_y_tiling);
 389
 390 struct intel_mipmap_tree *
 391 intel_miptree_create_for_region(struct intel_context *intel,
 392                                 GLenum target,
 393                                 gl_format format,
 394                                 struct intel_region *region);
 395
 396 struct intel_mipmap_tree*
 397 intel_miptree_create_for_dri2_buffer(struct intel_context *intel,
 398                                      unsigned dri_attachment,
 399                                      gl_format format,
 400                                      uint32_t num_samples,
 401                                      struct intel_region *region);
 402
 403 /**
 404  * Create a miptree appropriate as the storage for a non-texture renderbuffer.
 405  * The miptree has the following properties:
 406  *     - The target is GL_TEXTURE_2D.
 407  *     - There are no levels other than the base level 0.
 408  *     - Depth is 1.
 409  */
 410 struct intel_mipmap_tree*
 411 intel_miptree_create_for_renderbuffer(struct intel_context *intel,
 412                                       gl_format format,
 413                                       uint32_t width,
 414                                       uint32_t height,
 415                                       uint32_t num_samples);
 416
 417 /** \brief Assert that the level and layer are valid for the miptree. */
 418 static inline void
 419 intel_miptree_check_level_layer(struct intel_mipmap_tree *mt,
 420                                 uint32_t level,
 421                                 uint32_t layer)
 422 {
 423    assert(level >= mt->first_level);
 424    assert(level <= mt->last_level);
 425    assert(layer < mt->level[level].depth);
 426 }
 427
 428 int intel_miptree_pitch_align (struct intel_context *intel,
 429                                struct intel_mipmap_tree *mt,
 430                                uint32_t tiling,
 431                                int pitch);
 432
 433 void intel_miptree_reference(struct intel_mipmap_tree **dst,
 434                              struct intel_mipmap_tree *src);
 435
 436 void intel_miptree_release(struct intel_mipmap_tree **mt);
 437
 438 /* Check if an image fits an existing mipmap tree layout
 439  */
 440 bool intel_miptree_match_image(struct intel_mipmap_tree *mt,
 441                                     struct gl_texture_image *image);
 442
 443 void
 444 intel_miptree_get_image_offset(struct intel_mipmap_tree *mt,
 445                                GLuint level, GLuint slice,
 446                                GLuint *x, GLuint *y);
 447
 448 void
 449 intel_miptree_get_dimensions_for_image(struct gl_texture_image *image,
 450                                        int *width, int *height, int *depth);
 451
 452 void intel_miptree_set_level_info(struct intel_mipmap_tree *mt,
 453                                   GLuint level,
 454                                   GLuint x, GLuint y,
 455                                   GLuint w, GLuint h, GLuint d);
 456
 457 void intel_miptree_set_image_offset(struct intel_mipmap_tree *mt,
 458                                     GLuint level,
 459                                     GLuint img, GLuint x, GLuint y);
 460
 461 void
 462 intel_miptree_copy_teximage(struct intel_context *intel,
 463                             struct intel_texture_image *intelImage,
 464                             struct intel_mipmap_tree *dst_mt);
 465
 466 /**
 467  * Copy the stencil data from \c mt->stencil_mt->region to \c mt->region for
 468  * the given miptree slice.
 469  *
 470  * \see intel_mipmap_tree::stencil_mt
 471  */
 472 void
 473 intel_miptree_s8z24_scatter(struct intel_context *intel,
 474                             struct intel_mipmap_tree *mt,
 475                             uint32_t level,
 476                             uint32_t slice);
 477
 478 /**
 479  * Copy the stencil data in \c mt->stencil_mt->region to \c mt->region for the
 480  * given miptree slice.
 481  *
 482  * \see intel_mipmap_tree::stencil_mt
 483  */
 484 void
 485 intel_miptree_s8z24_gather(struct intel_context *intel,
 486                            struct intel_mipmap_tree *mt,
 487                            uint32_t level,
 488                            uint32_t layer);
 489
 490 bool
 491 intel_miptree_alloc_mcs(struct intel_context *intel,
 492                         struct intel_mipmap_tree *mt,
 493                         GLuint num_samples);
 494
 495 /**
 496  * \name Miptree HiZ functions
 497  * \{
 498  *
 499  * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
 500  * functions on a miptree without HiZ. In that case, each function is a no-op.
 501  */
 502
 503 /**
 504  * \brief Allocate the miptree's embedded HiZ miptree.
 505  * \see intel_mipmap_tree:hiz_mt
 506  * \return false if allocation failed
 507  */
 508
 509 bool
 510 intel_miptree_alloc_hiz(struct intel_context *intel,
 511                         struct intel_mipmap_tree *mt,
 512                         GLuint num_samples);
 513
 514 void
 515 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree *mt,
 516                                           uint32_t level,
 517                                           uint32_t depth);
 518 void
 519 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree *mt,
 520                                             uint32_t level,
 521                                             uint32_t depth);
 522
 523 /**
 524  * \return false if no resolve was needed
 525  */
 526 bool
 527 intel_miptree_slice_resolve_hiz(struct intel_context *intel,
 528                                 struct intel_mipmap_tree *mt,
 529                                 unsigned int level,
 530                                 unsigned int depth);
 531
 532 /**
 533  * \return false if no resolve was needed
 534  */
 535 bool
 536 intel_miptree_slice_resolve_depth(struct intel_context *intel,
 537                                   struct intel_mipmap_tree *mt,
 538                                   unsigned int level,
 539                                   unsigned int depth);
 540
 541 /**
 542  * \return false if no resolve was needed
 543  */
 544 bool
 545 intel_miptree_all_slices_resolve_hiz(struct intel_context *intel,
 546                                      struct intel_mipmap_tree *mt);
 547
 548 /**
 549  * \return false if no resolve was needed
 550  */
 551 bool
 552 intel_miptree_all_slices_resolve_depth(struct intel_context *intel,
 553                                        struct intel_mipmap_tree *mt);
 554
 555 /**\}*/
 556
 557 void
 558 intel_miptree_downsample(struct intel_context *intel,
 559                          struct intel_mipmap_tree *mt);
 560
 561 void
 562 intel_miptree_upsample(struct intel_context *intel,
 563                        struct intel_mipmap_tree *mt);
 564
 565 /* i915_mipmap_tree.c:
 566  */
 567 void i915_miptree_layout(struct intel_mipmap_tree *mt);
 568 void i945_miptree_layout(struct intel_mipmap_tree *mt);
 569 void brw_miptree_layout(struct intel_context *intel,
 570                         struct intel_mipmap_tree *mt);
 571
 572 void
 573 intel_miptree_map(struct intel_context *intel,
 574                   struct intel_mipmap_tree *mt,
 575                   unsigned int level,
 576                   unsigned int slice,
 577                   unsigned int x,
 578                   unsigned int y,
 579                   unsigned int w,
 580                   unsigned int h,
 581                   GLbitfield mode,
 582                   void **out_ptr,
 583                   int *out_stride);
 584
 585 void
 586 intel_miptree_unmap(struct intel_context *intel,
 587                     struct intel_mipmap_tree *mt,
 588                     unsigned int level,
 589                     unsigned int slice);
 590
 591 #ifdef I915
 592 static inline void
 593 intel_hiz_exec(struct intel_context *intel, struct intel_mipmap_tree *mt,
 594                unsigned int level, unsigned int layer, enum gen6_hiz_op op)
 595 {
 596    /* Stub on i915.  It would be nice if we didn't execute resolve code at all
 597     * there.
 598     */
 599 }
 600 #else
 601 void
 602 intel_hiz_exec(struct intel_context *intel, struct intel_mipmap_tree *mt,
 603                unsigned int level, unsigned int layer, enum gen6_hiz_op op);
 604 #endif
 605
 606 #ifdef __cplusplus
 607 }
 608 #endif
 609
 610 #endif