src/mesa/drivers/dri/intel/intel_mipmap_tree.h

   1 /**************************************************************************
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   3  * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
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  16  * of the Software.
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  27
  28 #ifndef INTEL_MIPMAP_TREE_H
  29 #define INTEL_MIPMAP_TREE_H
  30
  31 #include <assert.h>
  32
  33 #include "intel_regions.h"
  34 #include "intel_resolve_map.h"
  35
  36 #ifdef __cplusplus
  37 extern "C" {
  38 #endif
  39
  40 /* A layer on top of the intel_regions code which adds:
  41  *
  42  * - Code to size and layout a region to hold a set of mipmaps.
  43  * - Query to determine if a new image fits in an existing tree.
  44  * - More refcounting
  45  *     - maybe able to remove refcounting from intel_region?
  46  * - ?
  47  *
  48  * The fixed mipmap layout of intel hardware where one offset
  49  * specifies the position of all images in a mipmap hierachy
  50  * complicates the implementation of GL texture image commands,
  51  * compared to hardware where each image is specified with an
  52  * independent offset.
  53  *
  54  * In an ideal world, each texture object would be associated with a
  55  * single bufmgr buffer or 2d intel_region, and all the images within
  56  * the texture object would slot into the tree as they arrive.  The
  57  * reality can be a little messier, as images can arrive from the user
  58  * with sizes that don't fit in the existing tree, or in an order
  59  * where the tree layout cannot be guessed immediately.
  60  *
  61  * This structure encodes an idealized mipmap tree.  The GL image
  62  * commands build these where possible, otherwise store the images in
  63  * temporary system buffers.
  64  */
  65
  66 struct intel_resolve_map;
  67 struct intel_texture_image;
  68
  69 struct intel_miptree_map {
  70    /** Bitfield of GL_MAP_READ_BIT, GL_MAP_WRITE_BIT, GL_MAP_INVALIDATE_BIT */
  71    GLbitfield mode;
  72    /** Region of interest for the map. */
  73    int x, y, w, h;
  74    /** Possibly malloced temporary buffer for the mapping. */
  75    void *buffer;
  76    /** Possible pointer to a BO temporary for the mapping. */
  77    drm_intel_bo *bo;
  78    /** Pointer to the start of (map_x, map_y) returned by the mapping. */
  79    void *ptr;
  80    /** Stride of the mapping. */
  81    int stride;
  82
  83    /**
  84     * intel_mipmap_tree::singlesample_mt is temporary storage that persists
  85     * only for the duration of the map.
  86     */
  87    bool singlesample_mt_is_tmp;
  88 };
  89
  90 /**
  91  * Describes the location of each texture image within a texture region.
  92  */
  93 struct intel_mipmap_level
  94 {
  95    /** Offset to this miptree level, used in computing x_offset. */
  96    GLuint level_x;
  97    /** Offset to this miptree level, used in computing y_offset. */
  98    GLuint level_y;
  99    GLuint width;
 100    GLuint height;
 101
 102    /**
 103     * \brief Number of 2D slices in this miplevel.
 104     *
 105     * The exact semantics of depth varies according to the texture target:
 106     *    - For GL_TEXTURE_CUBE_MAP, depth is 6.
 107     *    - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
 108     *      identical for all miplevels in the texture.
 109     *    - For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its
 110     *      value, like width and height, varies with miplevel.
 111     *    - For other texture types, depth is 1.
 112     */
 113    GLuint depth;
 114
 115    /**
 116     * \brief List of 2D images in this mipmap level.
 117     *
 118     * This may be a list of cube faces, array slices in 2D array texture, or
 119     * layers in a 3D texture. The list's length is \c depth.
 120     */
 121    struct intel_mipmap_slice {
 122       /**
 123        * \name Offset to slice
 124        * \{
 125        *
 126        * Hardware formats are so diverse that that there is no unified way to
 127        * compute the slice offsets, so we store them in this table.
 128        *
 129        * The (x, y) offset to slice \c s at level \c l relative the miptrees
 130        * base address is
 131        * \code
 132        *     x = mt->level[l].slice[s].x_offset
 133        *     y = mt->level[l].slice[s].y_offset
 134        */
 135       GLuint x_offset;
 136       GLuint y_offset;
 137       /** \} */
 138
 139       /**
 140        * Mapping information. Persistent for the duration of
 141        * intel_miptree_map/unmap on this slice.
 142        */
 143       struct intel_miptree_map *map;
 144    } *slice;
 145 };
 146
 147 /**
 148  * Enum for keeping track of the different MSAA layouts supported by Gen7.
 149  */
 150 enum intel_msaa_layout
 151 {
 152    /**
 153     * Ordinary surface with no MSAA.
 154     */
 155    INTEL_MSAA_LAYOUT_NONE,
 156
 157    /**
 158     * Interleaved Multisample Surface.  The additional samples are
 159     * accommodated by scaling up the width and the height of the surface so
 160     * that all the samples corresponding to a pixel are located at nearby
 161     * memory locations.
 162     */
 163    INTEL_MSAA_LAYOUT_IMS,
 164
 165    /**
 166     * Uncompressed Multisample Surface.  The surface is stored as a 2D array,
 167     * with array slice n containing all pixel data for sample n.
 168     */
 169    INTEL_MSAA_LAYOUT_UMS,
 170
 171    /**
 172     * Compressed Multisample Surface.  The surface is stored as in
 173     * INTEL_MSAA_LAYOUT_UMS, but there is an additional buffer called the MCS
 174     * (Multisample Control Surface) buffer.  Each pixel in the MCS buffer
 175     * indicates the mapping from sample number to array slice.  This allows
 176     * the common case (where all samples constituting a pixel have the same
 177     * color value) to be stored efficiently by just using a single array
 178     * slice.
 179     */
 180    INTEL_MSAA_LAYOUT_CMS,
 181 };
 182
 183 struct intel_mipmap_tree
 184 {
 185    /* Effectively the key:
 186     */
 187    GLenum target;
 188
 189    /**
 190     * Generally, this is just the same as the gl_texture_image->TexFormat or
 191     * gl_renderbuffer->Format.
 192     *
 193     * However, for textures and renderbuffers with packed depth/stencil formats
 194     * on hardware where we want or need to use separate stencil, there will be
 195     * two miptrees for storing the data.  If the depthstencil texture or rb is
 196     * MESA_FORMAT_Z32_FLOAT_X24S8, then mt->format will be
 197     * MESA_FORMAT_Z32_FLOAT, otherwise for MESA_FORMAT_S8_Z24 objects it will be
 198     * MESA_FORMAT_X8_Z24.
 199     *
 200     * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
 201     * formats if the hardware lacks support for ETC1/ETC2. See @ref wraps_etc.
 202     */
 203    gl_format format;
 204
 205    /** This variable stores the value of ETC compressed texture format */
 206    gl_format etc_format;
 207
 208    /**
 209     * The X offset of each image in the miptree must be aligned to this. See
 210     * the "Alignment Unit Size" section of the BSpec.
 211     */
 212    unsigned int align_w;
 213    unsigned int align_h; /**< \see align_w */
 214
 215    GLuint first_level;
 216    GLuint last_level;
 217
 218    /**
 219     * Level zero image dimensions.  These dimensions correspond to the
 220     * physical layout of data in memory.  Accordingly, they account for the
 221     * extra width, height, and or depth that must be allocated in order to
 222     * accommodate multisample formats, and they account for the extra factor
 223     * of 6 in depth that must be allocated in order to accommodate cubemap
 224     * textures.
 225     */
 226    GLuint physical_width0, physical_height0, physical_depth0;
 227
 228    GLuint cpp;
 229    GLuint num_samples;
 230    bool compressed;
 231
 232    /**
 233     * Level zero image dimensions.  These dimensions correspond to the
 234     * logical width, height, and depth of the region as seen by client code.
 235     * Accordingly, they do not account for the extra width, height, and/or
 236     * depth that must be allocated in order to accommodate multisample
 237     * formats, nor do they account for the extra factor of 6 in depth that
 238     * must be allocated in order to accommodate cubemap textures.
 239     */
 240    uint32_t logical_width0, logical_height0, logical_depth0;
 241
 242    /**
 243     * For 1D array, 2D array, cube, and 2D multisampled surfaces on Gen7: true
 244     * if the surface only contains LOD 0, and hence no space is for LOD's
 245     * other than 0 in between array slices.
 246     *
 247     * Corresponds to the surface_array_spacing bit in gen7_surface_state.
 248     */
 249    bool array_spacing_lod0;
 250
 251    /**
 252     * MSAA layout used by this buffer.
 253     */
 254    enum intel_msaa_layout msaa_layout;
 255
 256    /* Derived from the above:
 257     */
 258    GLuint total_width;
 259    GLuint total_height;
 260
 261    /* The 3DSTATE_CLEAR_PARAMS value associated with the last depth clear to
 262     * this depth mipmap tree, if any.
 263     */
 264    uint32_t depth_clear_value;
 265
 266    /* Includes image offset tables:
 267     */
 268    struct intel_mipmap_level level[MAX_TEXTURE_LEVELS];
 269
 270    /* The data is held here:
 271     */
 272    struct intel_region *region;
 273
 274    /* Offset into region bo where miptree starts:
 275     */
 276    uint32_t offset;
 277
 278    /**
 279     * \brief Singlesample miptree.
 280     *
 281     * This is used under two cases.
 282     *
 283     * --- Case 1: As persistent singlesample storage for multisample window
 284     *  system front and back buffers ---
 285     *
 286     * Suppose that the window system FBO was created with a multisample
 287     * config.  Let `back_irb` be the `intel_renderbuffer` for the FBO's back
 288     * buffer. Then `back_irb` contains two miptrees: a parent multisample
 289     * miptree (back_irb->mt) and a child singlesample miptree
 290     * (back_irb->mt->singlesample_mt).  The DRM buffer shared with DRI2
 291     * belongs to `back_irb->mt->singlesample_mt` and contains singlesample
 292     * data.  The singlesample miptree is created at the same time as and
 293     * persists for the lifetime of its parent multisample miptree.
 294     *
 295     * When access to the singlesample data is needed, such as at
 296     * eglSwapBuffers and glReadPixels, an automatic downsample occurs from
 297     * `back_rb->mt` to `back_rb->mt->singlesample_mt` when necessary.
 298     *
 299     * This description of the back buffer applies analogously to the front
 300     * buffer.
 301     *
 302     *
 303     * --- Case 2: As temporary singlesample storage for mapping multisample
 304     *  miptrees ---
 305     *
 306     * Suppose the intel_miptree_map is called on a multisample miptree, `mt`,
 307     * for which case 1 does not apply (that is, `mt` does not belong to
 308     * a front or back buffer).  Then `mt->singlesample_mt` is null at the
 309     * start of the call. intel_miptree_map will create a temporary
 310     * singlesample miptree, store it at `mt->singlesample_mt`, downsample from
 311     * `mt` to `mt->singlesample_mt` if necessary, then map
 312     * `mt->singlesample_mt`. The temporary miptree is later deleted during
 313     * intel_miptree_unmap.
 314     */
 315    struct intel_mipmap_tree *singlesample_mt;
 316
 317    /**
 318     * \brief A downsample is needed from this miptree to singlesample_mt.
 319     */
 320    bool need_downsample;
 321
 322    /**
 323     * \brief HiZ miptree
 324     *
 325     * This is non-null only if HiZ is enabled for this miptree.
 326     *
 327     * \see intel_miptree_alloc_hiz()
 328     */
 329    struct intel_mipmap_tree *hiz_mt;
 330
 331    /**
 332     * \brief Map of miptree slices to needed resolves.
 333     *
 334     * This is used only when the miptree has a child HiZ miptree.
 335     *
 336     * Let \c mt be a depth miptree with HiZ enabled. Then the resolve map is
 337     * \c mt->hiz_map. The resolve map of the child HiZ miptree, \c
 338     * mt->hiz_mt->hiz_map, is unused.
 339     */
 340    struct intel_resolve_map hiz_map;
 341
 342    /**
 343     * \brief Stencil miptree for depthstencil textures.
 344     *
 345     * This miptree is used for depthstencil textures and renderbuffers that
 346     * require separate stencil.  It always has the true copy of the stencil
 347     * bits, regardless of mt->format.
 348     *
 349     * \see intel_miptree_map_depthstencil()
 350     * \see intel_miptree_unmap_depthstencil()
 351     */
 352    struct intel_mipmap_tree *stencil_mt;
 353
 354    /**
 355     * \brief MCS miptree for multisampled textures.
 356     *
 357     * This miptree contains the "multisample control surface", which stores
 358     * the necessary information to implement compressed MSAA on Gen7+
 359     * (INTEL_MSAA_FORMAT_CMS).
 360     */
 361    struct intel_mipmap_tree *mcs_mt;
 362
 363    /**
 364     * \brief The miptree contains uncompressed data that was originally
 365     * ETC1/ETC2 data.
 366     *
 367     * On hardware that lacks support for ETC1/ETC2 textures, we do the following
 368     * on calls to glCompressedTexImage2D() with an ETC1/ETC2 texture format:
 369     *   1. Create a miptree whose format is a suitable uncompressed mesa format
 370     *      with the wraps_etc flag set.
 371     *   2. Translate the ETC1/ETC2 data into uncompressed mesa format.
 372     *   3. Store the uncompressed  data into the miptree and discard the ETC1/ETC2
 373     *      data.
 374     */
 375    bool wraps_etc;
 376
 377    /* These are also refcounted:
 378     */
 379    GLuint refcount;
 380 };
 381
 382
 383
 384 struct intel_mipmap_tree *intel_miptree_create(struct intel_context *intel,
 385                                                GLenum target,
 386                                                gl_format format,
 387                                                GLuint first_level,
 388                                                GLuint last_level,
 389                                                GLuint width0,
 390                                                GLuint height0,
 391                                                GLuint depth0,
 392                                                bool expect_accelerated_upload,
 393                                                GLuint num_samples,
 394                                                bool force_y_tiling);
 395
 396 struct intel_mipmap_tree *
 397 intel_miptree_create_for_region(struct intel_context *intel,
 398                                 GLenum target,
 399                                 gl_format format,
 400                                 struct intel_region *region);
 401
 402 struct intel_mipmap_tree*
 403 intel_miptree_create_for_dri2_buffer(struct intel_context *intel,
 404                                      unsigned dri_attachment,
 405                                      gl_format format,
 406                                      uint32_t num_samples,
 407                                      struct intel_region *region);
 408
 409 /**
 410  * Create a miptree appropriate as the storage for a non-texture renderbuffer.
 411  * The miptree has the following properties:
 412  *     - The target is GL_TEXTURE_2D.
 413  *     - There are no levels other than the base level 0.
 414  *     - Depth is 1.
 415  */
 416 struct intel_mipmap_tree*
 417 intel_miptree_create_for_renderbuffer(struct intel_context *intel,
 418                                       gl_format format,
 419                                       uint32_t width,
 420                                       uint32_t height,
 421                                       uint32_t num_samples);
 422
 423 /** \brief Assert that the level and layer are valid for the miptree. */
 424 static inline void
 425 intel_miptree_check_level_layer(struct intel_mipmap_tree *mt,
 426                                 uint32_t level,
 427                                 uint32_t layer)
 428 {
 429    assert(level >= mt->first_level);
 430    assert(level <= mt->last_level);
 431    assert(layer < mt->level[level].depth);
 432 }
 433
 434 int intel_miptree_pitch_align (struct intel_context *intel,
 435                                struct intel_mipmap_tree *mt,
 436                                uint32_t tiling,
 437                                int pitch);
 438
 439 void intel_miptree_reference(struct intel_mipmap_tree **dst,
 440                              struct intel_mipmap_tree *src);
 441
 442 void intel_miptree_release(struct intel_mipmap_tree **mt);
 443
 444 /* Check if an image fits an existing mipmap tree layout
 445  */
 446 bool intel_miptree_match_image(struct intel_mipmap_tree *mt,
 447                                     struct gl_texture_image *image);
 448
 449 void
 450 intel_miptree_get_image_offset(struct intel_mipmap_tree *mt,
 451                                GLuint level, GLuint slice,
 452                                GLuint *x, GLuint *y);
 453
 454 void
 455 intel_miptree_get_dimensions_for_image(struct gl_texture_image *image,
 456                                        int *width, int *height, int *depth);
 457
 458 void intel_miptree_set_level_info(struct intel_mipmap_tree *mt,
 459                                   GLuint level,
 460                                   GLuint x, GLuint y,
 461                                   GLuint w, GLuint h, GLuint d);
 462
 463 void intel_miptree_set_image_offset(struct intel_mipmap_tree *mt,
 464                                     GLuint level,
 465                                     GLuint img, GLuint x, GLuint y);
 466
 467 void
 468 intel_miptree_copy_teximage(struct intel_context *intel,
 469                             struct intel_texture_image *intelImage,
 470                             struct intel_mipmap_tree *dst_mt);
 471
 472 /**
 473  * Copy the stencil data from \c mt->stencil_mt->region to \c mt->region for
 474  * the given miptree slice.
 475  *
 476  * \see intel_mipmap_tree::stencil_mt
 477  */
 478 void
 479 intel_miptree_s8z24_scatter(struct intel_context *intel,
 480                             struct intel_mipmap_tree *mt,
 481                             uint32_t level,
 482                             uint32_t slice);
 483
 484 /**
 485  * Copy the stencil data in \c mt->stencil_mt->region to \c mt->region for the
 486  * given miptree slice.
 487  *
 488  * \see intel_mipmap_tree::stencil_mt
 489  */
 490 void
 491 intel_miptree_s8z24_gather(struct intel_context *intel,
 492                            struct intel_mipmap_tree *mt,
 493                            uint32_t level,
 494                            uint32_t layer);
 495
 496 bool
 497 intel_miptree_alloc_mcs(struct intel_context *intel,
 498                         struct intel_mipmap_tree *mt,
 499                         GLuint num_samples);
 500
 501 /**
 502  * \name Miptree HiZ functions
 503  * \{
 504  *
 505  * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
 506  * functions on a miptree without HiZ. In that case, each function is a no-op.
 507  */
 508
 509 /**
 510  * \brief Allocate the miptree's embedded HiZ miptree.
 511  * \see intel_mipmap_tree:hiz_mt
 512  * \return false if allocation failed
 513  */
 514
 515 bool
 516 intel_miptree_alloc_hiz(struct intel_context *intel,
 517                         struct intel_mipmap_tree *mt,
 518                         GLuint num_samples);
 519
 520 void
 521 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree *mt,
 522                                           uint32_t level,
 523                                           uint32_t depth);
 524 void
 525 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree *mt,
 526                                             uint32_t level,
 527                                             uint32_t depth);
 528
 529 /**
 530  * \return false if no resolve was needed
 531  */
 532 bool
 533 intel_miptree_slice_resolve_hiz(struct intel_context *intel,
 534                                 struct intel_mipmap_tree *mt,
 535                                 unsigned int level,
 536                                 unsigned int depth);
 537
 538 /**
 539  * \return false if no resolve was needed
 540  */
 541 bool
 542 intel_miptree_slice_resolve_depth(struct intel_context *intel,
 543                                   struct intel_mipmap_tree *mt,
 544                                   unsigned int level,
 545                                   unsigned int depth);
 546
 547 /**
 548  * \return false if no resolve was needed
 549  */
 550 bool
 551 intel_miptree_all_slices_resolve_hiz(struct intel_context *intel,
 552                                      struct intel_mipmap_tree *mt);
 553
 554 /**
 555  * \return false if no resolve was needed
 556  */
 557 bool
 558 intel_miptree_all_slices_resolve_depth(struct intel_context *intel,
 559                                        struct intel_mipmap_tree *mt);
 560
 561 /**\}*/
 562
 563 void
 564 intel_miptree_downsample(struct intel_context *intel,
 565                          struct intel_mipmap_tree *mt);
 566
 567 void
 568 intel_miptree_upsample(struct intel_context *intel,
 569                        struct intel_mipmap_tree *mt);
 570
 571 /* i915_mipmap_tree.c:
 572  */
 573 void i915_miptree_layout(struct intel_mipmap_tree *mt);
 574 void i945_miptree_layout(struct intel_mipmap_tree *mt);
 575 void brw_miptree_layout(struct intel_context *intel,
 576                         struct intel_mipmap_tree *mt);
 577
 578 void
 579 intel_miptree_map(struct intel_context *intel,
 580                   struct intel_mipmap_tree *mt,
 581                   unsigned int level,
 582                   unsigned int slice,
 583                   unsigned int x,
 584                   unsigned int y,
 585                   unsigned int w,
 586                   unsigned int h,
 587                   GLbitfield mode,
 588                   void **out_ptr,
 589                   int *out_stride);
 590
 591 void
 592 intel_miptree_unmap(struct intel_context *intel,
 593                     struct intel_mipmap_tree *mt,
 594                     unsigned int level,
 595                     unsigned int slice);
 596
 597 #ifdef I915
 598 static inline void
 599 intel_hiz_exec(struct intel_context *intel, struct intel_mipmap_tree *mt,
 600                unsigned int level, unsigned int layer, enum gen6_hiz_op op)
 601 {
 602    /* Stub on i915.  It would be nice if we didn't execute resolve code at all
 603     * there.
 604     */
 605 }
 606 #else
 607 void
 608 intel_hiz_exec(struct intel_context *intel, struct intel_mipmap_tree *mt,
 609                unsigned int level, unsigned int layer, enum gen6_hiz_op op);
 610 #endif
 611
 612 #ifdef __cplusplus
 613 }
 614 #endif
 615
 616 #endif