1 /**************************************************************************
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
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11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #ifndef INTEL_MIPMAP_TREE_H
29 #define INTEL_MIPMAP_TREE_H
33 #include "intel_regions.h"
34 #include "intel_resolve_map.h"
40 /* A layer on top of the intel_regions code which adds:
42 * - Code to size and layout a region to hold a set of mipmaps.
43 * - Query to determine if a new image fits in an existing tree.
45 * - maybe able to remove refcounting from intel_region?
48 * The fixed mipmap layout of intel hardware where one offset
49 * specifies the position of all images in a mipmap hierachy
50 * complicates the implementation of GL texture image commands,
51 * compared to hardware where each image is specified with an
54 * In an ideal world, each texture object would be associated with a
55 * single bufmgr buffer or 2d intel_region, and all the images within
56 * the texture object would slot into the tree as they arrive. The
57 * reality can be a little messier, as images can arrive from the user
58 * with sizes that don't fit in the existing tree, or in an order
59 * where the tree layout cannot be guessed immediately.
61 * This structure encodes an idealized mipmap tree. The GL image
62 * commands build these where possible, otherwise store the images in
63 * temporary system buffers.
66 struct intel_resolve_map
;
67 struct intel_texture_image
;
70 * When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
71 * depthstencil-split-to-separate-stencil miptree, we'll normally make a
72 * tmeporary and recreate the kind of data requested by Mesa core, since we're
73 * satisfying some glGetTexImage() request or something.
75 * However, occasionally you want to actually map the miptree's current data
76 * without transcoding back. This flag to intel_miptree_map() gets you that.
78 #define BRW_MAP_DIRECT_BIT 0x80000000
80 struct intel_miptree_map
{
81 /** Bitfield of GL_MAP_READ_BIT, GL_MAP_WRITE_BIT, GL_MAP_INVALIDATE_BIT */
83 /** Region of interest for the map. */
85 /** Possibly malloced temporary buffer for the mapping. */
87 /** Possible pointer to a temporary linear miptree for the mapping. */
88 struct intel_mipmap_tree
*mt
;
89 /** Pointer to the start of (map_x, map_y) returned by the mapping. */
91 /** Stride of the mapping. */
95 * intel_mipmap_tree::singlesample_mt is temporary storage that persists
96 * only for the duration of the map.
98 bool singlesample_mt_is_tmp
;
102 * Describes the location of each texture image within a texture region.
104 struct intel_mipmap_level
106 /** Offset to this miptree level, used in computing x_offset. */
108 /** Offset to this miptree level, used in computing y_offset. */
114 * \brief Number of 2D slices in this miplevel.
116 * The exact semantics of depth varies according to the texture target:
117 * - For GL_TEXTURE_CUBE_MAP, depth is 6.
118 * - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
119 * identical for all miplevels in the texture.
120 * - For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its
121 * value, like width and height, varies with miplevel.
122 * - For other texture types, depth is 1.
127 * \brief List of 2D images in this mipmap level.
129 * This may be a list of cube faces, array slices in 2D array texture, or
130 * layers in a 3D texture. The list's length is \c depth.
132 struct intel_mipmap_slice
{
134 * \name Offset to slice
137 * Hardware formats are so diverse that that there is no unified way to
138 * compute the slice offsets, so we store them in this table.
140 * The (x, y) offset to slice \c s at level \c l relative the miptrees
143 * x = mt->level[l].slice[s].x_offset
144 * y = mt->level[l].slice[s].y_offset
151 * Mapping information. Persistent for the duration of
152 * intel_miptree_map/unmap on this slice.
154 struct intel_miptree_map
*map
;
157 * \brief Is HiZ enabled for this slice?
159 * If \c mt->level[l].slice[s].has_hiz is set, then (1) \c mt->hiz_mt
160 * has been allocated and (2) the HiZ memory corresponding to this slice
161 * resides at \c mt->hiz_mt->level[l].slice[s].
168 * Enum for keeping track of the different MSAA layouts supported by Gen7.
170 enum intel_msaa_layout
173 * Ordinary surface with no MSAA.
175 INTEL_MSAA_LAYOUT_NONE
,
178 * Interleaved Multisample Surface. The additional samples are
179 * accommodated by scaling up the width and the height of the surface so
180 * that all the samples corresponding to a pixel are located at nearby
183 INTEL_MSAA_LAYOUT_IMS
,
186 * Uncompressed Multisample Surface. The surface is stored as a 2D array,
187 * with array slice n containing all pixel data for sample n.
189 INTEL_MSAA_LAYOUT_UMS
,
192 * Compressed Multisample Surface. The surface is stored as in
193 * INTEL_MSAA_LAYOUT_UMS, but there is an additional buffer called the MCS
194 * (Multisample Control Surface) buffer. Each pixel in the MCS buffer
195 * indicates the mapping from sample number to array slice. This allows
196 * the common case (where all samples constituting a pixel have the same
197 * color value) to be stored efficiently by just using a single array
200 INTEL_MSAA_LAYOUT_CMS
,
206 * Enum for keeping track of the state of an MCS buffer associated with a
207 * miptree. This determines when fast clear related operations are needed.
209 * Fast clear works by deferring the memory writes that would be used to clear
210 * the buffer, so that instead of performing them at the time of the clear
211 * operation, the hardware automatically performs them at the time that the
212 * buffer is later accessed for rendering. The MCS buffer keeps track of
213 * which regions of the buffer still have pending clear writes.
215 * This enum keeps track of the driver's knowledge of the state of the MCS
218 * MCS buffers only exist on Gen7+.
223 * There is no MCS buffer for this miptree, and one should never be
226 INTEL_MCS_STATE_NONE
,
229 * An MCS buffer exists for this miptree, and it is used for MSAA purposes.
231 INTEL_MCS_STATE_MSAA
,
234 * No deferred clears are pending for this miptree, and the contents of the
235 * color buffer are entirely correct. An MCS buffer may or may not exist
236 * for this miptree. If it does exist, it is entirely in the "no deferred
237 * clears pending" state. If it does not exist, it will be created the
238 * first time a fast color clear is executed.
240 * In this state, the color buffer can be used for purposes other than
241 * rendering without needing a render target resolve.
243 INTEL_MCS_STATE_RESOLVED
,
246 * An MCS buffer exists for this miptree, and deferred clears are pending
247 * for some regions of the color buffer, as indicated by the MCS buffer.
248 * The contents of the color buffer are only correct for the regions where
249 * the MCS buffer doesn't indicate a deferred clear.
251 * In this state, a render target resolve must be performed before the
252 * color buffer can be used for purposes other than rendering.
254 INTEL_MCS_STATE_UNRESOLVED
,
257 * An MCS buffer exists for this miptree, and deferred clears are pending
258 * for the entire color buffer, and the contents of the MCS buffer reflect
259 * this. The contents of the color buffer are undefined.
261 * In this state, a render target resolve must be performed before the
262 * color buffer can be used for purposes other than rendering.
264 * If the client attempts to clear a buffer which is already in this state,
265 * the clear can be safely skipped, since the buffer is already clear.
267 INTEL_MCS_STATE_CLEAR
,
271 struct intel_mipmap_tree
273 /* Effectively the key:
278 * Generally, this is just the same as the gl_texture_image->TexFormat or
279 * gl_renderbuffer->Format.
281 * However, for textures and renderbuffers with packed depth/stencil formats
282 * on hardware where we want or need to use separate stencil, there will be
283 * two miptrees for storing the data. If the depthstencil texture or rb is
284 * MESA_FORMAT_Z32_FLOAT_X24S8, then mt->format will be
285 * MESA_FORMAT_Z32_FLOAT, otherwise for MESA_FORMAT_S8_Z24 objects it will be
286 * MESA_FORMAT_X8_Z24.
288 * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
289 * formats if the hardware lacks support for ETC1/ETC2. See @ref wraps_etc.
293 /** This variable stores the value of ETC compressed texture format */
294 gl_format etc_format
;
297 * The X offset of each image in the miptree must be aligned to this. See
298 * the "Alignment Unit Size" section of the BSpec.
300 unsigned int align_w
;
301 unsigned int align_h
; /**< \see align_w */
307 * Level zero image dimensions. These dimensions correspond to the
308 * physical layout of data in memory. Accordingly, they account for the
309 * extra width, height, and or depth that must be allocated in order to
310 * accommodate multisample formats, and they account for the extra factor
311 * of 6 in depth that must be allocated in order to accommodate cubemap
314 GLuint physical_width0
, physical_height0
, physical_depth0
;
321 * Level zero image dimensions. These dimensions correspond to the
322 * logical width, height, and depth of the region as seen by client code.
323 * Accordingly, they do not account for the extra width, height, and/or
324 * depth that must be allocated in order to accommodate multisample
325 * formats, nor do they account for the extra factor of 6 in depth that
326 * must be allocated in order to accommodate cubemap textures.
328 uint32_t logical_width0
, logical_height0
, logical_depth0
;
331 * For 1D array, 2D array, cube, and 2D multisampled surfaces on Gen7: true
332 * if the surface only contains LOD 0, and hence no space is for LOD's
333 * other than 0 in between array slices.
335 * Corresponds to the surface_array_spacing bit in gen7_surface_state.
337 bool array_spacing_lod0
;
340 * MSAA layout used by this buffer.
342 enum intel_msaa_layout msaa_layout
;
344 /* Derived from the above:
349 /* The 3DSTATE_CLEAR_PARAMS value associated with the last depth clear to
350 * this depth mipmap tree, if any.
352 uint32_t depth_clear_value
;
354 /* Includes image offset tables:
356 struct intel_mipmap_level level
[MAX_TEXTURE_LEVELS
];
358 /* The data is held here:
360 struct intel_region
*region
;
362 /* Offset into region bo where miptree starts:
367 * \brief Singlesample miptree.
369 * This is used under two cases.
371 * --- Case 1: As persistent singlesample storage for multisample window
372 * system front and back buffers ---
374 * Suppose that the window system FBO was created with a multisample
375 * config. Let `back_irb` be the `intel_renderbuffer` for the FBO's back
376 * buffer. Then `back_irb` contains two miptrees: a parent multisample
377 * miptree (back_irb->mt) and a child singlesample miptree
378 * (back_irb->mt->singlesample_mt). The DRM buffer shared with DRI2
379 * belongs to `back_irb->mt->singlesample_mt` and contains singlesample
380 * data. The singlesample miptree is created at the same time as and
381 * persists for the lifetime of its parent multisample miptree.
383 * When access to the singlesample data is needed, such as at
384 * eglSwapBuffers and glReadPixels, an automatic downsample occurs from
385 * `back_rb->mt` to `back_rb->mt->singlesample_mt` when necessary.
387 * This description of the back buffer applies analogously to the front
391 * --- Case 2: As temporary singlesample storage for mapping multisample
394 * Suppose the intel_miptree_map is called on a multisample miptree, `mt`,
395 * for which case 1 does not apply (that is, `mt` does not belong to
396 * a front or back buffer). Then `mt->singlesample_mt` is null at the
397 * start of the call. intel_miptree_map will create a temporary
398 * singlesample miptree, store it at `mt->singlesample_mt`, downsample from
399 * `mt` to `mt->singlesample_mt` if necessary, then map
400 * `mt->singlesample_mt`. The temporary miptree is later deleted during
401 * intel_miptree_unmap.
403 struct intel_mipmap_tree
*singlesample_mt
;
406 * \brief A downsample is needed from this miptree to singlesample_mt.
408 bool need_downsample
;
413 * The hiz miptree contains the miptree's hiz buffer. To allocate the hiz
414 * miptree, use intel_miptree_alloc_hiz().
416 * To determine if hiz is enabled, do not check this pointer. Instead, use
417 * intel_miptree_slice_has_hiz().
419 struct intel_mipmap_tree
*hiz_mt
;
422 * \brief Map of miptree slices to needed resolves.
424 * This is used only when the miptree has a child HiZ miptree.
426 * Let \c mt be a depth miptree with HiZ enabled. Then the resolve map is
427 * \c mt->hiz_map. The resolve map of the child HiZ miptree, \c
428 * mt->hiz_mt->hiz_map, is unused.
430 struct intel_resolve_map hiz_map
;
433 * \brief Stencil miptree for depthstencil textures.
435 * This miptree is used for depthstencil textures and renderbuffers that
436 * require separate stencil. It always has the true copy of the stencil
437 * bits, regardless of mt->format.
439 * \see intel_miptree_map_depthstencil()
440 * \see intel_miptree_unmap_depthstencil()
442 struct intel_mipmap_tree
*stencil_mt
;
446 * \brief MCS miptree.
448 * This miptree contains the "multisample control surface", which stores
449 * the necessary information to implement compressed MSAA
450 * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+.
452 * NULL if no MCS miptree is in use for this surface.
454 struct intel_mipmap_tree
*mcs_mt
;
457 * MCS state for this buffer.
459 enum intel_mcs_state mcs_state
;
463 * The SURFACE_STATE bits associated with the last fast color clear to this
464 * color mipmap tree, if any.
466 * This value will only ever contain ones in bits 28-31, so it is safe to
467 * OR into dword 7 of SURFACE_STATE.
469 uint32_t fast_clear_color_value
;
471 /* These are also refcounted:
476 enum intel_miptree_tiling_mode
{
477 INTEL_MIPTREE_TILING_ANY
,
478 INTEL_MIPTREE_TILING_Y
,
479 INTEL_MIPTREE_TILING_NONE
,
483 intel_is_non_msrt_mcs_buffer_supported(struct intel_context
*intel
,
484 struct intel_mipmap_tree
*mt
);
487 intel_get_non_msrt_mcs_alignment(struct intel_context
*intel
,
488 struct intel_mipmap_tree
*mt
,
489 unsigned *width_px
, unsigned *height
);
492 intel_miptree_alloc_non_msrt_mcs(struct intel_context
*intel
,
493 struct intel_mipmap_tree
*mt
);
495 struct intel_mipmap_tree
*intel_miptree_create(struct intel_context
*intel
,
503 bool expect_accelerated_upload
,
505 enum intel_miptree_tiling_mode
);
507 struct intel_mipmap_tree
*
508 intel_miptree_create_layout(struct intel_context
*intel
,
519 struct intel_mipmap_tree
*
520 intel_miptree_create_for_bo(struct intel_context
*intel
,
529 struct intel_mipmap_tree
*
530 intel_miptree_create_for_dri2_buffer(struct intel_context
*intel
,
531 unsigned dri_attachment
,
533 uint32_t num_samples
,
534 struct intel_region
*region
);
537 * Create a miptree appropriate as the storage for a non-texture renderbuffer.
538 * The miptree has the following properties:
539 * - The target is GL_TEXTURE_2D.
540 * - There are no levels other than the base level 0.
543 struct intel_mipmap_tree
*
544 intel_miptree_create_for_renderbuffer(struct intel_context
*intel
,
548 uint32_t num_samples
);
550 /** \brief Assert that the level and layer are valid for the miptree. */
552 intel_miptree_check_level_layer(struct intel_mipmap_tree
*mt
,
556 assert(level
>= mt
->first_level
);
557 assert(level
<= mt
->last_level
);
558 assert(layer
< mt
->level
[level
].depth
);
561 int intel_miptree_pitch_align (struct intel_context
*intel
,
562 struct intel_mipmap_tree
*mt
,
566 void intel_miptree_reference(struct intel_mipmap_tree
**dst
,
567 struct intel_mipmap_tree
*src
);
569 void intel_miptree_release(struct intel_mipmap_tree
**mt
);
571 /* Check if an image fits an existing mipmap tree layout
573 bool intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
574 struct gl_texture_image
*image
);
577 intel_miptree_get_image_offset(struct intel_mipmap_tree
*mt
,
578 GLuint level
, GLuint slice
,
579 GLuint
*x
, GLuint
*y
);
582 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
583 int *width
, int *height
, int *depth
);
586 intel_miptree_get_tile_offsets(struct intel_mipmap_tree
*mt
,
587 GLuint level
, GLuint slice
,
591 void intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
594 GLuint w
, GLuint h
, GLuint d
);
596 void intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
598 GLuint img
, GLuint x
, GLuint y
);
601 intel_miptree_copy_teximage(struct intel_context
*intel
,
602 struct intel_texture_image
*intelImage
,
603 struct intel_mipmap_tree
*dst_mt
, bool invalidate
);
606 * Copy the stencil data from \c mt->stencil_mt->region to \c mt->region for
607 * the given miptree slice.
609 * \see intel_mipmap_tree::stencil_mt
612 intel_miptree_s8z24_scatter(struct intel_context
*intel
,
613 struct intel_mipmap_tree
*mt
,
618 * Copy the stencil data in \c mt->stencil_mt->region to \c mt->region for the
619 * given miptree slice.
621 * \see intel_mipmap_tree::stencil_mt
624 intel_miptree_s8z24_gather(struct intel_context
*intel
,
625 struct intel_mipmap_tree
*mt
,
630 intel_miptree_alloc_mcs(struct intel_context
*intel
,
631 struct intel_mipmap_tree
*mt
,
635 * \name Miptree HiZ functions
638 * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
639 * functions on a miptree without HiZ. In that case, each function is a no-op.
643 * \brief Allocate the miptree's embedded HiZ miptree.
644 * \see intel_mipmap_tree:hiz_mt
645 * \return false if allocation failed
649 intel_miptree_alloc_hiz(struct intel_context
*intel
,
650 struct intel_mipmap_tree
*mt
);
653 intel_miptree_slice_has_hiz(struct intel_mipmap_tree
*mt
,
658 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
662 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
667 * \return false if no resolve was needed
670 intel_miptree_slice_resolve_hiz(struct intel_context
*intel
,
671 struct intel_mipmap_tree
*mt
,
676 * \return false if no resolve was needed
679 intel_miptree_slice_resolve_depth(struct intel_context
*intel
,
680 struct intel_mipmap_tree
*mt
,
685 * \return false if no resolve was needed
688 intel_miptree_all_slices_resolve_hiz(struct intel_context
*intel
,
689 struct intel_mipmap_tree
*mt
);
692 * \return false if no resolve was needed
695 intel_miptree_all_slices_resolve_depth(struct intel_context
*intel
,
696 struct intel_mipmap_tree
*mt
);
701 * Update the fast clear state for a miptree to indicate that it has been used
705 intel_miptree_used_for_rendering(struct intel_mipmap_tree
*mt
)
708 /* Nothing needs to be done for I915, since it doesn't support fast
712 /* If the buffer was previously in fast clear state, change it to
713 * unresolved state, since it won't be guaranteed to be clear after
716 if (mt
->mcs_state
== INTEL_MCS_STATE_CLEAR
)
717 mt
->mcs_state
= INTEL_MCS_STATE_UNRESOLVED
;
722 intel_miptree_downsample(struct intel_context
*intel
,
723 struct intel_mipmap_tree
*mt
);
726 intel_miptree_upsample(struct intel_context
*intel
,
727 struct intel_mipmap_tree
*mt
);
729 /* i915_mipmap_tree.c:
731 void i915_miptree_layout(struct intel_mipmap_tree
*mt
);
732 void i945_miptree_layout(struct intel_mipmap_tree
*mt
);
733 void brw_miptree_layout(struct intel_context
*intel
,
734 struct intel_mipmap_tree
*mt
);
736 void *intel_miptree_map_raw(struct intel_context
*intel
,
737 struct intel_mipmap_tree
*mt
);
739 void intel_miptree_unmap_raw(struct intel_context
*intel
,
740 struct intel_mipmap_tree
*mt
);
743 intel_miptree_map(struct intel_context
*intel
,
744 struct intel_mipmap_tree
*mt
,
756 intel_miptree_unmap(struct intel_context
*intel
,
757 struct intel_mipmap_tree
*mt
,
763 intel_hiz_exec(struct intel_context
*intel
, struct intel_mipmap_tree
*mt
,
764 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
)
766 /* Stub on i915. It would be nice if we didn't execute resolve code at all
772 intel_hiz_exec(struct intel_context
*intel
, struct intel_mipmap_tree
*mt
,
773 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);