1 /**************************************************************************
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
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28 #ifndef INTEL_MIPMAP_TREE_H
29 #define INTEL_MIPMAP_TREE_H
33 #include "intel_regions.h"
34 #include "intel_resolve_map.h"
40 /* A layer on top of the intel_regions code which adds:
42 * - Code to size and layout a region to hold a set of mipmaps.
43 * - Query to determine if a new image fits in an existing tree.
45 * - maybe able to remove refcounting from intel_region?
48 * The fixed mipmap layout of intel hardware where one offset
49 * specifies the position of all images in a mipmap hierachy
50 * complicates the implementation of GL texture image commands,
51 * compared to hardware where each image is specified with an
54 * In an ideal world, each texture object would be associated with a
55 * single bufmgr buffer or 2d intel_region, and all the images within
56 * the texture object would slot into the tree as they arrive. The
57 * reality can be a little messier, as images can arrive from the user
58 * with sizes that don't fit in the existing tree, or in an order
59 * where the tree layout cannot be guessed immediately.
61 * This structure encodes an idealized mipmap tree. The GL image
62 * commands build these where possible, otherwise store the images in
63 * temporary system buffers.
66 struct intel_resolve_map
;
67 struct intel_texture_image
;
70 * When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
71 * depthstencil-split-to-separate-stencil miptree, we'll normally make a
72 * tmeporary and recreate the kind of data requested by Mesa core, since we're
73 * satisfying some glGetTexImage() request or something.
75 * However, occasionally you want to actually map the miptree's current data
76 * without transcoding back. This flag to intel_miptree_map() gets you that.
78 #define BRW_MAP_DIRECT_BIT 0x80000000
80 struct intel_miptree_map
{
81 /** Bitfield of GL_MAP_READ_BIT, GL_MAP_WRITE_BIT, GL_MAP_INVALIDATE_BIT */
83 /** Region of interest for the map. */
85 /** Possibly malloced temporary buffer for the mapping. */
87 /** Possible pointer to a temporary linear miptree for the mapping. */
88 struct intel_mipmap_tree
*mt
;
89 /** Pointer to the start of (map_x, map_y) returned by the mapping. */
91 /** Stride of the mapping. */
95 * intel_mipmap_tree::singlesample_mt is temporary storage that persists
96 * only for the duration of the map.
98 bool singlesample_mt_is_tmp
;
102 * Describes the location of each texture image within a texture region.
104 struct intel_mipmap_level
106 /** Offset to this miptree level, used in computing x_offset. */
108 /** Offset to this miptree level, used in computing y_offset. */
114 * \brief Number of 2D slices in this miplevel.
116 * The exact semantics of depth varies according to the texture target:
117 * - For GL_TEXTURE_CUBE_MAP, depth is 6.
118 * - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
119 * identical for all miplevels in the texture.
120 * - For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its
121 * value, like width and height, varies with miplevel.
122 * - For other texture types, depth is 1.
127 * \brief List of 2D images in this mipmap level.
129 * This may be a list of cube faces, array slices in 2D array texture, or
130 * layers in a 3D texture. The list's length is \c depth.
132 struct intel_mipmap_slice
{
134 * \name Offset to slice
137 * Hardware formats are so diverse that that there is no unified way to
138 * compute the slice offsets, so we store them in this table.
140 * The (x, y) offset to slice \c s at level \c l relative the miptrees
143 * x = mt->level[l].slice[s].x_offset
144 * y = mt->level[l].slice[s].y_offset
151 * Mapping information. Persistent for the duration of
152 * intel_miptree_map/unmap on this slice.
154 struct intel_miptree_map
*map
;
157 * \brief Is HiZ enabled for this slice?
159 * If \c mt->level[l].slice[s].has_hiz is set, then (1) \c mt->hiz_mt
160 * has been allocated and (2) the HiZ memory corresponding to this slice
161 * resides at \c mt->hiz_mt->level[l].slice[s].
168 * Enum for keeping track of the different MSAA layouts supported by Gen7.
170 enum intel_msaa_layout
173 * Ordinary surface with no MSAA.
175 INTEL_MSAA_LAYOUT_NONE
,
178 * Interleaved Multisample Surface. The additional samples are
179 * accommodated by scaling up the width and the height of the surface so
180 * that all the samples corresponding to a pixel are located at nearby
183 INTEL_MSAA_LAYOUT_IMS
,
186 * Uncompressed Multisample Surface. The surface is stored as a 2D array,
187 * with array slice n containing all pixel data for sample n.
189 INTEL_MSAA_LAYOUT_UMS
,
192 * Compressed Multisample Surface. The surface is stored as in
193 * INTEL_MSAA_LAYOUT_UMS, but there is an additional buffer called the MCS
194 * (Multisample Control Surface) buffer. Each pixel in the MCS buffer
195 * indicates the mapping from sample number to array slice. This allows
196 * the common case (where all samples constituting a pixel have the same
197 * color value) to be stored efficiently by just using a single array
200 INTEL_MSAA_LAYOUT_CMS
,
203 struct intel_mipmap_tree
205 /* Effectively the key:
210 * Generally, this is just the same as the gl_texture_image->TexFormat or
211 * gl_renderbuffer->Format.
213 * However, for textures and renderbuffers with packed depth/stencil formats
214 * on hardware where we want or need to use separate stencil, there will be
215 * two miptrees for storing the data. If the depthstencil texture or rb is
216 * MESA_FORMAT_Z32_FLOAT_X24S8, then mt->format will be
217 * MESA_FORMAT_Z32_FLOAT, otherwise for MESA_FORMAT_S8_Z24 objects it will be
218 * MESA_FORMAT_X8_Z24.
220 * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
221 * formats if the hardware lacks support for ETC1/ETC2. See @ref wraps_etc.
225 /** This variable stores the value of ETC compressed texture format */
226 gl_format etc_format
;
229 * The X offset of each image in the miptree must be aligned to this. See
230 * the "Alignment Unit Size" section of the BSpec.
232 unsigned int align_w
;
233 unsigned int align_h
; /**< \see align_w */
239 * Level zero image dimensions. These dimensions correspond to the
240 * physical layout of data in memory. Accordingly, they account for the
241 * extra width, height, and or depth that must be allocated in order to
242 * accommodate multisample formats, and they account for the extra factor
243 * of 6 in depth that must be allocated in order to accommodate cubemap
246 GLuint physical_width0
, physical_height0
, physical_depth0
;
253 * Level zero image dimensions. These dimensions correspond to the
254 * logical width, height, and depth of the region as seen by client code.
255 * Accordingly, they do not account for the extra width, height, and/or
256 * depth that must be allocated in order to accommodate multisample
257 * formats, nor do they account for the extra factor of 6 in depth that
258 * must be allocated in order to accommodate cubemap textures.
260 uint32_t logical_width0
, logical_height0
, logical_depth0
;
263 * For 1D array, 2D array, cube, and 2D multisampled surfaces on Gen7: true
264 * if the surface only contains LOD 0, and hence no space is for LOD's
265 * other than 0 in between array slices.
267 * Corresponds to the surface_array_spacing bit in gen7_surface_state.
269 bool array_spacing_lod0
;
272 * MSAA layout used by this buffer.
274 enum intel_msaa_layout msaa_layout
;
276 /* Derived from the above:
281 /* The 3DSTATE_CLEAR_PARAMS value associated with the last depth clear to
282 * this depth mipmap tree, if any.
284 uint32_t depth_clear_value
;
286 /* Includes image offset tables:
288 struct intel_mipmap_level level
[MAX_TEXTURE_LEVELS
];
290 /* The data is held here:
292 struct intel_region
*region
;
294 /* Offset into region bo where miptree starts:
299 * \brief Singlesample miptree.
301 * This is used under two cases.
303 * --- Case 1: As persistent singlesample storage for multisample window
304 * system front and back buffers ---
306 * Suppose that the window system FBO was created with a multisample
307 * config. Let `back_irb` be the `intel_renderbuffer` for the FBO's back
308 * buffer. Then `back_irb` contains two miptrees: a parent multisample
309 * miptree (back_irb->mt) and a child singlesample miptree
310 * (back_irb->mt->singlesample_mt). The DRM buffer shared with DRI2
311 * belongs to `back_irb->mt->singlesample_mt` and contains singlesample
312 * data. The singlesample miptree is created at the same time as and
313 * persists for the lifetime of its parent multisample miptree.
315 * When access to the singlesample data is needed, such as at
316 * eglSwapBuffers and glReadPixels, an automatic downsample occurs from
317 * `back_rb->mt` to `back_rb->mt->singlesample_mt` when necessary.
319 * This description of the back buffer applies analogously to the front
323 * --- Case 2: As temporary singlesample storage for mapping multisample
326 * Suppose the intel_miptree_map is called on a multisample miptree, `mt`,
327 * for which case 1 does not apply (that is, `mt` does not belong to
328 * a front or back buffer). Then `mt->singlesample_mt` is null at the
329 * start of the call. intel_miptree_map will create a temporary
330 * singlesample miptree, store it at `mt->singlesample_mt`, downsample from
331 * `mt` to `mt->singlesample_mt` if necessary, then map
332 * `mt->singlesample_mt`. The temporary miptree is later deleted during
333 * intel_miptree_unmap.
335 struct intel_mipmap_tree
*singlesample_mt
;
338 * \brief A downsample is needed from this miptree to singlesample_mt.
340 bool need_downsample
;
345 * The hiz miptree contains the miptree's hiz buffer. To allocate the hiz
346 * miptree, use intel_miptree_alloc_hiz().
348 * To determine if hiz is enabled, do not check this pointer. Instead, use
349 * intel_miptree_slice_has_hiz().
351 struct intel_mipmap_tree
*hiz_mt
;
354 * \brief Map of miptree slices to needed resolves.
356 * This is used only when the miptree has a child HiZ miptree.
358 * Let \c mt be a depth miptree with HiZ enabled. Then the resolve map is
359 * \c mt->hiz_map. The resolve map of the child HiZ miptree, \c
360 * mt->hiz_mt->hiz_map, is unused.
362 struct intel_resolve_map hiz_map
;
365 * \brief Stencil miptree for depthstencil textures.
367 * This miptree is used for depthstencil textures and renderbuffers that
368 * require separate stencil. It always has the true copy of the stencil
369 * bits, regardless of mt->format.
371 * \see intel_miptree_map_depthstencil()
372 * \see intel_miptree_unmap_depthstencil()
374 struct intel_mipmap_tree
*stencil_mt
;
377 * \brief MCS miptree for multisampled textures.
379 * This miptree contains the "multisample control surface", which stores
380 * the necessary information to implement compressed MSAA on Gen7+
381 * (INTEL_MSAA_FORMAT_CMS).
383 struct intel_mipmap_tree
*mcs_mt
;
385 /* These are also refcounted:
390 enum intel_miptree_tiling_mode
{
391 INTEL_MIPTREE_TILING_ANY
,
392 INTEL_MIPTREE_TILING_Y
,
393 INTEL_MIPTREE_TILING_NONE
,
396 struct intel_mipmap_tree
*intel_miptree_create(struct intel_context
*intel
,
404 bool expect_accelerated_upload
,
406 enum intel_miptree_tiling_mode
);
408 struct intel_mipmap_tree
*
409 intel_miptree_create_layout(struct intel_context
*intel
,
420 struct intel_mipmap_tree
*
421 intel_miptree_create_for_bo(struct intel_context
*intel
,
430 struct intel_mipmap_tree
*
431 intel_miptree_create_for_dri2_buffer(struct intel_context
*intel
,
432 unsigned dri_attachment
,
434 uint32_t num_samples
,
435 struct intel_region
*region
);
438 * Create a miptree appropriate as the storage for a non-texture renderbuffer.
439 * The miptree has the following properties:
440 * - The target is GL_TEXTURE_2D.
441 * - There are no levels other than the base level 0.
444 struct intel_mipmap_tree
*
445 intel_miptree_create_for_renderbuffer(struct intel_context
*intel
,
449 uint32_t num_samples
);
451 /** \brief Assert that the level and layer are valid for the miptree. */
453 intel_miptree_check_level_layer(struct intel_mipmap_tree
*mt
,
457 assert(level
>= mt
->first_level
);
458 assert(level
<= mt
->last_level
);
459 assert(layer
< mt
->level
[level
].depth
);
462 int intel_miptree_pitch_align (struct intel_context
*intel
,
463 struct intel_mipmap_tree
*mt
,
467 void intel_miptree_reference(struct intel_mipmap_tree
**dst
,
468 struct intel_mipmap_tree
*src
);
470 void intel_miptree_release(struct intel_mipmap_tree
**mt
);
472 /* Check if an image fits an existing mipmap tree layout
474 bool intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
475 struct gl_texture_image
*image
);
478 intel_miptree_get_image_offset(struct intel_mipmap_tree
*mt
,
479 GLuint level
, GLuint slice
,
480 GLuint
*x
, GLuint
*y
);
483 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
484 int *width
, int *height
, int *depth
);
487 intel_miptree_get_tile_offsets(struct intel_mipmap_tree
*mt
,
488 GLuint level
, GLuint slice
,
492 void intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
495 GLuint w
, GLuint h
, GLuint d
);
497 void intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
499 GLuint img
, GLuint x
, GLuint y
);
502 intel_miptree_copy_teximage(struct intel_context
*intel
,
503 struct intel_texture_image
*intelImage
,
504 struct intel_mipmap_tree
*dst_mt
, bool invalidate
);
507 * Copy the stencil data from \c mt->stencil_mt->region to \c mt->region for
508 * the given miptree slice.
510 * \see intel_mipmap_tree::stencil_mt
513 intel_miptree_s8z24_scatter(struct intel_context
*intel
,
514 struct intel_mipmap_tree
*mt
,
519 * Copy the stencil data in \c mt->stencil_mt->region to \c mt->region for the
520 * given miptree slice.
522 * \see intel_mipmap_tree::stencil_mt
525 intel_miptree_s8z24_gather(struct intel_context
*intel
,
526 struct intel_mipmap_tree
*mt
,
531 intel_miptree_alloc_mcs(struct intel_context
*intel
,
532 struct intel_mipmap_tree
*mt
,
536 * \name Miptree HiZ functions
539 * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
540 * functions on a miptree without HiZ. In that case, each function is a no-op.
544 * \brief Allocate the miptree's embedded HiZ miptree.
545 * \see intel_mipmap_tree:hiz_mt
546 * \return false if allocation failed
550 intel_miptree_alloc_hiz(struct intel_context
*intel
,
551 struct intel_mipmap_tree
*mt
);
554 intel_miptree_slice_has_hiz(struct intel_mipmap_tree
*mt
,
559 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
563 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
568 * \return false if no resolve was needed
571 intel_miptree_slice_resolve_hiz(struct intel_context
*intel
,
572 struct intel_mipmap_tree
*mt
,
577 * \return false if no resolve was needed
580 intel_miptree_slice_resolve_depth(struct intel_context
*intel
,
581 struct intel_mipmap_tree
*mt
,
586 * \return false if no resolve was needed
589 intel_miptree_all_slices_resolve_hiz(struct intel_context
*intel
,
590 struct intel_mipmap_tree
*mt
);
593 * \return false if no resolve was needed
596 intel_miptree_all_slices_resolve_depth(struct intel_context
*intel
,
597 struct intel_mipmap_tree
*mt
);
602 intel_miptree_downsample(struct intel_context
*intel
,
603 struct intel_mipmap_tree
*mt
);
606 intel_miptree_upsample(struct intel_context
*intel
,
607 struct intel_mipmap_tree
*mt
);
609 /* i915_mipmap_tree.c:
611 void i915_miptree_layout(struct intel_mipmap_tree
*mt
);
612 void i945_miptree_layout(struct intel_mipmap_tree
*mt
);
613 void brw_miptree_layout(struct intel_context
*intel
,
614 struct intel_mipmap_tree
*mt
);
616 void *intel_miptree_map_raw(struct intel_context
*intel
,
617 struct intel_mipmap_tree
*mt
);
619 void intel_miptree_unmap_raw(struct intel_context
*intel
,
620 struct intel_mipmap_tree
*mt
);
623 intel_miptree_map(struct intel_context
*intel
,
624 struct intel_mipmap_tree
*mt
,
636 intel_miptree_unmap(struct intel_context
*intel
,
637 struct intel_mipmap_tree
*mt
,
643 intel_hiz_exec(struct intel_context
*intel
, struct intel_mipmap_tree
*mt
,
644 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
)
646 /* Stub on i915. It would be nice if we didn't execute resolve code at all
652 intel_hiz_exec(struct intel_context
*intel
, struct intel_mipmap_tree
*mt
,
653 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);