1 /**************************************************************************
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #ifndef INTEL_MIPMAP_TREE_H
29 #define INTEL_MIPMAP_TREE_H
33 #include "intel_regions.h"
34 #include "intel_resolve_map.h"
40 /* A layer on top of the intel_regions code which adds:
42 * - Code to size and layout a region to hold a set of mipmaps.
43 * - Query to determine if a new image fits in an existing tree.
45 * - maybe able to remove refcounting from intel_region?
48 * The fixed mipmap layout of intel hardware where one offset
49 * specifies the position of all images in a mipmap hierachy
50 * complicates the implementation of GL texture image commands,
51 * compared to hardware where each image is specified with an
54 * In an ideal world, each texture object would be associated with a
55 * single bufmgr buffer or 2d intel_region, and all the images within
56 * the texture object would slot into the tree as they arrive. The
57 * reality can be a little messier, as images can arrive from the user
58 * with sizes that don't fit in the existing tree, or in an order
59 * where the tree layout cannot be guessed immediately.
61 * This structure encodes an idealized mipmap tree. The GL image
62 * commands build these where possible, otherwise store the images in
63 * temporary system buffers.
66 struct intel_resolve_map
;
67 struct intel_texture_image
;
70 * When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
71 * depthstencil-split-to-separate-stencil miptree, we'll normally make a
72 * tmeporary and recreate the kind of data requested by Mesa core, since we're
73 * satisfying some glGetTexImage() request or something.
75 * However, occasionally you want to actually map the miptree's current data
76 * without transcoding back. This flag to intel_miptree_map() gets you that.
78 #define BRW_MAP_DIRECT_BIT 0x80000000
80 struct intel_miptree_map
{
81 /** Bitfield of GL_MAP_READ_BIT, GL_MAP_WRITE_BIT, GL_MAP_INVALIDATE_BIT */
83 /** Region of interest for the map. */
85 /** Possibly malloced temporary buffer for the mapping. */
87 /** Possible pointer to a BO temporary for the mapping. */
89 /** Pointer to the start of (map_x, map_y) returned by the mapping. */
91 /** Stride of the mapping. */
95 * intel_mipmap_tree::singlesample_mt is temporary storage that persists
96 * only for the duration of the map.
98 bool singlesample_mt_is_tmp
;
102 * Describes the location of each texture image within a texture region.
104 struct intel_mipmap_level
106 /** Offset to this miptree level, used in computing x_offset. */
108 /** Offset to this miptree level, used in computing y_offset. */
114 * \brief Number of 2D slices in this miplevel.
116 * The exact semantics of depth varies according to the texture target:
117 * - For GL_TEXTURE_CUBE_MAP, depth is 6.
118 * - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
119 * identical for all miplevels in the texture.
120 * - For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its
121 * value, like width and height, varies with miplevel.
122 * - For other texture types, depth is 1.
127 * \brief List of 2D images in this mipmap level.
129 * This may be a list of cube faces, array slices in 2D array texture, or
130 * layers in a 3D texture. The list's length is \c depth.
132 struct intel_mipmap_slice
{
134 * \name Offset to slice
137 * Hardware formats are so diverse that that there is no unified way to
138 * compute the slice offsets, so we store them in this table.
140 * The (x, y) offset to slice \c s at level \c l relative the miptrees
143 * x = mt->level[l].slice[s].x_offset
144 * y = mt->level[l].slice[s].y_offset
151 * Mapping information. Persistent for the duration of
152 * intel_miptree_map/unmap on this slice.
154 struct intel_miptree_map
*map
;
159 * Enum for keeping track of the different MSAA layouts supported by Gen7.
161 enum intel_msaa_layout
164 * Ordinary surface with no MSAA.
166 INTEL_MSAA_LAYOUT_NONE
,
169 * Interleaved Multisample Surface. The additional samples are
170 * accommodated by scaling up the width and the height of the surface so
171 * that all the samples corresponding to a pixel are located at nearby
174 INTEL_MSAA_LAYOUT_IMS
,
177 * Uncompressed Multisample Surface. The surface is stored as a 2D array,
178 * with array slice n containing all pixel data for sample n.
180 INTEL_MSAA_LAYOUT_UMS
,
183 * Compressed Multisample Surface. The surface is stored as in
184 * INTEL_MSAA_LAYOUT_UMS, but there is an additional buffer called the MCS
185 * (Multisample Control Surface) buffer. Each pixel in the MCS buffer
186 * indicates the mapping from sample number to array slice. This allows
187 * the common case (where all samples constituting a pixel have the same
188 * color value) to be stored efficiently by just using a single array
191 INTEL_MSAA_LAYOUT_CMS
,
194 struct intel_mipmap_tree
196 /* Effectively the key:
201 * Generally, this is just the same as the gl_texture_image->TexFormat or
202 * gl_renderbuffer->Format.
204 * However, for textures and renderbuffers with packed depth/stencil formats
205 * on hardware where we want or need to use separate stencil, there will be
206 * two miptrees for storing the data. If the depthstencil texture or rb is
207 * MESA_FORMAT_Z32_FLOAT_X24S8, then mt->format will be
208 * MESA_FORMAT_Z32_FLOAT, otherwise for MESA_FORMAT_S8_Z24 objects it will be
209 * MESA_FORMAT_X8_Z24.
211 * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
212 * formats if the hardware lacks support for ETC1/ETC2. See @ref wraps_etc.
216 /** This variable stores the value of ETC compressed texture format */
217 gl_format etc_format
;
220 * The X offset of each image in the miptree must be aligned to this. See
221 * the "Alignment Unit Size" section of the BSpec.
223 unsigned int align_w
;
224 unsigned int align_h
; /**< \see align_w */
230 * Level zero image dimensions. These dimensions correspond to the
231 * physical layout of data in memory. Accordingly, they account for the
232 * extra width, height, and or depth that must be allocated in order to
233 * accommodate multisample formats, and they account for the extra factor
234 * of 6 in depth that must be allocated in order to accommodate cubemap
237 GLuint physical_width0
, physical_height0
, physical_depth0
;
244 * Level zero image dimensions. These dimensions correspond to the
245 * logical width, height, and depth of the region as seen by client code.
246 * Accordingly, they do not account for the extra width, height, and/or
247 * depth that must be allocated in order to accommodate multisample
248 * formats, nor do they account for the extra factor of 6 in depth that
249 * must be allocated in order to accommodate cubemap textures.
251 uint32_t logical_width0
, logical_height0
, logical_depth0
;
254 * For 1D array, 2D array, cube, and 2D multisampled surfaces on Gen7: true
255 * if the surface only contains LOD 0, and hence no space is for LOD's
256 * other than 0 in between array slices.
258 * Corresponds to the surface_array_spacing bit in gen7_surface_state.
260 bool array_spacing_lod0
;
263 * MSAA layout used by this buffer.
265 enum intel_msaa_layout msaa_layout
;
267 /* Derived from the above:
272 /* The 3DSTATE_CLEAR_PARAMS value associated with the last depth clear to
273 * this depth mipmap tree, if any.
275 uint32_t depth_clear_value
;
277 /* Includes image offset tables:
279 struct intel_mipmap_level level
[MAX_TEXTURE_LEVELS
];
281 /* The data is held here:
283 struct intel_region
*region
;
285 /* Offset into region bo where miptree starts:
290 * \brief Singlesample miptree.
292 * This is used under two cases.
294 * --- Case 1: As persistent singlesample storage for multisample window
295 * system front and back buffers ---
297 * Suppose that the window system FBO was created with a multisample
298 * config. Let `back_irb` be the `intel_renderbuffer` for the FBO's back
299 * buffer. Then `back_irb` contains two miptrees: a parent multisample
300 * miptree (back_irb->mt) and a child singlesample miptree
301 * (back_irb->mt->singlesample_mt). The DRM buffer shared with DRI2
302 * belongs to `back_irb->mt->singlesample_mt` and contains singlesample
303 * data. The singlesample miptree is created at the same time as and
304 * persists for the lifetime of its parent multisample miptree.
306 * When access to the singlesample data is needed, such as at
307 * eglSwapBuffers and glReadPixels, an automatic downsample occurs from
308 * `back_rb->mt` to `back_rb->mt->singlesample_mt` when necessary.
310 * This description of the back buffer applies analogously to the front
314 * --- Case 2: As temporary singlesample storage for mapping multisample
317 * Suppose the intel_miptree_map is called on a multisample miptree, `mt`,
318 * for which case 1 does not apply (that is, `mt` does not belong to
319 * a front or back buffer). Then `mt->singlesample_mt` is null at the
320 * start of the call. intel_miptree_map will create a temporary
321 * singlesample miptree, store it at `mt->singlesample_mt`, downsample from
322 * `mt` to `mt->singlesample_mt` if necessary, then map
323 * `mt->singlesample_mt`. The temporary miptree is later deleted during
324 * intel_miptree_unmap.
326 struct intel_mipmap_tree
*singlesample_mt
;
329 * \brief A downsample is needed from this miptree to singlesample_mt.
331 bool need_downsample
;
336 * This is non-null only if HiZ is enabled for this miptree.
338 * \see intel_miptree_alloc_hiz()
340 struct intel_mipmap_tree
*hiz_mt
;
343 * \brief Map of miptree slices to needed resolves.
345 * This is used only when the miptree has a child HiZ miptree.
347 * Let \c mt be a depth miptree with HiZ enabled. Then the resolve map is
348 * \c mt->hiz_map. The resolve map of the child HiZ miptree, \c
349 * mt->hiz_mt->hiz_map, is unused.
351 struct intel_resolve_map hiz_map
;
354 * \brief Stencil miptree for depthstencil textures.
356 * This miptree is used for depthstencil textures and renderbuffers that
357 * require separate stencil. It always has the true copy of the stencil
358 * bits, regardless of mt->format.
360 * \see intel_miptree_map_depthstencil()
361 * \see intel_miptree_unmap_depthstencil()
363 struct intel_mipmap_tree
*stencil_mt
;
366 * \brief MCS miptree for multisampled textures.
368 * This miptree contains the "multisample control surface", which stores
369 * the necessary information to implement compressed MSAA on Gen7+
370 * (INTEL_MSAA_FORMAT_CMS).
372 struct intel_mipmap_tree
*mcs_mt
;
374 /* These are also refcounted:
381 struct intel_mipmap_tree
*intel_miptree_create(struct intel_context
*intel
,
389 bool expect_accelerated_upload
,
391 bool force_y_tiling
);
393 struct intel_mipmap_tree
*
394 intel_miptree_create_layout(struct intel_context
*intel
,
405 struct intel_mipmap_tree
*
406 intel_miptree_create_for_region(struct intel_context
*intel
,
409 struct intel_region
*region
);
411 struct intel_mipmap_tree
*
412 intel_miptree_create_for_dri2_buffer(struct intel_context
*intel
,
413 unsigned dri_attachment
,
415 uint32_t num_samples
,
416 struct intel_region
*region
);
419 * Create a miptree appropriate as the storage for a non-texture renderbuffer.
420 * The miptree has the following properties:
421 * - The target is GL_TEXTURE_2D.
422 * - There are no levels other than the base level 0.
425 struct intel_mipmap_tree
*
426 intel_miptree_create_for_renderbuffer(struct intel_context
*intel
,
430 uint32_t num_samples
);
432 /** \brief Assert that the level and layer are valid for the miptree. */
434 intel_miptree_check_level_layer(struct intel_mipmap_tree
*mt
,
438 assert(level
>= mt
->first_level
);
439 assert(level
<= mt
->last_level
);
440 assert(layer
< mt
->level
[level
].depth
);
443 int intel_miptree_pitch_align (struct intel_context
*intel
,
444 struct intel_mipmap_tree
*mt
,
448 void intel_miptree_reference(struct intel_mipmap_tree
**dst
,
449 struct intel_mipmap_tree
*src
);
451 void intel_miptree_release(struct intel_mipmap_tree
**mt
);
453 /* Check if an image fits an existing mipmap tree layout
455 bool intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
456 struct gl_texture_image
*image
);
459 intel_miptree_get_image_offset(struct intel_mipmap_tree
*mt
,
460 GLuint level
, GLuint slice
,
461 GLuint
*x
, GLuint
*y
);
464 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
465 int *width
, int *height
, int *depth
);
468 intel_miptree_get_tile_offsets(struct intel_mipmap_tree
*mt
,
469 GLuint level
, GLuint slice
,
473 void intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
476 GLuint w
, GLuint h
, GLuint d
);
478 void intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
480 GLuint img
, GLuint x
, GLuint y
);
483 intel_miptree_copy_teximage(struct intel_context
*intel
,
484 struct intel_texture_image
*intelImage
,
485 struct intel_mipmap_tree
*dst_mt
, bool invalidate
);
488 * Copy the stencil data from \c mt->stencil_mt->region to \c mt->region for
489 * the given miptree slice.
491 * \see intel_mipmap_tree::stencil_mt
494 intel_miptree_s8z24_scatter(struct intel_context
*intel
,
495 struct intel_mipmap_tree
*mt
,
500 * Copy the stencil data in \c mt->stencil_mt->region to \c mt->region for the
501 * given miptree slice.
503 * \see intel_mipmap_tree::stencil_mt
506 intel_miptree_s8z24_gather(struct intel_context
*intel
,
507 struct intel_mipmap_tree
*mt
,
512 intel_miptree_alloc_mcs(struct intel_context
*intel
,
513 struct intel_mipmap_tree
*mt
,
517 * \name Miptree HiZ functions
520 * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
521 * functions on a miptree without HiZ. In that case, each function is a no-op.
525 * \brief Allocate the miptree's embedded HiZ miptree.
526 * \see intel_mipmap_tree:hiz_mt
527 * \return false if allocation failed
531 intel_miptree_alloc_hiz(struct intel_context
*intel
,
532 struct intel_mipmap_tree
*mt
,
536 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
540 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
545 * \return false if no resolve was needed
548 intel_miptree_slice_resolve_hiz(struct intel_context
*intel
,
549 struct intel_mipmap_tree
*mt
,
554 * \return false if no resolve was needed
557 intel_miptree_slice_resolve_depth(struct intel_context
*intel
,
558 struct intel_mipmap_tree
*mt
,
563 * \return false if no resolve was needed
566 intel_miptree_all_slices_resolve_hiz(struct intel_context
*intel
,
567 struct intel_mipmap_tree
*mt
);
570 * \return false if no resolve was needed
573 intel_miptree_all_slices_resolve_depth(struct intel_context
*intel
,
574 struct intel_mipmap_tree
*mt
);
579 intel_miptree_downsample(struct intel_context
*intel
,
580 struct intel_mipmap_tree
*mt
);
583 intel_miptree_upsample(struct intel_context
*intel
,
584 struct intel_mipmap_tree
*mt
);
586 /* i915_mipmap_tree.c:
588 void i915_miptree_layout(struct intel_mipmap_tree
*mt
);
589 void i945_miptree_layout(struct intel_mipmap_tree
*mt
);
590 void brw_miptree_layout(struct intel_context
*intel
,
591 struct intel_mipmap_tree
*mt
);
593 void *intel_miptree_map_raw(struct intel_context
*intel
,
594 struct intel_mipmap_tree
*mt
);
596 void intel_miptree_unmap_raw(struct intel_context
*intel
,
597 struct intel_mipmap_tree
*mt
);
600 intel_miptree_map(struct intel_context
*intel
,
601 struct intel_mipmap_tree
*mt
,
613 intel_miptree_unmap(struct intel_context
*intel
,
614 struct intel_mipmap_tree
*mt
,
620 intel_hiz_exec(struct intel_context
*intel
, struct intel_mipmap_tree
*mt
,
621 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
)
623 /* Stub on i915. It would be nice if we didn't execute resolve code at all
629 intel_hiz_exec(struct intel_context
*intel
, struct intel_mipmap_tree
*mt
,
630 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);