1 /**************************************************************************
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
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28 #ifndef INTEL_MIPMAP_TREE_H
29 #define INTEL_MIPMAP_TREE_H
33 #include "intel_regions.h"
34 #include "intel_resolve_map.h"
40 /* A layer on top of the intel_regions code which adds:
42 * - Code to size and layout a region to hold a set of mipmaps.
43 * - Query to determine if a new image fits in an existing tree.
45 * - maybe able to remove refcounting from intel_region?
48 * The fixed mipmap layout of intel hardware where one offset
49 * specifies the position of all images in a mipmap hierachy
50 * complicates the implementation of GL texture image commands,
51 * compared to hardware where each image is specified with an
54 * In an ideal world, each texture object would be associated with a
55 * single bufmgr buffer or 2d intel_region, and all the images within
56 * the texture object would slot into the tree as they arrive. The
57 * reality can be a little messier, as images can arrive from the user
58 * with sizes that don't fit in the existing tree, or in an order
59 * where the tree layout cannot be guessed immediately.
61 * This structure encodes an idealized mipmap tree. The GL image
62 * commands build these where possible, otherwise store the images in
63 * temporary system buffers.
66 struct intel_resolve_map
;
67 struct intel_texture_image
;
69 struct intel_miptree_map
{
70 /** Bitfield of GL_MAP_READ_BIT, GL_MAP_WRITE_BIT, GL_MAP_INVALIDATE_BIT */
72 /** Region of interest for the map. */
74 /** Possibly malloced temporary buffer for the mapping. */
76 /** Possible pointer to a BO temporary for the mapping. */
78 /** Pointer to the start of (map_x, map_y) returned by the mapping. */
80 /** Stride of the mapping. */
84 * intel_mipmap_tree::singlesample_mt is temporary storage that persists
85 * only for the duration of the map.
87 bool singlesample_mt_is_tmp
;
91 * Describes the location of each texture image within a texture region.
93 struct intel_mipmap_level
95 /** Offset to this miptree level, used in computing x_offset. */
97 /** Offset to this miptree level, used in computing y_offset. */
103 * \brief Number of 2D slices in this miplevel.
105 * The exact semantics of depth varies according to the texture target:
106 * - For GL_TEXTURE_CUBE_MAP, depth is 6.
107 * - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
108 * identical for all miplevels in the texture.
109 * - For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its
110 * value, like width and height, varies with miplevel.
111 * - For other texture types, depth is 1.
116 * \brief List of 2D images in this mipmap level.
118 * This may be a list of cube faces, array slices in 2D array texture, or
119 * layers in a 3D texture. The list's length is \c depth.
121 struct intel_mipmap_slice
{
123 * \name Offset to slice
126 * Hardware formats are so diverse that that there is no unified way to
127 * compute the slice offsets, so we store them in this table.
129 * The (x, y) offset to slice \c s at level \c l relative the miptrees
132 * x = mt->level[l].slice[s].x_offset
133 * y = mt->level[l].slice[s].y_offset
140 * Mapping information. Persistent for the duration of
141 * intel_miptree_map/unmap on this slice.
143 struct intel_miptree_map
*map
;
148 * Enum for keeping track of the different MSAA layouts supported by Gen7.
150 enum intel_msaa_layout
153 * Ordinary surface with no MSAA.
155 INTEL_MSAA_LAYOUT_NONE
,
158 * Interleaved Multisample Surface. The additional samples are
159 * accommodated by scaling up the width and the height of the surface so
160 * that all the samples corresponding to a pixel are located at nearby
163 INTEL_MSAA_LAYOUT_IMS
,
166 * Uncompressed Multisample Surface. The surface is stored as a 2D array,
167 * with array slice n containing all pixel data for sample n.
169 INTEL_MSAA_LAYOUT_UMS
,
172 * Compressed Multisample Surface. The surface is stored as in
173 * INTEL_MSAA_LAYOUT_UMS, but there is an additional buffer called the MCS
174 * (Multisample Control Surface) buffer. Each pixel in the MCS buffer
175 * indicates the mapping from sample number to array slice. This allows
176 * the common case (where all samples constituting a pixel have the same
177 * color value) to be stored efficiently by just using a single array
180 INTEL_MSAA_LAYOUT_CMS
,
183 struct intel_mipmap_tree
185 /* Effectively the key:
190 * Generally, this is just the same as the gl_texture_image->TexFormat or
191 * gl_renderbuffer->Format.
193 * However, for textures and renderbuffers with packed depth/stencil formats
194 * on hardware where we want or need to use separate stencil, there will be
195 * two miptrees for storing the data. If the depthstencil texture or rb is
196 * MESA_FORMAT_Z32_FLOAT_X24S8, then mt->format will be
197 * MESA_FORMAT_Z32_FLOAT, otherwise for MESA_FORMAT_S8_Z24 objects it will be
198 * MESA_FORMAT_X8_Z24.
200 * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
201 * formats if the hardware lacks support for ETC1/ETC2. See @ref wraps_etc.
205 /** This variable stores the value of ETC compressed texture format */
206 gl_format etc_format
;
209 * The X offset of each image in the miptree must be aligned to this. See
210 * the "Alignment Unit Size" section of the BSpec.
212 unsigned int align_w
;
213 unsigned int align_h
; /**< \see align_w */
218 GLuint width0
, height0
, depth0
; /**< Level zero image dimensions */
224 * If num_samples > 0, then singlesample_width0 is the value that width0
225 * would have if instead a singlesample miptree were created. Note that,
226 * for non-interleaved msaa layouts, the two values are the same.
228 * If num_samples == 0, then singlesample_width0 is undefined.
230 uint32_t singlesample_width0
;
232 /** \see singlesample_width0 */
233 uint32_t singlesample_height0
;
236 * For 1D array, 2D array, cube, and 2D multisampled surfaces on Gen7: true
237 * if the surface only contains LOD 0, and hence no space is for LOD's
238 * other than 0 in between array slices.
240 * Corresponds to the surface_array_spacing bit in gen7_surface_state.
242 bool array_spacing_lod0
;
245 * MSAA layout used by this buffer.
247 enum intel_msaa_layout msaa_layout
;
249 /* Derived from the above:
254 /* The 3DSTATE_CLEAR_PARAMS value associated with the last depth clear to
255 * this depth mipmap tree, if any.
257 uint32_t depth_clear_value
;
259 /* Includes image offset tables:
261 struct intel_mipmap_level level
[MAX_TEXTURE_LEVELS
];
263 /* The data is held here:
265 struct intel_region
*region
;
267 /* Offset into region bo where miptree starts:
272 * \brief Singlesample miptree.
274 * This is used under two cases.
276 * --- Case 1: As persistent singlesample storage for multisample window
277 * system front and back buffers ---
279 * Suppose that the window system FBO was created with a multisample
280 * config. Let `back_irb` be the `intel_renderbuffer` for the FBO's back
281 * buffer. Then `back_irb` contains two miptrees: a parent multisample
282 * miptree (back_irb->mt) and a child singlesample miptree
283 * (back_irb->mt->singlesample_mt). The DRM buffer shared with DRI2
284 * belongs to `back_irb->mt->singlesample_mt` and contains singlesample
285 * data. The singlesample miptree is created at the same time as and
286 * persists for the lifetime of its parent multisample miptree.
288 * When access to the singlesample data is needed, such as at
289 * eglSwapBuffers and glReadPixels, an automatic downsample occurs from
290 * `back_rb->mt` to `back_rb->mt->singlesample_mt` when necessary.
292 * This description of the back buffer applies analogously to the front
296 * --- Case 2: As temporary singlesample storage for mapping multisample
299 * Suppose the intel_miptree_map is called on a multisample miptree, `mt`,
300 * for which case 1 does not apply (that is, `mt` does not belong to
301 * a front or back buffer). Then `mt->singlesample_mt` is null at the
302 * start of the call. intel_miptree_map will create a temporary
303 * singlesample miptree, store it at `mt->singlesample_mt`, downsample from
304 * `mt` to `mt->singlesample_mt` if necessary, then map
305 * `mt->singlesample_mt`. The temporary miptree is later deleted during
306 * intel_miptree_unmap.
308 struct intel_mipmap_tree
*singlesample_mt
;
311 * \brief A downsample is needed from this miptree to singlesample_mt.
313 bool need_downsample
;
318 * This is non-null only if HiZ is enabled for this miptree.
320 * \see intel_miptree_alloc_hiz()
322 struct intel_mipmap_tree
*hiz_mt
;
325 * \brief Map of miptree slices to needed resolves.
327 * This is used only when the miptree has a child HiZ miptree.
329 * Let \c mt be a depth miptree with HiZ enabled. Then the resolve map is
330 * \c mt->hiz_map. The resolve map of the child HiZ miptree, \c
331 * mt->hiz_mt->hiz_map, is unused.
333 struct intel_resolve_map hiz_map
;
336 * \brief Stencil miptree for depthstencil textures.
338 * This miptree is used for depthstencil textures and renderbuffers that
339 * require separate stencil. It always has the true copy of the stencil
340 * bits, regardless of mt->format.
342 * \see intel_miptree_map_depthstencil()
343 * \see intel_miptree_unmap_depthstencil()
345 struct intel_mipmap_tree
*stencil_mt
;
348 * \brief MCS miptree for multisampled textures.
350 * This miptree contains the "multisample control surface", which stores
351 * the necessary information to implement compressed MSAA on Gen7+
352 * (INTEL_MSAA_FORMAT_CMS).
354 struct intel_mipmap_tree
*mcs_mt
;
357 * \brief The miptree contains uncompressed data that was originally
360 * On hardware that lacks support for ETC1/ETC2 textures, we do the following
361 * on calls to glCompressedTexImage2D() with an ETC1/ETC2 texture format:
362 * 1. Create a miptree whose format is a suitable uncompressed mesa format
363 * with the wraps_etc flag set.
364 * 2. Translate the ETC1/ETC2 data into uncompressed mesa format.
365 * 3. Store the uncompressed data into the miptree and discard the ETC1/ETC2
370 /* These are also refcounted:
377 struct intel_mipmap_tree
*intel_miptree_create(struct intel_context
*intel
,
385 bool expect_accelerated_upload
,
387 enum intel_msaa_layout msaa_layout
,
388 bool force_y_tiling
);
390 struct intel_mipmap_tree
*
391 intel_miptree_create_for_region(struct intel_context
*intel
,
394 struct intel_region
*region
);
396 struct intel_mipmap_tree
*
397 intel_miptree_create_for_dri2_buffer(struct intel_context
*intel
,
398 unsigned dri_attachment
,
400 uint32_t num_samples
,
401 struct intel_region
*region
);
404 * Create a miptree appropriate as the storage for a non-texture renderbuffer.
405 * The miptree has the following properties:
406 * - The target is GL_TEXTURE_2D.
407 * - There are no levels other than the base level 0.
410 struct intel_mipmap_tree
*
411 intel_miptree_create_for_renderbuffer(struct intel_context
*intel
,
415 uint32_t num_samples
);
417 /** \brief Assert that the level and layer are valid for the miptree. */
419 intel_miptree_check_level_layer(struct intel_mipmap_tree
*mt
,
423 assert(level
>= mt
->first_level
);
424 assert(level
<= mt
->last_level
);
425 assert(layer
< mt
->level
[level
].depth
);
428 int intel_miptree_pitch_align (struct intel_context
*intel
,
429 struct intel_mipmap_tree
*mt
,
433 void intel_miptree_reference(struct intel_mipmap_tree
**dst
,
434 struct intel_mipmap_tree
*src
);
436 void intel_miptree_release(struct intel_mipmap_tree
**mt
);
438 /* Check if an image fits an existing mipmap tree layout
440 bool intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
441 struct gl_texture_image
*image
);
444 intel_miptree_get_image_offset(struct intel_mipmap_tree
*mt
,
445 GLuint level
, GLuint slice
,
446 GLuint
*x
, GLuint
*y
);
449 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
450 int *width
, int *height
, int *depth
);
452 void intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
455 GLuint w
, GLuint h
, GLuint d
);
457 void intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
459 GLuint img
, GLuint x
, GLuint y
);
462 intel_miptree_copy_teximage(struct intel_context
*intel
,
463 struct intel_texture_image
*intelImage
,
464 struct intel_mipmap_tree
*dst_mt
);
467 * Copy the stencil data from \c mt->stencil_mt->region to \c mt->region for
468 * the given miptree slice.
470 * \see intel_mipmap_tree::stencil_mt
473 intel_miptree_s8z24_scatter(struct intel_context
*intel
,
474 struct intel_mipmap_tree
*mt
,
479 * Copy the stencil data in \c mt->stencil_mt->region to \c mt->region for the
480 * given miptree slice.
482 * \see intel_mipmap_tree::stencil_mt
485 intel_miptree_s8z24_gather(struct intel_context
*intel
,
486 struct intel_mipmap_tree
*mt
,
491 intel_miptree_alloc_mcs(struct intel_context
*intel
,
492 struct intel_mipmap_tree
*mt
,
496 * \name Miptree HiZ functions
499 * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
500 * functions on a miptree without HiZ. In that case, each function is a no-op.
504 * \brief Allocate the miptree's embedded HiZ miptree.
505 * \see intel_mipmap_tree:hiz_mt
506 * \return false if allocation failed
510 intel_miptree_alloc_hiz(struct intel_context
*intel
,
511 struct intel_mipmap_tree
*mt
,
515 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
519 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
524 * \return false if no resolve was needed
527 intel_miptree_slice_resolve_hiz(struct intel_context
*intel
,
528 struct intel_mipmap_tree
*mt
,
533 * \return false if no resolve was needed
536 intel_miptree_slice_resolve_depth(struct intel_context
*intel
,
537 struct intel_mipmap_tree
*mt
,
542 * \return false if no resolve was needed
545 intel_miptree_all_slices_resolve_hiz(struct intel_context
*intel
,
546 struct intel_mipmap_tree
*mt
);
549 * \return false if no resolve was needed
552 intel_miptree_all_slices_resolve_depth(struct intel_context
*intel
,
553 struct intel_mipmap_tree
*mt
);
558 intel_miptree_downsample(struct intel_context
*intel
,
559 struct intel_mipmap_tree
*mt
);
562 intel_miptree_upsample(struct intel_context
*intel
,
563 struct intel_mipmap_tree
*mt
);
565 /* i915_mipmap_tree.c:
567 void i915_miptree_layout(struct intel_mipmap_tree
*mt
);
568 void i945_miptree_layout(struct intel_mipmap_tree
*mt
);
569 void brw_miptree_layout(struct intel_context
*intel
,
570 struct intel_mipmap_tree
*mt
);
573 intel_miptree_map(struct intel_context
*intel
,
574 struct intel_mipmap_tree
*mt
,
586 intel_miptree_unmap(struct intel_context
*intel
,
587 struct intel_mipmap_tree
*mt
,
593 intel_hiz_exec(struct intel_context
*intel
, struct intel_mipmap_tree
*mt
,
594 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
)
596 /* Stub on i915. It would be nice if we didn't execute resolve code at all
602 intel_hiz_exec(struct intel_context
*intel
, struct intel_mipmap_tree
*mt
,
603 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);