src/mesa/drivers/dri/intel/intel_mipmap_tree.h

   1 /**************************************************************************
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   3  * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
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  11  * permit persons to whom the Software is furnished to do so, subject to
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  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
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  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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  27
  28 #ifndef INTEL_MIPMAP_TREE_H
  29 #define INTEL_MIPMAP_TREE_H
  30
  31 #include <assert.h>
  32
  33 #include "intel_regions.h"
  34 #include "intel_resolve_map.h"
  35
  36 #ifdef __cplusplus
  37 extern "C" {
  38 #endif
  39
  40 /* A layer on top of the intel_regions code which adds:
  41  *
  42  * - Code to size and layout a region to hold a set of mipmaps.
  43  * - Query to determine if a new image fits in an existing tree.
  44  * - More refcounting
  45  *     - maybe able to remove refcounting from intel_region?
  46  * - ?
  47  *
  48  * The fixed mipmap layout of intel hardware where one offset
  49  * specifies the position of all images in a mipmap hierachy
  50  * complicates the implementation of GL texture image commands,
  51  * compared to hardware where each image is specified with an
  52  * independent offset.
  53  *
  54  * In an ideal world, each texture object would be associated with a
  55  * single bufmgr buffer or 2d intel_region, and all the images within
  56  * the texture object would slot into the tree as they arrive.  The
  57  * reality can be a little messier, as images can arrive from the user
  58  * with sizes that don't fit in the existing tree, or in an order
  59  * where the tree layout cannot be guessed immediately.
  60  *
  61  * This structure encodes an idealized mipmap tree.  The GL image
  62  * commands build these where possible, otherwise store the images in
  63  * temporary system buffers.
  64  */
  65
  66 struct intel_resolve_map;
  67 struct intel_texture_image;
  68
  69 struct intel_miptree_map {
  70    /** Bitfield of GL_MAP_READ_BIT, GL_MAP_WRITE_BIT, GL_MAP_INVALIDATE_BIT */
  71    GLbitfield mode;
  72    /** Region of interest for the map. */
  73    int x, y, w, h;
  74    /** Possibly malloced temporary buffer for the mapping. */
  75    void *buffer;
  76    /** Possible pointer to a BO temporary for the mapping. */
  77    drm_intel_bo *bo;
  78    /** Pointer to the start of (map_x, map_y) returned by the mapping. */
  79    void *ptr;
  80    /** Stride of the mapping. */
  81    int stride;
  82 };
  83
  84 /**
  85  * Describes the location of each texture image within a texture region.
  86  */
  87 struct intel_mipmap_level
  88 {
  89    /** Offset to this miptree level, used in computing x_offset. */
  90    GLuint level_x;
  91    /** Offset to this miptree level, used in computing y_offset. */
  92    GLuint level_y;
  93    GLuint width;
  94    GLuint height;
  95
  96    /**
  97     * \brief Number of 2D slices in this miplevel.
  98     *
  99     * The exact semantics of depth varies according to the texture target:
 100     *    - For GL_TEXTURE_CUBE_MAP, depth is 6.
 101     *    - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
 102     *      identical for all miplevels in the texture.
 103     *    - For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its
 104     *      value, like width and height, varies with miplevel.
 105     *    - For other texture types, depth is 1.
 106     */
 107    GLuint depth;
 108
 109    /**
 110     * \brief List of 2D images in this mipmap level.
 111     *
 112     * This may be a list of cube faces, array slices in 2D array texture, or
 113     * layers in a 3D texture. The list's length is \c depth.
 114     */
 115    struct intel_mipmap_slice {
 116       /**
 117        * \name Offset to slice
 118        * \{
 119        *
 120        * Hardware formats are so diverse that that there is no unified way to
 121        * compute the slice offsets, so we store them in this table.
 122        *
 123        * The (x, y) offset to slice \c s at level \c l relative the miptrees
 124        * base address is
 125        * \code
 126        *     x = mt->level[l].slice[s].x_offset
 127        *     y = mt->level[l].slice[s].y_offset
 128        */
 129       GLuint x_offset;
 130       GLuint y_offset;
 131       /** \} */
 132
 133       /**
 134        * Pointer to mapping information, present across
 135        * intel_tex_image_map()/unmap of the slice.
 136        */
 137       struct intel_miptree_map *map;
 138    } *slice;
 139 };
 140
 141 /**
 142  * Enum for keeping track of the different MSAA layouts supported by Gen7.
 143  */
 144 enum intel_msaa_layout
 145 {
 146    /**
 147     * Ordinary surface with no MSAA.
 148     */
 149    INTEL_MSAA_LAYOUT_NONE,
 150
 151    /**
 152     * Interleaved Multisample Surface.  The additional samples are
 153     * accommodated by scaling up the width and the height of the surface so
 154     * that all the samples corresponding to a pixel are located at nearby
 155     * memory locations.
 156     */
 157    INTEL_MSAA_LAYOUT_IMS,
 158
 159    /**
 160     * Uncompressed Multisample Surface.  The surface is stored as a 2D array,
 161     * with array slice n containing all pixel data for sample n.
 162     */
 163    INTEL_MSAA_LAYOUT_UMS,
 164
 165    /**
 166     * Compressed Multisample Surface.  The surface is stored as in
 167     * INTEL_MSAA_LAYOUT_UMS, but there is an additional buffer called the MCS
 168     * (Multisample Control Surface) buffer.  Each pixel in the MCS buffer
 169     * indicates the mapping from sample number to array slice.  This allows
 170     * the common case (where all samples constituting a pixel have the same
 171     * color value) to be stored efficiently by just using a single array
 172     * slice.
 173     */
 174    INTEL_MSAA_LAYOUT_CMS,
 175 };
 176
 177 struct intel_mipmap_tree
 178 {
 179    /* Effectively the key:
 180     */
 181    GLenum target;
 182
 183    /**
 184     * Generally, this is just the same as the gl_texture_image->TexFormat or
 185     * gl_renderbuffer->Format.
 186     *
 187     * However, for textures and renderbuffers with packed depth/stencil formats
 188     * on hardware where we want or need to use separate stencil, there will be
 189     * two miptrees for storing the data.  If the depthstencil texture or rb is
 190     * MESA_FORMAT_Z32_FLOAT_X24S8, then mt->format will be
 191     * MESA_FORMAT_Z32_FLOAT, otherwise for MESA_FORMAT_S8_Z24 objects it will be
 192     * MESA_FORMAT_X8_Z24.
 193     */
 194    gl_format format;
 195
 196    /**
 197     * The X offset of each image in the miptree must be aligned to this. See
 198     * the "Alignment Unit Size" section of the BSpec.
 199     */
 200    unsigned int align_w;
 201    unsigned int align_h; /**< \see align_w */
 202
 203    GLuint first_level;
 204    GLuint last_level;
 205
 206    GLuint width0, height0, depth0; /**< Level zero image dimensions */
 207    GLuint cpp;
 208    GLuint num_samples;
 209    bool compressed;
 210
 211    /**
 212     * For 1D array, 2D array, cube, and 2D multisampled surfaces on Gen7: true
 213     * if the surface only contains LOD 0, and hence no space is for LOD's
 214     * other than 0 in between array slices.
 215     *
 216     * Corresponds to the surface_array_spacing bit in gen7_surface_state.
 217     */
 218    bool array_spacing_lod0;
 219
 220    /**
 221     * MSAA layout used by this buffer.
 222     */
 223    enum intel_msaa_layout msaa_layout;
 224
 225    /* Derived from the above:
 226     */
 227    GLuint total_width;
 228    GLuint total_height;
 229
 230    /* The 3DSTATE_CLEAR_PARAMS value associated with the last depth clear to
 231     * this depth mipmap tree, if any.
 232     */
 233    uint32_t depth_clear_value;
 234
 235    /* Includes image offset tables:
 236     */
 237    struct intel_mipmap_level level[MAX_TEXTURE_LEVELS];
 238
 239    /* The data is held here:
 240     */
 241    struct intel_region *region;
 242
 243    /* Offset into region bo where miptree starts:
 244     */
 245    uint32_t offset;
 246
 247    /**
 248     * \brief HiZ miptree
 249     *
 250     * This is non-null only if HiZ is enabled for this miptree.
 251     *
 252     * \see intel_miptree_alloc_hiz()
 253     */
 254    struct intel_mipmap_tree *hiz_mt;
 255
 256    /**
 257     * \brief Map of miptree slices to needed resolves.
 258     *
 259     * This is used only when the miptree has a child HiZ miptree.
 260     *
 261     * Let \c mt be a depth miptree with HiZ enabled. Then the resolve map is
 262     * \c mt->hiz_map. The resolve map of the child HiZ miptree, \c
 263     * mt->hiz_mt->hiz_map, is unused.
 264     */
 265    struct intel_resolve_map hiz_map;
 266
 267    /**
 268     * \brief Stencil miptree for depthstencil textures.
 269     *
 270     * This miptree is used for depthstencil textures and renderbuffers that
 271     * require separate stencil.  It always has the true copy of the stencil
 272     * bits, regardless of mt->format.
 273     *
 274     * \see intel_miptree_map_depthstencil()
 275     * \see intel_miptree_unmap_depthstencil()
 276     */
 277    struct intel_mipmap_tree *stencil_mt;
 278
 279    /**
 280     * \brief MCS miptree for multisampled textures.
 281     *
 282     * This miptree contains the "multisample control surface", which stores
 283     * the necessary information to implement compressed MSAA on Gen7+
 284     * (INTEL_MSAA_FORMAT_CMS).
 285     */
 286    struct intel_mipmap_tree *mcs_mt;
 287
 288    /* These are also refcounted:
 289     */
 290    GLuint refcount;
 291 };
 292
 293
 294
 295 struct intel_mipmap_tree *intel_miptree_create(struct intel_context *intel,
 296                                                GLenum target,
 297                                                gl_format format,
 298                                                GLuint first_level,
 299                                                GLuint last_level,
 300                                                GLuint width0,
 301                                                GLuint height0,
 302                                                GLuint depth0,
 303                                                bool expect_accelerated_upload,
 304                                                GLuint num_samples,
 305                                                enum intel_msaa_layout msaa_layout);
 306
 307 struct intel_mipmap_tree *
 308 intel_miptree_create_for_region(struct intel_context *intel,
 309                                 GLenum target,
 310                                 gl_format format,
 311                                 struct intel_region *region);
 312
 313 /**
 314  * Create a miptree appropriate as the storage for a non-texture renderbuffer.
 315  * The miptree has the following properties:
 316  *     - The target is GL_TEXTURE_2D.
 317  *     - There are no levels other than the base level 0.
 318  *     - Depth is 1.
 319  */
 320 struct intel_mipmap_tree*
 321 intel_miptree_create_for_renderbuffer(struct intel_context *intel,
 322                                       gl_format format,
 323                                       uint32_t width,
 324                                       uint32_t height,
 325                                       uint32_t num_samples);
 326
 327 /** \brief Assert that the level and layer are valid for the miptree. */
 328 static inline void
 329 intel_miptree_check_level_layer(struct intel_mipmap_tree *mt,
 330                                 uint32_t level,
 331                                 uint32_t layer)
 332 {
 333    assert(level >= mt->first_level);
 334    assert(level <= mt->last_level);
 335    assert(layer < mt->level[level].depth);
 336 }
 337
 338 int intel_miptree_pitch_align (struct intel_context *intel,
 339                                struct intel_mipmap_tree *mt,
 340                                uint32_t tiling,
 341                                int pitch);
 342
 343 void intel_miptree_reference(struct intel_mipmap_tree **dst,
 344                              struct intel_mipmap_tree *src);
 345
 346 void intel_miptree_release(struct intel_mipmap_tree **mt);
 347
 348 /* Check if an image fits an existing mipmap tree layout
 349  */
 350 bool intel_miptree_match_image(struct intel_mipmap_tree *mt,
 351                                     struct gl_texture_image *image);
 352
 353 void
 354 intel_miptree_get_image_offset(struct intel_mipmap_tree *mt,
 355                                GLuint level, GLuint face, GLuint depth,
 356                                GLuint *x, GLuint *y);
 357
 358 void
 359 intel_miptree_get_dimensions_for_image(struct gl_texture_image *image,
 360                                        int *width, int *height, int *depth);
 361
 362 void intel_miptree_set_level_info(struct intel_mipmap_tree *mt,
 363                                   GLuint level,
 364                                   GLuint x, GLuint y,
 365                                   GLuint w, GLuint h, GLuint d);
 366
 367 void intel_miptree_set_image_offset(struct intel_mipmap_tree *mt,
 368                                     GLuint level,
 369                                     GLuint img, GLuint x, GLuint y);
 370
 371 void
 372 intel_miptree_copy_teximage(struct intel_context *intel,
 373                             struct intel_texture_image *intelImage,
 374                             struct intel_mipmap_tree *dst_mt);
 375
 376 /**
 377  * Copy the stencil data from \c mt->stencil_mt->region to \c mt->region for
 378  * the given miptree slice.
 379  *
 380  * \see intel_mipmap_tree::stencil_mt
 381  */
 382 void
 383 intel_miptree_s8z24_scatter(struct intel_context *intel,
 384                             struct intel_mipmap_tree *mt,
 385                             uint32_t level,
 386                             uint32_t slice);
 387
 388 /**
 389  * Copy the stencil data in \c mt->stencil_mt->region to \c mt->region for the
 390  * given miptree slice.
 391  *
 392  * \see intel_mipmap_tree::stencil_mt
 393  */
 394 void
 395 intel_miptree_s8z24_gather(struct intel_context *intel,
 396                            struct intel_mipmap_tree *mt,
 397                            uint32_t level,
 398                            uint32_t layer);
 399
 400 bool
 401 intel_miptree_alloc_mcs(struct intel_context *intel,
 402                         struct intel_mipmap_tree *mt,
 403                         GLuint num_samples);
 404
 405 /**
 406  * \name Miptree HiZ functions
 407  * \{
 408  *
 409  * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
 410  * functions on a miptree without HiZ. In that case, each function is a no-op.
 411  */
 412
 413 /**
 414  * \brief Allocate the miptree's embedded HiZ miptree.
 415  * \see intel_mipmap_tree:hiz_mt
 416  * \return false if allocation failed
 417  */
 418
 419 bool
 420 intel_miptree_alloc_hiz(struct intel_context *intel,
 421                         struct intel_mipmap_tree *mt,
 422                         GLuint num_samples);
 423
 424 void
 425 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree *mt,
 426                                           uint32_t level,
 427                                           uint32_t depth);
 428 void
 429 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree *mt,
 430                                             uint32_t level,
 431                                             uint32_t depth);
 432 void
 433 intel_miptree_all_slices_set_need_hiz_resolve(struct intel_mipmap_tree *mt);
 434
 435 void
 436 intel_miptree_all_slices_set_need_depth_resolve(struct intel_mipmap_tree *mt);
 437
 438 /**
 439  * \return false if no resolve was needed
 440  */
 441 bool
 442 intel_miptree_slice_resolve_hiz(struct intel_context *intel,
 443                                 struct intel_mipmap_tree *mt,
 444                                 unsigned int level,
 445                                 unsigned int depth);
 446
 447 /**
 448  * \return false if no resolve was needed
 449  */
 450 bool
 451 intel_miptree_slice_resolve_depth(struct intel_context *intel,
 452                                   struct intel_mipmap_tree *mt,
 453                                   unsigned int level,
 454                                   unsigned int depth);
 455
 456 /**
 457  * \return false if no resolve was needed
 458  */
 459 bool
 460 intel_miptree_all_slices_resolve_hiz(struct intel_context *intel,
 461                                      struct intel_mipmap_tree *mt);
 462
 463 /**
 464  * \return false if no resolve was needed
 465  */
 466 bool
 467 intel_miptree_all_slices_resolve_depth(struct intel_context *intel,
 468                                        struct intel_mipmap_tree *mt);
 469
 470 /**\}*/
 471
 472 /* i915_mipmap_tree.c:
 473  */
 474 void i915_miptree_layout(struct intel_mipmap_tree *mt);
 475 void i945_miptree_layout(struct intel_mipmap_tree *mt);
 476 void brw_miptree_layout(struct intel_context *intel,
 477                         struct intel_mipmap_tree *mt);
 478
 479 void
 480 intel_miptree_map(struct intel_context *intel,
 481                   struct intel_mipmap_tree *mt,
 482                   unsigned int level,
 483                   unsigned int slice,
 484                   unsigned int x,
 485                   unsigned int y,
 486                   unsigned int w,
 487                   unsigned int h,
 488                   GLbitfield mode,
 489                   void **out_ptr,
 490                   int *out_stride);
 491
 492 void
 493 intel_miptree_unmap(struct intel_context *intel,
 494                     struct intel_mipmap_tree *mt,
 495                     unsigned int level,
 496                     unsigned int slice);
 497
 498 #ifdef I915
 499 static inline void
 500 intel_hiz_exec(struct intel_context *intel, struct intel_mipmap_tree *mt,
 501                unsigned int level, unsigned int layer, enum gen6_hiz_op op)
 502 {
 503    /* Stub on i915.  It would be nice if we didn't execute resolve code at all
 504     * there.
 505     */
 506 }
 507 #else
 508 void
 509 intel_hiz_exec(struct intel_context *intel, struct intel_mipmap_tree *mt,
 510                unsigned int level, unsigned int layer, enum gen6_hiz_op op);
 511 #endif
 512
 513 #ifdef __cplusplus
 514 }
 515 #endif
 516
 517 #endif